AVAGO AFBR

AFBR-5905Z/5905AZ
ATM Multimode Fiber Transceivers
in 2 x 5 Package Style
Agilent AFBR-5905Z/5905AZ
ATM Multimode Fiber Transceivers
in 2 x 5 Package Style
Data Sheet
Data Sheet
Features
• Multisourced 2 x 5 pack
with MT-RJ receptacle
• Single +3.3 V power sup
Description
Transmitter Sections
• Wave solder and aqueo
The AFBR-5905Z family of
The transmitter section of the
process compatibility
transceivers from Agilent
AFBR-5905Z utilizes a 1300
• Full compliance with AT
provide the system designer Features
nm InGaAsP LED. This LED is
UNI SONET OC-3 multim
Description
with products to implement a
packaged in the optical
physical layer specifica
The AFBR-5905Z family of transceivers
from Avago
• Multisourced
2 x 5 portion
package style
with MT-RJ
range of solutions
for prosubassembly
of the
• RoHS compliant
vide the system designer with
products fiber
to implement
multimode
SONET aOC-3 receptacle
transmitter section. It is driven • Receiver output squelch
range of solutions for multimode
fiber
SONET
OC-3
(SDH STM-1) physical(SDH
layers• Single
by +3.3
a custom
silicon
V power
supplyIC which
enabled
STM-1) physical layers for ATM
These
for and
ATMother
andservices.
other services.
converts
differential
PECL
•
Wave
solder
and
aqueous
wash
process
compatibility
Applications
transceivers are all supplied in the new industry standard
signals, ECL referenced
These
transceivers
are all • Fulllogic
2 x 5 DIP style with a MT-RJ fiber
connector
interface.
compliance
with
ATM
Forum
UNI
SONET
• OC-3
Multimode fiber ATM ba
(shifted) to a +3.3 V supply,
supplied in the new industry multimode
fiber
physical
layer
specification
links
into
an
analog
LED
drive
ATM 2 km Backbone Links standard 2 x 5 DIP style with
current.
•
RoHS
compliant
•
Multimode fiber ATM w
a MT-RJ fiber connector
closet to desktop links
The AFBR-5905Z is a 1300 nm
product
with
optical
perforinterface.
• Receiver
output
squelch function enabled
Receiver
Sections
mance compliant with the SONET STS-3c (OC-3) Physical
km Backbone
The receiver section of the
Ordering Information
Layer Interface Specification.ATM
This2physical
layer isLinks
defined
Applications
AFBR-5905Z
utilizes
an
in the ATM Forum User-Network
Interface
(UNI)
SpeciThe AFBR-5905Z is a 1300 nm
The AFBR-5905Z 1300
• Multimode
backbone links
InGaAsfiber
PINATM
photodiode
fication Version 3.0. This document
the ANSI
product references
with optical
product is available fo
• Multimode
wiringsilicon
closet to desktop
links
coupledfiber
to aATM
custom
T1E1.2 specification for the performance
details of the interface
for with
2
compliant
production
orders thro
transimpedance
preamplifier
km multimode fiber backbone
links.
The
ATM
100
Mb/sthe SONET STS-3c (OC-3) Ordering Information
Agilent Component Fie
IC. It is packaged in the
125 MBd Physical Layer interface
is Layer
best implemented
Physical
Interface
Offices and Authorized
optical subassembly
portion
of
with the AFBR- 5903Z family
of
FDDI
Transceivers
which
The
AFBR-5905Z
1300 nm product
is available
for produc- world wid
Specification. This physical
Distributors
the
receiver.
are specified for use in this 4B/5B
encoded
physical
layer
tion
orders
through
the
Avago
Component
Field
Sales Oflayer is defined in the ATM
AFBR-5905Z = 0°C to
per the FDDI PMD standard. Forum User-Network Interface
fices and
Authorized
Distributors
world
wide.
This PIN/preamplifier combinaAFBR-5905AZ = -40°
(UNI) Specification Version 3.0.
tion is coupled
to a custom
AFBR-5905Z
=
0°C
to
+70°C
+85°C.
Transmitter Sections
This document references the
quantizer IC which provides
AFBR-5905AZ
= -40°Cshaping
to +85°C.for the
ANSI
T1E1.2 utilizes
specification
the final pulse
The transmitter section of the
AFBR-5905Z
a 1300 for
detailsinof
interface
logic output and the Signal
nm InGaAsP LED. This LED isthe
packaged
thethe
optical
sub- for
2 km multimode
Detect function. The Data
assembly portion of the transmitter
section. It is fiber
driven by
backbone
links. PECL logic
output is differential. The
a custom silicon IC which converts
differential
Signal Detect output is singlesignals, ECL referenced (shifted)
to
a
+3.3
V
supply,
into
an
The ATM 100 Mb/s-125 MBd
analog LED drive current. Physical Layer interface is best ended. Both Data and Signal
Detect outputs are PECL
implemented with the AFBRcompatible, ECL referenced
5903Z family of FDDI
(shifted) to a 3.3 V power
Transceivers which are
specified for use in this 4B/5B supply. The receiver outputs,
Data Out and Data Out Bar,
encoded physical layer per the
FDDI PMD standard.
Receiver Sections
2 x 5 DIP. The low profile of the Avago transceiver design
The receiver section of the AFBR-5905Z utilizes an InGaAs
complies with the maximum height allowed for the MT-RJ
PIN photodiode coupled to a custom silicon transimpedconnector
over theelectrical
entire length
the package.
ance
preamplifier
IC.
It
is
packaged
in
the
optical
subare squelched at Signal Detect
this package outline
and pin
andofoptical
assembly
portion
of
the
receiver.
This
PIN/preamplifier
Deassert. That is, when the
out are compliant The
with
the subassemblies
subassemblies
to ensure high
optical
utilize a high-volume
assembly
combination
coupled
to a custom
IC which
light input is
power
decreases
to quantizer
multisource
definition
of
the
2
immunity
to
external
process together with low-cost lens elementsEMI
which result
provides
the-38
finaldBm
pulseorshaping
for the xlogic
output
and
a typical
less, the
5 DIP.
The
low profile
of the building
fields. block.
in a cost-effective
the
Signal
Detect
function.
The
Data
output
is
differenSignal Detect Deasserts, i.e. the Agilent transceiver design
The outer housing is
electrical subassembly consists of a high volume multial.
The Detect
Signal Detect
output
Bothwith
Datathe The
Signal
output
goes istosingleended.
a
complies
maximum
electrically conductive and is
printed circuit board on which the IC and various
and
Signal
are PECL compatible,
ECL ref- fortilayer
PECL
lowDetect
state.outputs
This forces
height allowed
the MT-RJ
at reciever signal ground
passive circuit elements are attached.
erenced
(shifted)
to a 3.3Data
V power
The receiver
the receiver
outputs,
Out supply.
connector
over thesurface-mounted
entire
potential. The MT-RJ ports is
outputs,
DataOut
OutBar
and to
Data
Sigand Data
goOut
to Bar, are squelched
length of at
the
package.
The receiver section
includes
an internal
shield for the
molded
of filled
nonconductive
nal
Detect
Deassert.
That
is, when
input power
steady
PECL
levels
High
and the light
electrical and optical
subassemblies
ensure high imThe optical subassemblies
plastic
to providetomechanical
decreases
to a typical -38 dBm or less, the Signal Detect
Low respectively.
munity
to external strength
EMI fields.and electrical
utilize a high-volume
assembly
Deasserts, i.e. the Signal Detect output goes to a PECL low
process together with low-cost
isolation. The solder posts of
Package
The outer housing is electrically conductive and is at restate. This forces the receiver outputs, Data Out and Data
lens elements which result in a the Agilent design are isolated
ciever signal ground potential. The MT-RJ ports is molded
Out
to go to
steady PECL
levels High and Low respecTheBar
overall
package
concept
cost-effective building block.
from the internal circuit of the
of filled nonconductive plastic to provide mechanical
tively.
for the Agilent transceiver
transceiver.
The electrical subassembly
strength and electrical isolation. The solder posts of the
consists of three basic
consists of a high Avago
volume
The transceiver
is attached
Package
design are isolated
from the internal
circuit to
of the
elements; the two optical
multilayer printedtransceiver.
circuit
a printed circuit board with
subassemblies,
an
electrical
The overall package concept for the Avago transceiver
board on which the IC and
the ten signal pins and the
subassembly,
housingthe two
consists
of threeand
basicthe
elements;
optical subasThe transceiver is attached
to a printed
circuit board
various surface-mounted
two solder
posts which
exit with
as
illustrated
in
the
block
semblies, an electrical subassembly, and the housing as
the
ten
signal
pins
and
the
two
solder
posts
which
passive circuit elements are
the bottom of the housing. exit
Thethe
diagram in
inthe
Figure
illustrated
block1.
diagram in Figure 1.
bottom
of
the
housing.
The
two
solder
posts
provide
attached.
two solder posts provide the the
The package outline drawing
primary
mechanical
strengthmechanical
to withstandstrength
the loadstoimprimary
The package outline drawing and pin out
shown section
in
Theare
receiver
includes
and pin out are shown in
posed
on
the
transceiver
by
mating
with
the
MT-RJ conwithstand the loads imposed
Figures 2 and 3. The details of this package
outline and pin
for the fiber cables.
Figures 2 and 3. The details of an internal shield nectored
on the transceiver by mating
out are compliant with the multisource definition of the
with the MT-RJ connectored
fiber cables.
RX SUPPLY
DATA OUT
DATA OUT
QUANTIZER IC
SIGNAL
DETECT
RX GROUND
TX GROUND
DATA IN
DATA IN
LED DRIVER IC
TX SUPPLY
Figure 1. Block Diagram.
PIN PHOTODIODE
PRE-AMPLIFIER
SUBASSEMBLY
MT-RJ
RECEPTACLE
LED
OPTICAL
SUBASSEMBLY
13.97
(0.55)
MIN.
4.5 ±0.2
(0.177 ±0.008)
(PCB to OPTICS
CENTER LINE)
5.15
(0.20)
(PCB to OVERALL
RECEPTACLE CENTER
LINE)
FRONT VIEW
Case temperature
measurement point
13.59
(0.535)
MAX.
TOP VIEW
9.6
(0.378)
MAX.
10.16
(0.4)
Pin 1
7.59
(0.299)
8.6
(0.339)
12
(0.472)
1.778
(0.07)
+0
-0.2
(+000)
(0.024)
(-008)
Ø 0.61
Ø1.5
(0.059)
17.778
(0.7)
7.112
(0.28)
49.56 (1.951) REF.
37.56 (1.479) MAX.
9.8
(0.386)
MAX.
9.3
(0.366)
MAX.
SIDE VIEW
Ø 1.07
(0.042)
DIMENSIONS IN MILLIMETERS (INCHES)
NOTES:
1. THIS PAGE DESCRIBES THE MAXIMUM PACKAGE OUTLINE, MOUNTING STUDS, PINS AND THEIR RELATIONSHIPS TO EACH OTHER.
2. TOLERANCED TO ACCOMMODATE ROUND OR RECTANGULAR LEADS.
3. ALL 12 PINS AND POSTS ARE TO BE TREATED AS A SINGLE PATTERN.
4. THE MT-RJ HAS A 750 µm FIBER SPACING.
5. THE MT-RJ ALIGNMENT PINS ARE IN THE MODULE.
6. FOR SM MODULES, THE FERRULE WILL BE PC POLISHED (NOT ANGLED).
7. SEE MT-RJ TRANSCEIVER PIN OUT DIAGRAM FOR DETAILS.
Figure 2. Package Outline Drawing
3
3.3
(0.13)
RX
TX
Mounting Studs/
Solder Posts
Top
View
RECEIVER SIGNAL GROUND
RECEIVER POWER SUPPLY
SIGNAL DETECT
RECEIVER DATA OUT BAR
RECEIVER DATA OUT
o
o
o
o
o
1
2
3
4
5
10 o
9 o
8 o
7 o
o
6
TRANSMITTER DATA IN BAR
TRANSMITTER DATA IN
TRANSMITTER DISABLE (LASER BASED PRODUCTS ONLY)
TRANSMITTER SIGNAL GROUND
TRANSMITTER POWER SUPPLY
Figure 3. Pin Out Diagram.
Pin Descriptions:
No internal terminations are
based products connect this
provided. See recommended
pin to +3.3 V TTL logic high
Supply
VCC TX: module. To
Pin
1 Receiverconnect
Signal Ground
RX:to the circuit schematic. Pin 6 Transmitter Power
Directly
thisVEE
pin
“1”
to disable
Provide +3.3 V dc via
the recommended
transmitter
power
Directly
connect
thisplane.
pin to the receiver ground plane.
receiver
ground
enable
module connect
to TTL
Pin 5 Receiver Data Out
RD+:filter circuit.logic
supply
Locate
the“0”.
power supply filter circuit
low
Pin
Power
Supply
VCC RX:VCC
Pin2 2Receiver
Receiver
Power
Supply
as close as
possible to the VCC TX pin.
No internal terminations
are
Provide
+3.3 V dc via the recommended receiver power
RX:
Pin 9 Transmitter Data In TD+:
provided. See recommended
Pin 7 Transmitter Signal Ground VEE TX:
supply
filter
circuit.
Locate
the
power
supply
filter
circuit
Provide +3.3 V dc via the
circuit schematic.
No internal terminations are
Directly connect this pin to the transmitter ground plane.
asrecommended
close as possible
to the VCC
RX pin.
receiver
power
provided. See recommended
Pin 6 Transmitter Power
supply
Locate
Pin 8Supply
Transmitter Disable
TDIS: schematic.
Pin
3 Signalfilter
Detectcircuit.
SD:
circuit
VCC TX:
the
power
supply
filter
circuit
No internal connection. Optional feature for laser based
Normal optical input levels to the receiver result in a logic
10 Transmitter Data In Bar TD-:
asoutput.
close Low
as possible
to the
VCC
+3.3 in
V dcproducts
via the only. For Pin
laser based products connect this pin
“1”
optical input
levels
to theProvide
receiver result
internal
terminations
are
to +3.3 V TTL logicNo
high
“1” to disable
module. To
enable
aRX
faultpin.
condition indicated by a logic “0”recommended
output. This Sig-transmitter
power
supply
filter
circuit.
provided.
See
recommended
module
connect
to
TTL
logic
low
“0”.
nal
Detect
output
can
be
used
to
drive
a
PECL
input
on
Pin 3 Signal Detect SD:
power
supply filter
circuit schematic.
an upstream circuit, such as Signal DetectLocate
input orthe
Loss
of
Pin
9 Transmitter
Data In TD+:
Normal
optical
input
levels
to
circuit
as
close
as
possible
to
Signal-bar.
Mounting Studs/Solder Posts
the receiver result in a logic
the VCC TX pin. No internal terminations are provided. See recommended
Pin
4
Receiver
Data
Out
Bar
RD-:
circuit
schematic.
“1” output.
The mounting studs are
Pinrecommended
7 Transmitter Signal Ground
No
internal
terminations
are
provided.
See
provided
Low optical input levels to the
Pin 10 Transmitter Data
In Bar TD-:for transceiver
VEE TX:
circuit
schematic.
mechanical
attachment to the
receiver result in a fault
No internal terminations are provided. See recommended
Directly
connect
this
pin
to
the
circuit
board.
It is
condition
indicated
Pin
5 Receiver Data
Out RD+:by a logic
circuit schematic.
transmitter
ground
plane.
recommended
that
the holes in
“0”internal
output.
No
terminations are provided. See recommended
the
circuit
board
be
connected
Mounting
Posts
circuit
Pin 8 Transmitter Disable
TDIS: Studs/Solder
This schematic.
Signal Detect output can
to chassis ground.
be used to drive a PECL input No internal connection.
The mounting studs are provided for transceiver mechanion an upstream circuit, such
cal laser
attachment to the circuit board. It is recommended
Optional feature for
as Signal Detect input or Loss
that For
the holes
based products only.
laserin the circuit board be connected to chassis
of Signal-bar.
ground.
Pin
PinDescriptions:
1 Receiver Signal Ground VEE RX:
Pin 4 Receiver Data Out Bar RD-:
4
Application Information
Figure 4 was generated for the 1300 nm transceivers with
extensively in the ANSI and
a Avago fiber optic link model containing the current inIEEE committees, including the
dustry conventions for fiber cable specifications and the
ANSI T1E1.2 committee, to
draft ANSI T1E1.2. These optical parameters are reflected
establish the optical
in the guaranteed performance of the transceiver specifiperformance requirements for
cations in this data sheet. This same model has been used
various fiber optic interface
extensively in the ANSI and IEEE committees, including
standards. The cable
the ANSI T1E1.2 committee, to establish the optical perparameters used come from
formance requirements for various fiber optic interface
the ISO/IEC JTC1/SC 25/WG3
standards. The cable parameters used come from the ISO/
Generic Cabling for Customer
IEC JTC1/SC 25/WG3 Generic Cabling for Customer PremPremises per DIS 11801 docuises per DIS 11801 document and the EIA/TIA-568-A Comment and the EIA/TIA-568-A
mercial Building Telecommunications Cabling Standard
Commercial Building
per SP-2840.
Telecommunications Cabling
Standard per SP-2840.
12
HFBR-5905, 62.5/125 µm
10
OPTICAL POWER BUDGET (dB)
The Applications Engineering group is available to assist
pplication Information
125 µm fiber cables only. The
you with the technical understanding and design tradearea under the curves
he Applications
offs Engineering
associated with these transceivers. You can contact
represents the remaining OPB
roup is available
assist your
you Avago
themtothrough
sales representative. The folat any link length, which is
ith the technical
underlowing
information is provided to answer some of the
available for overcoming nontanding and design
trade-offs
most common
questions about the use of these parts.
fiber cable related losses.
ssociated with these transeivers. You can
contactOptical
them Power
Agilent
Transceiver
BudgetLED
versustechnology
Link Lengthhas
hrough your Agilent sales
produced 1300 nm LED
Optical Power Budget (OPB) is the available optical power
epresentative.
devices with lower aging
for a fiber optic link to accommodate fiber cable losses plus
characteristics than normally
he following information
is
losses due to in-line
connectors, splices, optical switches,
associated with these
rovided to answer
some of
and to provide
margin for link aging and unplanned losses
technologies in the industry.
he most common
questions
due to
cable plant reconfiguration or repair.
The industry convention is 1.5
bout the use of these parts.
dB agingOPB
for associated
1300 nm with
LEDs.
Figure 4 illustrates the predicted
the
ansceiver Optical
Power Budget
transceiver
specified inThe
this data sheet at the Beginning
ersus Link Length
1300
nm Agilent
LEDs areand
of Life (BOL). These curves
represent
the attenuation
specified
to
experience
less
chromatic
plus
modal
dispersion
losses
associated
with
ptical Power Budget (OPB) is
than
1
dB
of
aging
over
normal
the
62.5/125
µm
and
50/
125
µm
fiber
cables
only.
The
area
he available optical power for
commercial
equipment
mission
under
the
curves
represents
the
remaining
OPB
at
any
link
fiber optic link to
life
periods.
Contact
your
length,
which
is
available
for
overcoming
nonfiber
cable
ccommodate fiber cable losses
Agilent
sales has
representative
for
related
losses. Avago LED
technology
produced 1300
lus losses due
to in-line
additional
details.
nm
LED
devices
with
lower
aging
characteristics
than
noronnectors, splices, optical
associated with these
technologies
in the industry.
witches, and mally
to provide
Figure
4 was generated
for the
The
industry
convention
is
1.5
dB
aging
for
1300 nm
LEDs.
margin for link aging and
1300 nm transceivers
with
a
The
1300
nm
Avago
LEDs
are
specified
to
experience
less
nplanned losses due to cable
Agilent fiber optic link model
than 1 dB
aging over
normal commercial
equipment
lant reconfiguration
orofrepair.
containing
the current
industry
mission life periods. Contact
your
Avago
sales
representaconventions
for
fiber
cable
igure 4 illustrates the pretive for additional details.
icted OPB associated with the specifications and the draft
ANSI T1E1.2. These optical
ansceiver specified in this
parameters are reflected in the
ata sheet at the Beginning of
guaranteed performance of the
ife (BOL). These curves
transceiver specifications in
epresent the attenuation and
this data sheet. This same
hromatic plus modal
model has been used
ispersion losses associated
ith the 62.5/125 µm and 50/
8
HFBR-5905
50/125 µm
6
4
2
0
0.
3
0.5
1.0
1.5
2.0
2.5
FIBER OPTIC CABLE LENGTH (km)
Figure 4. Typical Optical Power Budget at BOL
versus Fiber Optic Cable Length.
Transceiver Signaling Operating Rate Range and BER
Performance
specification tables are derived from the values in Table
B1 of Annex B. They represent the worst case jitter contribution that the transceivers are allowed to make to the
overall system jitter without violating the Annex B allocation example. In practice, the typical contribution of the
Avago transceivers is well below these maximum allowed
Recommended Handling Precautions
amounts.
BIT ERROR RATE
For purposes of definition, the symbol (Baud) rate, also
called signaling rate, is the reciprocal of the symbol time.
Data rate (bits/sec) is the symbol rate divided by the enx 10-2
coding
factor
used toOperating
encode the data 1 (symbols/bit).
Transceiver
Signaling
When
used and
in 155
SONET OC-3 applications the
Rate Range
BERMb/s
Performance
Agilent recommends that
performance of the 1300 nm transceivers,1 xAFBR-5905
is
Recommended Handling
Precautions
10-3
normal
static precautions be
For purposes of definition, the
guaranteed to the full conditions listed in product specitaken
innormal
the handling
and
symbol (Baud) rate, also called
1 x 10-4
Avago
recommends
that
static precautions
be
fication tables. The transceivers may be used for other ap- HFBR-5905 SERIES
assembly
of
these
transceivers
signaling rate, is the reciprocal
taken
in
the
handling
and
assembly
of
these
transceiv1 x 10-5
plications at signaling rates different than 155
Mb/s with
to prevent
damage
which
of the symbol time. Data rate
1 x 10-6
ersCENTER
to prevent
damage
which may
be induced
bymay
electroOF SYMBOL
some variation in the link optical power budget.
Figure
1 x 10-7
be induced
by electrostatic
(bits/sec) is the symbol rate
static
discharge
(ESD).
The
AFBR-5905Z
series
of
transceiv1 x 10-8
5 gives an indication of the typical performance
of these
(ESD).
divided by the encoding factor
1 x 10-9
ers meet MIL-STD- discharge
883C Method
3015.4 Class 2 products.
1 x 10-10
products at different rates.
The
AFBR-5905Z
series
of data or
used to encode the data
1 x 10-11
Care should be used
to avoid
shorting the
receiver
1 x 10-12
transceivers
meet MIL-STD(symbols/bit).
These
transceivers can also be used for applications
which
signal
detect
outputs
directly
to
ground
without
proper
-6
0
4
-4
-2
2
883C Method 3015.4 Class 2
require
different
Bit
Error
Rate
(BER)
performance.
Figure
current
limiting
impedance.
When used in 155 Mb/s
RELATIVE INPUT OPTICAL POWER - dB
products.
6SONET
illustrates
the typical
trade-offthe
between link BER and the
OC-3
applications
CONDITIONS:
Solder
and
Wash
Process
receivers
input
optical
power
level.
Care Compatibility
should be used to avoid
performance of the 1300 nm
1. 125 MBd
2. PRBS 2 -1
shorting
the with
receiver
data or
transceivers, AFBR-5905 is
The transceivers are delivered
protective
process
3. CENTER OF SYMBOL SAMPLING
Transceiver
Jitter
4. T = +25C
signal
detect
outputs
directly
guaranteed
to Performance
the full
plugs inserted into the MT-RJ receptacle. This process
5. V = 3.3 V dc
INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
to ground
without proper
conditions
listed
product are designed 6.to
The
Avago 1300
nmintransceivers
operplug protects the optical
subassemblies
during wave solcurrent
limiting
specification
tables.
Figure
Bit Error
Relative
Receiver
ate
per the system
jitter allocations stated
in 6.Table
B1Rate
of vs. der
and aqueous wash processing andimpedance.
acts as a dust cover
7
A
CC
BIT ERROR RATE
TRANSCEIVER RELATIVE POWER BUDGET
AT CONSTANT BER (dB)
Input
Optical Power.
Annex
B of the draft ANSI
Revision
3 standard.
The
during shipping. These
are compatible with
The transceivers
may T1E1.2
be used
Soldertransceivers
and Wash Process
Transceiver
Jitter
Performance
Avago
1300
nm
transmitters
will
tolerate
the
worst
case
either industry standard
wave or hand solder processes.
for other applications at
Compatibility
input
electrical
jitter
allowedthan
in Annex The
B without
violatsignaling
rates
different
Agilent
1300 nm
The transceivers are delivered
Shipping Container
ing
the
worst
case
output
optical
jitter
requirements.
155 Mb/s with some variation
transceivers are designed
to
with protective process plugs
The
Avago
1300
nm receivers
the worst
in the
link
optical
power will tolerate
operate
percase
the system
jitter
The transceiver
is inserted
packaged into
in a shipping
container dethe MT-RJ
input
optical
jitter allowed
violating
budget.
Figure
5 gives in
anAnnex B without
allocations
stated signed
in Table
to B1
protect receptacle.
it from mechanical
and ESD
damage
This
process
plug
the
worst case
electrical jitter allowed.
TheBjitter
indication
of output
the typical
of Annex
of theduring
draft shipment
ANSI orprotects
storage. the optical
specifications
in the products
following 1300
nm transceiver
performancestated
of these
T1E1.2
Revision 3 standard.
subassemblies during wave
at different rates.
solder and aqueous wash
The Agilent 1300 nm
2.5
Recommended
1 x 10-2 the
processing and acts
as a dust Handling Precau
Transceiver Signaling
Operating will tolerate
transmitters
cover
during
shipping.
Rate
Range
and
BER
Performance
worst
case
input
electrical
2
Agilent recommends that
1 x 10-3
jitter
allowedthe
in Annex
B
normal
static precautions b
These
transceivers
are compatFor
purposes
of
definition,
1.5
taken in the handling and
ible
with
either
industry
symbol (Baud) without
rate, alsoviolating
called the 1worst
x 10-4
HFBR-5905 SERIES
1
case
optical jitter
assembly
of these transceiv
standard wave or hand
solder
signaling rate, is
theoutput
reciprocal
1 x 10-5
requirements.
to prevent damage which m
0.5
processes.
of the symbol time.
Data rate
1 x 10-6
CENTER OF SYMBOL
x 10-7
be induced by electrostatic
(bits/sec) is theThe
symbol
rate1300 nm 1receivers
Agilent
0
1 x 10-8
Shipping Container discharge (ESD).
divided by the encoding
factor
1 x 10-9
will tolerate
the worst
case
1 x 10-10
-0.5
The AFBR-5905Z
series of
The transceiver is packaged
in
used to encodeinput
the data
optical jitter allowed
in
1 x 10-11
1 x 10-12
transceivers
meet
MIL-STD
a
shipping
container
designed
(symbols/bit).
Annex
B
without
violating
the
-1
-6
0
4
-4
-2
2
0
25
50
75
100 125 150 175 200
883C Method 3015.4 Class
to
protect
it
from
mechanical
worst
case
output
electrical
SIGNAL RATEWhen
(MBd)
used in 155 Mb/s
RELATIVE INPUT OPTICAL POWER - dB
products.
and ESD damage during
jitter allowed.
SONET
OC-3 applications
the
CONDITIONS:
CONDITIONS:
shipment
or
storage.
1. PRBS 2 -1
Care should be used to avo
performance ofThe
the jitter
1300 specifications
nm
stated
1. 125 MBd
2. DATA SAMPLED AT CENTER OF DATA SYMBOL.
2. PRBS 2 -1
3. BER = 10
shorting the receiver data o
transceivers,
AFBR-5905
is
in
the
following
1300
nm
3. CENTER OF SYMBOL SAMPLING
4. T = +25 C
4. T = +25C
signal detect outputs direct
5. V = 3.3 V dc
guaranteed to the
full
transceiver
specification tables
5. V = 3.3 V dc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
6. INPUT
to ground without proper
conditions listed
productfrom the values
areinderived
inOPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
current limiting impedance.
Figure 5. Transceiver Relative
Optical Power tables.
specification
Table B1 of AnnexFigure
B. They
6. Bit Error Rate vs. Relative Receiver
Budget at Constant BER vs. Signaling Rate.
Input
Optical
Power.
represent
the
worst
case
jitter
The transceivers may be used
Solder and Wash Process
contribution
that the
Transceiver Jitter Performance
for
other
applications
at
Compatibility
These transceivers can also be
transceivers
are allowed to
signaling
rates
different
than
The
Agilent
1300
nm
used for applications which
The transceivers are deliver
make variation
to the overall system
155
Mb/sRate
with some
transceivers are designed to
require different Bit
Error
with protective process plu
jitter
without
violating
the
the link
power
operate per the system jitter
(BER) performance.inFigure
6 optical
inserted into the MT-RJ
Annex
B
allocation
example.
In
budget.
Figure 5 gives an
allocations stated in Table B1
illustrates the typical
trade-off
receptacle. This process plu
practice,
the
typical
indication
of the typical
of Annex B of the draft ANSI
between link BER and
the
protects the optical
contribution
of
the
Agilent
performance
these products T1E1.2 Revision 3 standard.
receivers input optical
power oftransceivers
subassemblies during wave
is
well
below
at different rates.
7
7
-6
A
CC
A
CC
Board Layout - Decoupling Circuit,
Ground Planes and Termination
Circuits
Board Layout - Hole Pattern
The Agilent transceiver
Board Layout - Decoupling Circuit, Ground Planes and
Board Layout - Holecomplies
Pattern with the circuit board
contiguous ground plane be
It is important to take care in
“Common Transceiver
Termination Circuits
The Avago
complies
with
the circuit
board
provided in the circuit
boardtransceiver
the layout of your circuit
Footprint”
hole
pattern
defined
“Common
Transceiver
Footprint”
hole
pattern
defined
in
directly
Itboard
is important
to take
care in the layout
of yourunder
circuitthe transceiver
to achieve
optimum
in the original multisource
the
original
multisource
announcement
which
defined
provide
a low inductance
board
to achievefrom
optimum
performance to
from
these transperformance
these
announcement which defined
the 2 x 5 package style.
is reproduced
ground
for signal return
ceivers.
Figure 7 Figure
provides7 aprovides
good example
of a schematic
transceivers.
the 2This
x 5drawing
package
style. Thisin Figure
9
with
the
addition
of
ANSI
Y14.5M
compliant
current.
This
recommendation
for
a power
supply decoupling
circuit that
works well
with
a good
example
of a schematic
drawing is reproduced in dimensioning
to
be
used
as a guide
in thethe
mechanical
is ina contiguous
keeping with good high
these
It issupply
further decoupling
recommended that
for aparts.
power
Figure
9 with
additionlayout
of of
your
circuit
board.
frequency
ground
provided
the circuit board
directlyboard
un- layout
circuitplane
that be
works
wellinwith
ANSI Y14.5M compliant
practices.
Figures
7 and 8
der
the transceiver
provide a low inductance
ground
for
these
parts. It istofurther
dimensioning to be used as a
show
two
recommended
signal
return current.
is in
keeping
recommended
thatThis
a recommendation
guide in the mechanical layout
termination
schemes.
with good high frequency board layout practices.
Figures
of your circuit board.
7 and 8 show two recommended termination schemes.
PHY DEVICE
VCC (+3.3 V)
TERMINATE AT
TRANSCEIVER INPUTS
Z = 50 Ω
VEE TX o
VCC TX o
o RD-
o RD+
TD+ o
LVPECL
Z = 50 Ω
TD+
130 Ω
6
o SD
7
o VCC RX
TD- o
8
1
2
3
4
TX
RX
9
o VEE RX
10
N/C o
100 Ω
TD-
1 µH
C2
130 Ω
VCC (+3.3 V)
C3
10 µF
VCC (+3.3 V)
1 µH
RD+
C1
5
Z = 50 Ω
100 Ω
LVPECL
RD-
Z = 50 Ω
130 Ω
130 Ω
Z = 50 Ω
VCC (+3.3 V)
130 Ω
SD
82 Ω
Note: C1 = C2 = C3 = 10 nF or 100 nF
Figure 7. Recommended Decoupling and Termination Circuits
7
TERMINATE AT
DEVICE INPUTS
TERMINATE AT
TRANSCEIVER INPUTS
PHY DEVICE
VCC (+3.3 V)
VCC (+3.3 V)
10 nF
130 Ω
130 Ω
Z = 50 Ω
TDLVPECL
VCC TX o
N/C o
82 Ω
3
4
5
VCC (+3.3 V)
VCC (+3.3 V)
1 µH
C3
VCC (+3.3 V)
10 nF
10 µF
130 Ω
RD+
LVPECL
Z = 50 Ω
RDVCC (+3.3 V)
Z = 50 Ω
82 Ω
10 nF
SD
82 Ω
Note: C1 = C2 = C3 = 10 nF or 100 nF
Figure 8. Alternative Termination Circuits
Spacing Of Front
Housing Leads Holes
TERMINATE AT DEVICE INPUTS
7.11
(0.28)
3.56
(0.14)
Ø 1.4 ±0.1
(0.055
±0.004)
Holes For
Housing
Leads
Ø 1.4 ±0.1
(0.055
±0.004)
10.16
13.97
(0.4)
(0.55)
MIN.
10.8
(0.425)
3.08
(0.121)
13.34 7.59
(0.525) (0.299)
3
(0.118)
3
(0.118)
6
(0.236)
27
(1.063)
4.57
(0.18)
17.78
(0.7)
9.59
(0.378)
1.778
(0.07)
2
(0.079)
Ø 2.29
(0.09)
7.112
(0.28)
3.08
(0.121)
Ø 0.81 ±0.1
(0.032 ±0.004)
DIMENSIONS IN MILLIMETERS (INCHES)
NOTES:
1. THIS FIGURE DESCRIBES THE RECOMMENDED CIRCUIT BOARD LAYOUT FOR THE MT-RJ TRANSCEIVER PLACED
AT .550 SPACING.
2. THE HATCHED AREAS ARE KEEP-OUT AREAS RESERVED FOR HOUSING STANDOFFS. NO METAL TRACES OR
GROUND CONNECTION IN KEEP-OUT AREAS.
3. 10 PIN MODULE REQUIRES ONLY 16 PCB HOLES, INCLUDING 4 PACKAGE GROUNDING TAB HOLES CONNECTED
TO SIGNAL GROUND.
4. THE SOLDER POSTS SHOULD BE SOLDERED TO CHASSIS GROUND FOR MECHANICAL INTEGRITY AND TO
ENSURE FOOTPRINT COMPATIBILITY WITH OTHER SFF TRANSCEIVERS.
Figure 9. Recommended Board Layout Hole Pattern
8
82 Ω
130 Ω
Z = 50 Ω
Ø 1.4 ±0.1
(0.055
±0.004)
130 Ω
1 µH
C1
KEEP OUT AREA
FOR PORT PLUG
7
(0.276)
TD+
82 Ω
C2
o RD+
2
6
o RD-
o VEE RX
1
7
o SD
TX
RX
8
TD+ o
TD- o
9
o VCC RX
10
VEE TX o
Z = 50 Ω
Regulatory
RegulatoryCompliance
Compliance
Transceiver
and Performance
Qualification
Data
The second case to
considerReliability
is
Electromagnetic
Interference
(EMI)
static
discharges
to
the
Thesetransceiver
transceiver
products
are
Mosthave
equipment
designs
These
products
are intended
to enable comThe 2 x 5 transceivers
passed Avago
reliability and
exterior
ofcomthe equipment
intended
to enable
commercial
utilizing
this and
higharespeed
trans-onmercial
system
designers
to develop equipment
that
performance qualification
testing
undergoing
chassis
containinggoing
the quality and reliability
system
develop regulations
ceiver from
AgilentDetails
will be
plies
withdesigners
the variousto
international
governing
monitoring.
are availtransceiver
parts. able
To the
equipment of
that
compliesTechnology
with
required
to meet the requirecertification
Information
Equipment. See
from your Avago
sales representative.
extentAdditional
that the MT-RJ
theRegulatory
various international
ments of FCC in the United
the
Compliance Table for details.
connector
is exposed
to the Support
Applications
Materials
regulationsis governing
certificaStates,
CENELEC EN55022
information
available from
your Avago sales represenoutside of the equipment
tion of Information Technology
(CISPR 22) in Europe and
tative.
Avago Component Field Sales Office
chassis it may be Contact
subject your
to localVCCI
Equipment. See the Regulatory
in Japan.
for
information
on
how to obtain evaluation boards for
whatever ESD system level test
Electrostatic
Discharge
(ESD)
Compliance
Table for
details.
This product is suitable for
the 2 x 5 transceivers.
criteria that the equipment
is
Additional information is
use in designs ranging from a
There are two design cases in which immunity
to
ESD
intended to meet.
available from your Agilent
Electromagnetic Interference
(EMI)
desktop computer
with a single
damage is important. The first case is during handling of
sales representative.
Transceiver
Reliability
and
transceiver to a concentrator
the transceiver prior to mounting it on the
circuit board.
It
Most equipment designs utilizing this high speed transData
or switch product with a large
isElectrostatic
important to
use normal
ESD handlingPerformance
precautionsQualification
for
Discharge
(ESD)
ceiver from Avago will be required to meet the requirenumber of transceivers.
ESD sensitive devices. These pre-cautions
include
using
The 2 x 5 transceivers
mentshave
of FCC in the United States, CENELEC EN55022
There are two design cases in
grounded wrist straps, work benches, and
floor
mats
in
passed Agilent reliability
and
(CISPR 22)
in Europe
and VCCI in Japan. This product is
which immunity to ESD
Immunity
ESD controlled areas. The second case toperformance
consider is static
qualification
suitable
for
use
in
designs
ranging from a desktop comdamage is important.
Equipment utilizing these
discharges to the exterior of the equipment
chassis
testing
andconare undergoing
puter with a single transceiver to a concentrator or switch
The first
is during
transceivers will be subject to
taining
the case
transceiver
parts. To the extent
that the
MT- and
ongoing
quality
reliability
product
with a large number of transceivers.
handling
ofisthe
transceiver
radio-frequency
RJ
connector
exposed
to the outside of
the
equipment
monitoring. Details are availprior to
mounting
it on
electromagnetic fields in some
chassis
it may
be subject
to the
whatever ESD
system
level
able from your Agilent
sales
Immunity
circuit
board.
It is
important
environments. These
test
criteria
that the
equipment
is intended
to
meet.
representative.
Equipment utilizing
these transceivers
be subject to
to use normal ESD handling
transceivers
have will
a high
Applications Support radio-frequency
Materials
electromagnetic
fields fields.
in some environprecautions for ESD sensitive
immunity to such
These transceivers have a high immunity to such
devices. These pre-cautions
Contact your localments.
Agilent
fields.
include using grounded wrist
Component Field Sales Office
straps, work benches, and floor for information on how to
mats in ESD controlled areas.
obtain evaluation boards for
the 2 x 5 transceivers.
Regulatory Compliance Table
Feature
Test Method
Performance
Electrostatic Discharge
(ESD) to the Electrical Pins
Electrostatic Discharge
(ESD) to the MT-RJ Receptacle
Electromagnetic
Interference (EMI)
MIL-STD-883C
Meets Class 2 (2000 to 3999 Volts).
Withstand up to 2200 V applied between electrical pins.
Typically withstand at least 25 kV without damage when the MT-RJ
Connector Receptacle is contacted by a Human Body Model probe.
Typically provide a 10 dB margin to the noted standards, however, it should
be noted that final margin depends on the customer's board and chassis
Immunity
Eye Safety
9
Variation of
IEC 801-2
FCC Class B
CENELEC CEN55022 VCCI
Class 2
Variation of IEC 61000-4-3
AEL Class 1
EN60825-1 (+A11)
design.
Typically show no measurable effect from a 10 V/m field swept from 10 to
450 MHz applied to the transceiver when mounted to a circuit card without a
chassis enclosure.
Compliant per Agilent testing under single fault conditions.
TUV Certification: LED Class 1
200
3.8
(0.15)
3.0
180
∆λ- TRANSMITTER OUTPUT OPTICAL
SPECTRAL WIDTH (FWHM) - nm
10.8 ±0.1
(0.425 ±0.004)
1
(0.039)
9.8 ±0.1
(0.386 ±0.004)
1.0
160
1.5
140
2.0
tr/f – TRANSMITTER
OUTPUT OPTICAL RISE/
FALL TIMES – ns
2.5
120
3.0
100
1260
1280
1300
1320
1340
1360
λC – TRANSMITTER OUTPUT OPTICAL RISE/FALL
TIMES – ns
13.97
(0.55)
MIN.
0.25 ±0.1
(0.01 ±0.004)
(TOP OF PCB TO
BOTTOM OF
OPENING)
HFBR-5905 TRANSMITTER TEST RESULTS
OF λC, ∆λ AND tr/f ARE CORRELATED AND COMPLY
WITH THE ALLOWED SPECTRAL WIDTH AS A FUNCTION
OF CENTER WAVELENGTH FOR VARIOUS RISE AND
FALL TIMES.
14.79
(0.589)
Figure 11. Transmitter Output Optical Spectral
Width (FWHM) vs. Transmitter Output Optical
Center Wavelength and Rise/Fall Times.
DIMENSIONS IN MILLIMETERS (INCHES)
Figure 10. Recommended Panel Mounting
RELATIVE INPUT OPTICAL POWER (dB)
6
5
4
3
2
1
0
-3
-2
-1
0
1
2
EYE SAMPLING TIME POSITION (ns)
CONDITIONS:
1. T A = +25 C
2. V CC = 3.3 V dc
3. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
4. INPUT OPTICAL POWER IS NORMALIZED TO
CENTER OF DATA SYMBOL.
5. NOTE 15 AND 16 APPLY.
Figure 12. Relative Input Optical Power vs.
Eye Sampling Time Position.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to each parameter in
isolation, all other parameters having values within the recommended operating conditions. It should not be assumed that limiting values
of more than one parameter can be applied to the product at the same time. Exposure to the absolute maximum ratings for extended
periods can adversely affect device reliability.
Parameter
Symbol
Minimum Typical
Maximum Unit
Storage Temperature
TS
-40
+100
Lead Soldering Temperature
TSOLD
+260
°C
Lead Soldering Time
tSOLD
10
sec.
Supply Voltage
VCC
-0.5
3.6
V
Data Input Voltage
VI
-0.5
VCC
V
Differential Input Voltage (p-p)
VD
2.0
V
Output Current
IO
50
mA
10
10
Reference
°C
Note 1
3
Recommended Operating Conditions
Parameter
Symbol
Minimum Typical
Maximum Unit
Reference
0
-40
3.135
+70
+85
3.465
°C
°C
V
Note A
Note B
Supply Voltage
TA
TA
VCC
Data Input Voltage - Low
VIL - VCC
-1.810
-1.475
V
Data Input Voltage - High
VIH - VCC
-1.165
-0.880
V
Data and Signal Detect Output Load
RL
50

Differential Input Voltage (p-p)
VD
0.800
V
Ambient Operating Temperature
AFBR-5905
AFBR-5905A
Note 2
Notes:
A. Ambient Operating Temperature corresponds to transceiver case temperature of 0 °C mininum to +85 °C maximum with necessary airflow applied.
Recommanded case temperature measurement point can be found in Figure 2.
B. Ambient Operating Temperature corresponds to transceiver case temperature of -40 °C mininum to +100 °C maximum with necessary airflow
applied. Recommanded case temperature measurement point can be found in Figure 2.
Transmitter Electrical Characteristics
AFBR-5905Z (TA= 0°C to +70°C, VCC=3.135V to 3.465V)
AFBR-5905AZ (TA= -40°C to +85°C, VCC= 3.135V to 3.465V)
Parameter
Symbol
Maximum Unit
Reference
Supply Current
ICC
Minimum Typical
133
175
mA
Note 3
Power Dissipation
PDISS
0.45
0.60
W
Note 5a
Data Input Current - Low
IIL
Data Input Current - High
IIH
350
µA
-350
-2
18
µA
Receiver Electrical Characteristics
AFBR-5905Z (TA= 0°C to +70°C, VCC= 3.135V to 3.465V)
AFBR-5905AZ(TA= -40°C to +85°C, VCC= 3.135V to 3.465V)
Parameter
Symbol
Supply Current
ICC
Minimum Typical
65
120
mA
Note 4
Power Dissipation
PDISS
0.225
0.415
W
Note 5b
Data Output Voltage - Low
VOL - VCC
-1.55
V
Note 6
-1.83
Maximum Unit
Reference
Data Output Voltage - High
VOH - VCC
-1.085
-0.88
V
Note 6
Data Output Rise Time
tr
0.35
2.2
ns
Note 7
Data Output Fall Time
tf
0.35
2.2
ns
Note 7
Signal Detect Output Voltage - Low
VOL - VCC
-1.83
-1.55
V
Note 6
Signal Detect Output Voltage - High
VOH - VCC
-1.085
-0.88
V
Note 6
Signal Detect Output Rise Time
tr
0.35
2.2
ns
Note 7
Signal Detect Output Fall Time
tf
0.35
2.2
ns
Note 7
Power Supply Noise Rejection
PSNR
11
11
50
mV
Transmitter Optical Characteristics
AFBR-5905Z (TA= 0°C to +70°C, VCC= 3.135V to 3.465V)
AFBR-5905AZ (TA= -40°C to +85°C, VCC= 3.135V to 3.465V)
Parameter
Output Optical Power
62.5/125 µm, NA = 0.275 Fiber
Output Optical Power
50/125 µm, NA = 0.20 Fiber
Optical Extinction Ratio
BOL
EOL
BOL
EOL
Symbol
Minimum Typical
Maximum Unit
Reference
PO
-19
-20
-22.5
-23.5
10
-15.7
-14
dBm avg
Note 8
-20.3
-14
dBm avg
Note 8
dB
Note 9
-45
dBm avg
Note 10
1380
nm
Note 23
nm
Figure 11
Note 23
PO
Output Optical Power at
PO ("0")
Logic Low "0" State
Center Wavelength
C
Spectral Width - FWHM
1270
1308

147
- RMS
Optical Rise Time
tr
0.6
63
1.2
3.0
ns
Figure 11
Note 12, 23
Optical Fall Time
tf
0.6
2.0
3.0
ns
Figure 11
Note 12, 23
Systematic Jitter Contributed
SJ
0.21
1.2
ns p-p
Figure 11
Note 13
by the Transmitter
Random Jitter Contributed
RJ
0.14
0.52
ns p-p
Note 14
by the Transmitter
Receiver Optical and Electrical Characteristics
AFBR-5905Z (TA= 0°C to +70°C, VCC= 3.135V to 3.465V)
AFBR-5905AZ (TA= -40°C to +85°C, VCC= 3.135V to 3.465V)
Parameter
Symbol
Maximum Unit
Reference
Input Optical Power
Minimum at Window Edge
Input Optical Power
Minimum at Eye Center
Input Optical Power Maximum
PIN Min (W)
Minimum Typical
-30
dBm avg
PIN Min (C)
-31
dBm avg
PIN Max
-14
Note 15
Figure 12
Note 16
Figure 12
Note 15
Operating Wavelength

1270
1380
nm
dBm avg
Systematic Jitter Contributed
SJ
0.15
1.2
ns p-p
Note 17
by the Receiver
Random Jitter Contributed
RJ
0.11
1.91
ns p-p
Note 18
by the Receiver
Signal Detect - Asserted
PA
-31
dBm avg
Note 19
Note 20
PD + 1.5 dB
Signal Detect - Deasserted
PD
-45
dBm avg
Signal Detect - Hysteresis
PA - PD
1.5
dB
Signal Detect Assert Time
0
2
100
µs
Note 21
(off to on)
Signal Detect Deassert Time
0
5
350
µs
Note 22
(on to off)
12
12
Notes:
1. This is the maximum voltage that can be applied across the
Differential Transmitter Data Inputs to prevent damage to the input
ESD protection circuit.
2. The outputs are terminated with 50 Ω connected to VCC -2 V.
3. The power supply current needed to operate the transmitter is
provided to differential ECL circuitry. This circuitry maintains a nearly
constant current flow from the power supply. Constant current
operation helps to prevent unwanted electrical noise from being
generated and conducted or emitted to neighboring circuitry.
4. This value is measured with the outputs terminated into 50 Ω
connected to VCC - 2 V and an Input Optical Power level of -14 dBm
average.
5a. The power dissipation of the transmitter is calculated as the sum of
the products of supply voltage and current.
5b. The power dissipation of the receiver is calculated as the sum of
the products of supply voltage and currents, minus the sum of the
products of the output voltages and currents.
6. This value is measured with respect to VCC with the output terminated
into 50 Ω connected to VCC - 2 V.
7. The output rise and fall times are measured between 20% and 80%
levels with the output connected to VCC -2 V through 50 Ω. 8. These
optical power values are measured with the following conditions: •
The Beginning of Life (BOL) to the End of Life (EOL) optical power
degradation is typically 1.5 dB per the industry convention for long
wavelength LEDs. The actual degradation observed in Avago’s 1300
nm LED products is < 1 dB, as specified in this data sheet. • Over the
specified operating voltage and temperature ranges. • With 25 MBd
(12.5 MHz square-wave), input signal. • At the end of one meter of
noted optical fiber with cladding modes removed. The average
power value can be converted to a peak power value by adding 3
dB. Higher output optical power transmitters are available on special
request. Please consult with your local Avago sales representative for
further details.
9. The Extinction Ratio is a measure of the modulation depth of the
optical signal. The data “1” output optical power is compared to
the data “0” peak output optical power and expressed in decibels.
With the transmitter driven by a 25 MBd (12.5 MHz square-wave)
input signal, the average optical power is measured. The data “1”
peak power is then calculated by adding 3 dB to the measured
average optical power. The data “0” output optical power is found
by measuring the optical power when the transmitter is driven by a
logic “0” input. The extinction ratio is the ratio of the optical power at
the “1” level compared to the optical power at the “0” level expressed
in decibels.
10. The transmitter will provide this low level of Output Optical
Power when driven by a logic “0” input. This can be useful in link
troubleshooting.
11. The relationship between Full Width Half Maximum and RMS values for
Spectral Width is derived from the assumption of a Gaussian shaped
spectrum which results in a 2.35 X RMS = FWHM relationship.
12. The optical rise and fall times are measured from 10% to 90% when
the transmitter is driven by a 25 MBd (12.5 MHz square-wave) input
signal. The ANSI T1E1.2 committee has designated the possibility of
defining an eye pattern mask for the transmitter optical output as
an item for further study. Avago will incorporate this requirement
into the specifications for these products if it is defined. The HFBR5905 products typically comply with the template requirements of
CCITT (now ITU-T) G.957 Section 3.2.5, Figure 2 for the STM-1 rate,
excluding the optical receiver filter normally associated with single
mode fiber measurements which is the likely source for the ANSI
T1E1.2 committee to follow in this matter.
For product information and a complete list of distributors, please go to our web site:
13. Systematic Jitter contributed by the transmitter is defined as the
combination of Duty Cycle Distortion and Data Dependent Jitter.
Systematic Jitter is measured at 50% threshold using a 155.52 MBd
(77.5 MHz square-wave), 27 - 1 psuedorandom data pattern input
signal.
14. Random Jitter contributed by the transmitter is specified with a
155.52 MBd (77.5 MHz square-wave) input signal.
15. This specification is intended to indicate the performance of the
receiver section of the transceiver when Input Optical Power signal
characteristics are present per the following definitions. The Input
Optical Power dynamic range from the minimum level (with a
window time-width) to the maximum level is the range over which
the receiver is guaranteed to provide output data with a Bit Error
Rate (BER) better than or equal to 1 x 10-10.
• At the Beginning of Life (BOL)
• Over the specified operating temperature and voltage ranges
• Input is a 155.52 MBd, 223 - 1 PRBS data pattern with 72 “1”s and
72 “0”s inserted per the CCITT (now ITU-T) recommendation G.958
Appendix I.
• Receiver data window time-width is 1.23 ns or greater for the
clock recovery circuit to operate in. The actual test data window
time-width is set to simulate the effect of worst case optical input
jitter based on the transmitter jitter values from the specification
tables. The test window time-width is AFBR-5905Z 3.32 ns.
• Transmitter operating with a 155.52 MBd, 77.5 MHz square-wave,
input signal to simulate any cross-talk present between the
transmitter and receiver sections of the transceiver.
16. All conditions of Note 15 apply except that the measurement is made
at the center of the symbol with no window time-width.
17. Systematic Jitter contributed by the receiver is defined as the
combination of Duty Cycle Distortion and Data Dependent Jitter.
Systematic Jitter is measured at 50% threshold using a 155.52 MBd
(77.5 MHz square-wave), 27 - 1 psuedorandom data pattern input
signal. 18. Random Jitter contributed by the receiver is specified with
a 155.52 MBd (77.5 MHz square-wave) input signal.
19. This value is measured during the transition from low to high levels
of input optical power.
20. This value is measured during the transition from high to low levels of
input optical power. At Signal Detect Deassert, the receiver outputs
Data Out and Data Out Bar go to steady PECL levels High and Low
respectively.
21. The Signal Detect output shall be asserted within 100 µs after a step
increase of the Input Optical Power.
22. Signal detect output shall be de-asserted within 350 µs after a step
decrease in the Input Optical Power. At Signal Detect Deassert, the
receiver outputs Data Out and Data Out Bar go to steady PECL levels
High and Low respectively.
23. The AFBR-5905Z transceiver complies with the requirements for the
trade-offs between center wavelength, spectral width, and rise/
fall times shown in Figure 11. This figure is derived from the FDDI
PMD standard (ISO/IEC 9314-3 : 1990 and ANSI X3.166 - 1990) per
the description in ANSI T1E1.2 Revision 3. The interpretation of this
figure is that values of Center Wavelength and Spectral Width must
lie along the appropriate Optical Rise/ Fall Time curve.
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Data subject to change. Copyright © 2008 Avago Technologies Limited. All rights reserved.
5989-3083EN - February 20, 2008