CYPRESS CY7C1470V25_12

CY7C1470V25
CY7C1472V25
CY7C1474V25
72-Mbit (2 M × 36/4 M × 18/1 M × 72)
Pipelined SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture
Features
Functional Description
■
Pin-compatible and functionally equivalent to ZBT™
■
Supports 200-MHz bus operations with zero wait states
❐ Available speed grades are 200 and 167 MHz
■
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■
Fully registered (inputs and outputs) for pipelined operation
■
Byte write capability
■
Single 2.5 V power supply
■
2.5 V/1.8 V I/O supply (VDDQ)
■
Fast clock-to-output times
❐ 3.0 ns (for 200-MHz device)
■
Clock enable (CEN) pin to suspend operation
■
Synchronous self-timed writes
■
CY7C1470V25 available in JEDEC-standard Pb-free 100-pin
TQFP, Pb-free and non Pb-free 165-ball FBGA package.
CY7C1472V25 available in JEDEC-standard Pb-free 100-pin
TQFP. CY7C1474V25 available in Pb-free and non Pb-free
209-ball FBGA package
■
IEEE 1149.1 JTAG boundary scan compatible
■
Burst capability – linear or interleaved burst order
■
“ZZ” sleep mode option and stop clock option
The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5 V,
2 M × 36/4 M × 18/1 M × 72 synchronous pipelined burst SRAMs
with No Bus Latency™ (NoBL logic, respectively. They are
designed to support unlimited true back-to-back read/write
operations
with
no
wait
states.
The
CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped
with the advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1470V25/CY7C1472V25/CY7C1474V25 are pin-compatible
and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the Byte Write Selects
(BWa–BWh for CY7C1474V25, BWa–BWd for CY7C1470V25
and BWa–BWb for CY7C1472V25) and a write enable (WE)
input. All writes are conducted with on-chip synchronous
self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
Cypress Semiconductor Corporation
Document Number: 38-05290 Rev. *O
•
198 Champion Court
•
200 MHz
167 MHz
Unit
3.0
450
120
3.4
400
120
ns
mA
mA
San Jose, CA 95134-1709
•
408-943-2600
Revised June 6, 2012
CY7C1470V25
CY7C1472V25
CY7C1474V25
Logic Block Diagram – CY7C1470V25
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
BWb
BWc
BWd
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
WE
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
ZZ
Document Number: 38-05290 Rev. *O
O
U
T
P
U
T
D
A
T
A
S
T
E
E
R
I
N
G
INPUT
REGISTER 0
B
U
F
F
E
R
S
DQs
DQPa
DQPb
DQPc
DQPd
E
E
READ LOGIC
SLEEP
CONTROL
Page 2 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Logic Block Diagram – CY7C1472V25
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
BURST A0'
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
BWb
WE
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
ZZ
Document Number: 38-05290 Rev. *O
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPa
DQPb
E
INPUT
REGISTER 0 E
READ LOGIC
Sleep
Control
Page 3 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Logic Block Diagram – CY7C1474V25
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
BURST A0'
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
E
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQPa
DQPb
DQPc
DQPd
DQPe
DQPf
DQPg
DQPh
WE
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
ZZ
Document Number: 38-05290 Rev. *O
INPUT
REGISTER 0 E
READ LOGIC
Sleep
Control
Page 4 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Contents
Pin Configurations ........................................................... 6
Pin Definitions .................................................................. 9
Functional Overview ...................................................... 10
Single Read Accesses .............................................. 10
Burst Read Accesses ................................................ 10
Single Write Accesses ............................................... 10
Burst Write Accesses ................................................ 11
Sleep Mode ............................................................... 11
Linear Burst Address Table ....................................... 11
Interleaved Burst Address Table ............................... 11
ZZ Mode Electrical Characteristics ............................ 11
Truth Table ...................................................................... 12
Partial Truth Table for Read/Write ................................ 13
Partial Truth Table for Read/Write ................................ 14
Partial Truth Table for Read/Write ................................ 14
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 15
Disabling the JTAG Feature ...................................... 15
Test Access Port (TAP) ............................................. 15
PERFORMING A TAP RESET .................................. 15
TAP REGISTERS ...................................................... 15
TAP Instruction Set ................................................... 15
TAP Controller State Diagram ....................................... 17
TAP Controller Block Diagram ...................................... 18
TAP Timing ...................................................................... 18
TAP AC Switching Characteristics ............................... 19
2.5 V TAP AC Test Conditions ....................................... 19
2.5 V TAP AC Output Load Equivalent ......................... 19
1.8 V TAP AC Test Conditions ....................................... 19
1.8 V TAP AC Output Load Equivalent ......................... 19
Document Number: 38-05290 Rev. *O
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 20
Identification Register Definitions ................................ 21
Scan Register Sizes ....................................................... 21
Instruction Codes ........................................................... 21
Boundary Scan Exit Order ............................................. 22
Boundary Scan Exit Order ............................................. 23
Maximum Ratings ........................................................... 24
Operating Range ............................................................. 24
Electrical Characteristics ............................................... 24
Capacitance .................................................................... 25
Thermal Resistance ........................................................ 25
AC Test Loads and Waveforms ..................................... 26
Switching Characteristics .............................................. 27
Switching Waveforms .................................................... 28
Ordering Information ...................................................... 30
Ordering Code Definitions ......................................... 30
Package Diagrams .......................................................... 31
Acronyms ........................................................................ 34
Document Conventions ................................................. 34
Units of Measure ....................................................... 34
Document History Page ................................................. 35
Sales, Solutions, and Legal Information ...................... 38
Worldwide Sales and Design Support ....................... 38
Products .................................................................... 38
PSoC Solutions ......................................................... 38
Page 5 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Pin Configurations
CY7C1470V25
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQPb
DQb
DQb
VDDQ
VSS
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
CY7C1472V25
(4 M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document Number: 38-05290 Rev. *O
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
VSS
VDD
NC(288)
NC(144)
A
A
A
A
A
A
A
A
A
VSS
VDD
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
DQb
DQb
NC
VSS
VDD
NC
NC
VDD
VSS
ZZ
DQb
DQa
DQa
DQb
VDDQ VDDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa DQPb
NC
DQa
VSS
VSS
VDDQ VDDQ
NC
DQa
DQa
NC
DQPa
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
(2 M × 36)
NC(288)
NC(144)
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DQPc
DQc
DQc
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
Page 6 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Pin Configurations (continued)
Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1470V25 (2 M × 36)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
A
CE1
BWc
BWb
CE3
ADV/LD
A
A
NC
BWa
VSS
CLK
CEN
WE
OE
A
A
NC
VSS
VSS
VSS
VDD
VDDQ
VDDQ
NC
DQb
DQPb
DQb
VDDQ
DQb
DQb
R
NC/1G
A
CE2
DQPc
DQc
NC
DQc
VDDQ
VDDQ
BWd
VSS
VDD
VSS
VSS
VSS
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
NC
DQd
DQc
NC
DQd
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQb
NC
DQa
DQb
ZZ
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQPd
DQd
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
DQa
DQPa
NC/144M
A
A
A
TDI
A1
TDO
A
A
A
MODE
A
A
A
TMS
A0
TCK
A
A
A
Document Number: 38-05290 Rev. *O
NC/288M
A
Page 7 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Pin Configurations (continued)
Figure 3. 209-ball FBGA (14 × 22 × 1.76 mm) pinout
CY7C1474V25 (1 M × 72)
1
2
3
4
5
6
7
8
9
10
11
A
DQg
DQg
A
CE2
A
ADV/LD
A
CE3
A
DQb
DQb
B
DQg
DQg
BWSc
BWSg
NC
WE
A
BWSb
BWSf
DQb
DQb
C
DQg
DQg
BWSh
BWSd
NC/576M
CE1
NC
BWSe
BWSa
DQb
DQb
D
DQg
DQg
VSS
NC
NC/1G
OE
NC
NC
VSS
DQb
DQb
E
DQPg
DQPc
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPf
DQPb
F
DQc
DQc
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQf
DQf
G
DQc
DQc
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQf
DQf
H
DQc
DQc
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQf
DQf
J
DQc
DQc
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQf
DQf
K
NC
NC
CLK
NC
VSS
CEN
VSS
NC
NC
NC
NC
L
DQh
DQh
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
M
DQh
DQh
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQa
DQa
N
DQh
DQh
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
P
DQh
DQh
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
DQa
DQa
R
DQPd
DQPh
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPa
DQPe
T
DQd
DQd
VSS
NC
NC
MODE
NC
NC
VSS
DQe
DQe
U
DQd
DQd
NC/144M
A
A
A
A
A
NC/288M
DQe
DQe
V
DQd
DQd
A
A
A
A1
A
A
A
DQe
DQe
W
DQd
DQd
TMS
TDI
A
A0
A
TDO
TCK
DQe
DQe
Document Number: 38-05290 Rev. *O
Page 8 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Pin Definitions
Pin Name
A0, A1, A
I/O Type
Pin Description
InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
synchronous
BWa, BWb,
InputByte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
BWc, BWd, synchronous the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc
BWe, BWf,
and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf controls DQf and DQPf,
BWg controls DQg and DQPg, BWh controls DQh and DQPh.
BWg, BWh
WE
InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/load input used to advance the on-chip address counter or load a new address. When
synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address
can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in
order to load a new address.
CLK
Inputclock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
OE
InputOutput enable, active LOW. Combined with the synchronous logic block inside the device to control
asynchronous the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted
HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state and when the device has been
deselected.
CEN
InputClock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
DQs
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[18:0]
during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQh
are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
DQPX
I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQ[71:0]. During write
synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg is controlled
by BWg, DQPh is controlled by BWh.
MODE
Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled
LOW selects the linear burst order. MODE should not change states during operation. When left floating
MODE will default HIGH, to an interleaved burst order.
TDO
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
output
synchronous
TDI
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
input
synchronous
Document Number: 38-05290 Rev. *O
Page 9 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Pin Definitions (continued)
Pin Name
TMS
TCK
VDD
VDDQ
I/O Type
Pin Description
Test mode This pin controls the test access port state machine. Sampled on the rising edge of TCK.
select
synchronous
JTAG clock
Clock input to the JTAG circuitry.
Power supply Power supply inputs to the core of the device.
I/O power
supply
Power supply for the I/O circuitry.
VSS
Ground
NC
–
No connects. This pin is not connected to the die.
NC/144M,
NC/288M,
NC/576M,
NC/1G
–
These pins are not connected. They will be used for expansion to the 144M, 288M, 576M and 1G
densities.
ZZ
Ground for the device. Should be connected to ground of the system.
InputZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
Functional Overview
The
CY7C1470V25/CY7C1472V25/CY7C1474V25
are
synchronous-pipelined burst NoBL SRAMs designed specifically
to eliminate wait states during write/read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
clock enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data outputs
pass through output registers controlled by the rising edge of the
clock. Maximum access delay from the clock rise (tCO) is 3.0 ns
(200-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW[x] can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
Document Number: 38-05290 Rev. *O
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 3.0 ns (200-MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
subsequent operation (read/write/deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output will tri-state following the next clock rise.
Burst Read Accesses
The CY7C1470V25/CY7C1472V25/CY7C1474V25 have an
on-chip burst counter that allows the user the ability to supply a
single address and conduct up to four reads without reasserting
the address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in Single Read
Accesses. The sequence of the burst counter is determined by
the MODE input signal. A LOW input on MODE selects a linear
burst mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (read
or write) is maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address inputs is
loaded into the address register. The write signals are latched
into the control logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
Page 10 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
subsequent clock rise, the chip enables (CE1, CE2, and CE3)
and WE inputs are ignored and the burst counter is incremented.
The correct BW (BWa,b,c,d,e,f,g,h for CY7C1474V25, BWa,b,c,d for
CY7C1470V25 and BWa,b for CY7C1472V25) inputs must be
driven in each cycle of the burst write in order to write the correct
bytes of data.
for
CY7C1474V25,
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
DQa,b,c,d/DQPa,b,c,d for CY7C1470V25 and DQa,b/DQPa,b for
CY7C1472V25). In addition, the address for the subsequent
access (read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
for
CY7C1474V25,
DQa,b,c,d/DQPa,b,c,d for CY7C1470V25 & DQa,b/DQPa,b for
CY7C1472V25) (or a subset for byte write operations, see Write
Cycle Description table for details) inputs is latched into the
device and the write is complete.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
The data written during the write operation is controlled by BW
(BWa,b,c,d,e,f,g,h for CY7C1474V25, BWa,b,c,d for CY7C1470V25
and
BWa,b
for
CY7C1472V25)
signals.
The
CY7C1470V25/CY7C1472V25/CY7C1474V25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the write enable input (WE) with the selected
byte write select (BW) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly simplify
read/modify/write sequences, which can be reduced to simple
byte write operations.
Linear Burst Address Table
(MODE = GND)
Because the CY7C1470V25/CY7C1472V25/CY7C1474V25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The output enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
for
CY7C1474V25,
DQa,b,c,d/DQPa,b,c,d for CY7C1470V25 and DQa,b/DQPa,b for
CY7C1472V25) inputs. Doing so will tri-state the output drivers.
As
a
safety
precaution,
DQ
and
DQP
for
CY7C1474V25,
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
DQa,b,c,d/DQPa,b,c,d for CY7C1470V25 and DQa,b/DQPa,b for
CY7C1472V25) are automatically tri-stated during the data
portion of a write cycle, regardless of the state of OE.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1:A0
00
01
10
11
Burst Write Accesses
The CY7C1470V25/CY7C1472V25/CY7C1474V25 has an
on-chip burst counter that allows the user the ability to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW in
order to load the initial address, as described in Single Write
Accesses on page 10. When ADV/LD is driven HIGH on the
Second
Address
A1:A0
01
00
11
10
Third
Address
A1:A0
10
11
00
01
Fourth
Address
A1:A0
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ  VDD 0.2 V
–
120
mA
tZZS
Device operation to ZZ
ZZ VDD  0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ  0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 38-05290 Rev. *O
Page 11 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Truth Table
The truth table for CY7C1470V25/CY7C1472V25/CY7C1474V25 follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Deselect cycle
Address Used CE ZZ ADV/LD WE BWx OE CEN CLK
None
H
L
L
X
X
X
L
L–H
Continue deselect cycle
None
Read cycle (begin burst)
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
X
L
External
L
Next
X
External
L
Next
X
DQ
Tri-state
H
X
X
X
L
L–H
Tri-state
L
L
H
X
L
L
L–H Data out (Q)
L
H
X
X
L
L
L–H Data out (Q)
L
L
H
X
H
L
L–H
Tri-state
L
H
X
X
H
L
L–H
Tri-state
External
L
L
L
L
L
X
L
L–H
Data in (D)
Write cycle (continue burst)
Next
X
L
H
X
L
X
L
L–H
Data in (D)
NOP/write abort (begin burst)
None
L
L
L
L
H
X
L
L–H
Tri-state
Write abort (continue burst)
Next
X
L
H
X
H
X
L
L–H
Tri-state
Current
X
L
X
X
X
X
H
L–H
–
None
X
H
X
X
X
X
X
X
Tri-state
Ignore clock edge (stall)
Sleep mode
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW[a:d]. See Write Cycle Description table for details.
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[a:d] = tri-state when OE is
inactive or when the device is deselected, and DQs = data when OE is active.
Document Number: 38-05290 Rev. *O
Page 12 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Partial Truth Table for Read/Write
The partial truth table for Read/Write for CY7C1470V25 follows. [8, 9, 10, 11]
Function (CY7C1470V25)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write – no bytes written
L
H
H
H
H
Write byte a – (DQa and DQPa)
L
H
H
H
L
Write byte b – (DQb and DQPb)
L
H
H
L
H
Write bytes b, a
L
H
H
L
L
Write byte c – (DQc and DQPc)
L
H
L
H
H
Write bytes c, a
L
H
L
H
L
Write bytes c, b
L
H
LL
L
H
Write bytes c, b, a
L
H
L
L
L
Write byte d – (DQd and DQPd)
L
L
H
H
H
Write bytes d, a
L
L
H
H
L
Write bytes d, b
L
L
H
L
H
Write bytes d, b, a
L
L
H
L
L
Write bytes d, c
L
L
L
H
H
Write bytes d, c, a
L
L
L
H
L
Write bytes d, c, b
L
L
L
L
H
Write all bytes
L
L
L
L
L
Notes
8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
9. Write is defined by WE and BW[a:d]. See Write Cycle Description table for details.
10. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
11. Table only lists a partial listing of the byte write combinations. Any combination of BW[a:d] is valid. Appropriate write will be done based on which byte write is active.
Document Number: 38-05290 Rev. *O
Page 13 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Partial Truth Table for Read/Write
The partial truth table for Read/Write for CY7C1472V25 follows. [12, 13, 14, 15]
Function (CY7C1472V25)
WE
BWb
BWa
Read
H
x
x
Write – no bytes written
L
H
H
Write byte a – (DQa and DQPa)
L
H
L
Write byte b – (DQb and DQPb)
L
L
H
Write both bytes
L
L
L
Partial Truth Table for Read/Write
The partial truth table for Read/Write for CY7C1474V25 follows. [12, 13, 14, 15]
Function (CY7C1474V25)
WE
BWx
Read
H
x
Write – no bytes written
L
H
Write byte X(DQx and DQPx)
L
L
Write all bytes
L
All BW = L
Notes
12. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
13. Write is defined by WE and BW[a:d]. See Write Cycle Description table for details.
14. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
15. Table only lists a partial listing of the byte write combinations. Any combination of BW[a:d] is valid. Appropriate write will be done based on which byte write is active.
Document Number: 38-05290 Rev. *O
Page 14 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1470V25/CY7C1474V25 incorporates a serial
boundary scan test access port (TAP). This port operates in
accordance with IEEE Standard 1149.1-1990 but does not have
the set of functions required for full 1149.1 compliance. These
functions from the IEEE specification are excluded because their
inclusion places an added delay in the critical speed path of the
SRAM. Note that the TAP controller functions in a manner that
does not conflict with the operation of other devices using 1149.1
fully compliant TAPs. The TAP operates using JEDEC-standard
2.5 V or 1.8 V I/O logic levels.
The CY7C1470V25/CY7C1474V25 contains a TAP controller,
instruction register, boundary scan register, bypass register, and
ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 17. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Instruction Codes on page 21).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Document Number: 38-05290 Rev. *O
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 18. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 21.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
Page 15 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
RESERVED and should not be used. The other five instructions
are described in detail below.
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in this SRAM TAP controller, and
therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a high Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a high Z state.
Document Number: 38-05290 Rev. *O
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the
device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold time (tCS plus tCH).
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the same
effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 16 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
0
1
EXIT1-DR
0
1
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 38-05290 Rev. *O
Page 17 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Instruction Register
31 30 29 .
.
Selection
Circuitry
. 2 1 0
TDO
Identification Register
x .
.
.
.
. 2 1 0
Boundary Scan Register
TCK
TMS
TAP CONTROLLER
TAP Timing
1
2
Test Clock
(TCK)
3
tTH
tTMSS
tTMSH
tTDIS
tTDIH
t
TL
4
5
6
tCYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
tTDOV
tTDOX
Test Data-Out
(TDO)
DON’T CARE
Document Number: 38-05290 Rev. *O
UNDEFINED
Page 18 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
TAP AC Switching Characteristics
Over the Operating Range
Parameter [16, 17]
Description
Min
Max
Unit
Clock
tTCYC
TCK clock cycle time
50
–
ns
tTF
TCK clock frequency
–
20
MHz
tTH
TCK clock HIGH time
20
–
ns
tTL
TCK clock LOW time
20
–
ns
tTDOV
TCK clock LOW to TDO valid
–
10
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
tTMSS
TMS set-up to TCK clock rise
5
–
ns
tTDIS
TDI set-up to TCK clock rise
5
–
ns
tCS
Capture set-up to TCK rise
5
–
ns
Output Times
Set-up Times
Hold Times
tTMSH
TMS hold after TCK clock rise
5
–
ns
tTDIH
TDI hold after clock rise
5
–
ns
tCH
Capture hold after clock rise
5
–
ns
2.5 V TAP AC Test Conditions
1.8 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 2.5 V
Input pulse levels ................................ 0.2 V to VDDQ – 0.2 V
Input rise and fall time ....................................................1 ns
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
Input timing reference levels ......................................... 0.9 V
Output reference levels .............................................. 1.25 V
Output reference levels ................................................ 0.9 V
Test load termination supply voltage .......................... 1.25 V
Test load termination supply voltage ............................ 0.9 V
2.5 V TAP AC Output Load Equivalent
1.8 V TAP AC Output Load Equivalent
0.9V
1.25V
50
50
TDO
TDO
Z O= 50
20pF
Z O= 50
20pF
Notes
16. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
17. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 38-05290 Rev. *O
Page 19 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 2.5 V ± 0.125 V unless otherwise noted)
Parameter [18]
Min
Max
Unit
VOH1
Output HIGH voltage
Description
IOH = –1.0 mA
Test Conditions
VDDQ = 2.5 V
1.7
–
V
VOH2
Output HIGH voltage
IOH = –100 A
VDDQ = 2.5 V
2.1
–
V
VDDQ = 1.8 V
1.6
–
V
VOL1
Output LOW voltage
IOL = 1.0 mA
VDDQ = 2.5 V
–
0.4
V
VOL2
Output LOW voltage
IOL = 100 A
VDDQ = 2.5 V
–
0.2
V
VDDQ = 1.8 V
–
0.2
V
VIH
Input HIGH voltage
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 1.8 V
1.26
VDD + 0.3
V
VIL
Input LOW voltage
VDDQ = 2.5 V
–0.3
0.7
V
VDDQ = 1.8 V
–0.3
0.36
V
IX
Input load current
–5
5
A
GND  VI  VDDQ
Note
18. All voltages referenced to VSS (GND).
Document Number: 38-05290 Rev. *O
Page 20 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Identification Register Definitions
Instruction Field
CY7C1470V25
(2 M × 36)
CY7C1474V25
(1 M × 72)
000
000
Revision number (31:29)
Device depth (28:24)
Architecture/memory type(23:18)
Bus width/density(17:12)
Cypress JEDEC ID code (11:1)
Describes the version number
01011
01011
001000
001000
Defines memory type and architecture
Reserved for internal use
Defines width and density
100100
110100
00000110100
00000110100
1
1
ID register presence indicator (0)
Description
Allows unique identification of SRAM
vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (× 36)
Bit Size (× 72)
Instruction
3
3
Bypass
1
1
ID
32
32
Boundary scan order – 165-ball FBGA package
71
–
Boundary scan order – 209-ball BGA package)
–
110
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM outputs to high Z state. This instruction is not 1149.1-compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a high Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation. This instruction does not implement 1149.1 preload function and
is therefore not 1149.1-compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 38-05290 Rev. *O
Page 21 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Boundary Scan Exit Order
(2 M × 36)
Bit #
165-ball ID
Bit #
165-ball ID
Bit #
165-ball ID
Bit #
165-ball ID
1
C1
21
R3
2
D1
22
P2
41
J11
61
B7
42
K10
62
B6
3
E1
23
R4
43
J10
63
A6
4
D2
24
P6
44
H11
64
B5
5
E2
25
R6
45
G11
65
A5
6
F1
26
R8
46
F11
66
A4
7
G1
27
P3
47
E11
67
B4
8
F2
28
P4
48
D10
68
B3
9
G2
29
P8
49
D11
69
A3
10
J1
30
P9
50
C11
70
A2
11
K1
31
P10
51
G10
71
B2
12
L1
32
R9
52
F10
13
J2
33
R10
53
E10
14
M1
34
R11
54
A9
15
N1
35
N11
55
B9
16
K2
36
M11
56
A10
17
L2
37
L11
57
B10
18
M2
38
M10
58
A8
19
R1
39
L10
59
B8
20
R2
40
K11
60
A7
Document Number: 38-05290 Rev. *O
Page 22 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Boundary Scan Exit Order
(1 M × 72)
Bit #
209-ball ID
Bit #
209-ball ID
Bit #
209-ball ID
Bit #
209-ball ID
1
A1
29
T1
57
U10
85
B11
2
A2
30
T2
58
T11
86
B10
3
B1
31
U1
59
T10
87
A11
4
B2
32
U2
60
R11
88
A10
5
C1
33
V1
61
R10
89
A7
6
C2
34
V2
62
P11
90
A5
7
D1
35
W1
63
P10
91
A9
8
D2
36
W2
64
N11
92
U8
9
E1
37
T6
65
N10
93
A6
10
E2
38
V3
66
M11
94
D6
11
F1
39
V4
67
M10
95
K6
12
F2
40
U4
68
L11
96
B6
13
G1
41
W5
69
L10
97
K3
14
G2
42
V6
70
P6
98
A8
15
H1
43
W6
71
J11
99
B4
16
H2
44
V5
72
J10
100
B3
17
J1
45
U5
73
H11
101
C3
18
J2
46
U6
74
H10
102
C4
19
L1
47
W7
75
G11
103
C8
20
L2
48
V7
76
G10
104
C9
21
M1
49
U7
77
F11
105
B9
22
M2
50
V8
78
F10
106
B8
23
N1
51
V9
79
E10
107
A4
24
N2
52
W11
80
E11
108
C6
25
P1
53
W10
81
D11
109
B7
110
A3
26
P2
54
V11
82
D10
27
R2
55
V10
83
C11
28
R1
56
U11
84
C10
Document Number: 38-05290 Rev. *O
Page 23 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Maximum Ratings
Current into outputs (LOW) ........................................ 20 mA
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Latch-up current ................................................... > 200 mA
Operating Range
Supply voltage on VDD relative to GND .......–0.5 V to +3.6 V
Range
Ambient
Temperature
VDD
VDDQ
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
Commercial
0 °C to +70 °C
DC to outputs in tri-state ...................–0.5 V to VDDQ + 0.5 V
1.7 V to VDD
Industrial
2.5 V – 5% /
+ 5%
–40 °C to +85 °C
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Electrical Characteristics
Over the Operating Range
Parameter [19, 20]
Description
VDD
Power supply voltage
VDDQ
I/O supply voltage
VOH
VOL
VIH
VIL
IX
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
[21]
Test Conditions
Min
Max
Unit
2.375
2.625
V
for 2.5 V I/O
2.375
VDD
V
for 1.8 V I/O
1.7
1.9
V
for 2.5 V I/O, IOH=1.0 mA
2.0
–
V
for 1.8 V I/O, IOH = –100 A
1.6
–
V
for 2.5 V I/O, IOL=1.0 mA
–
0.4
V
for 1.8 V I/O, IOL= 100 A
–
0.2
V
for 2.5 V I/O
1.7
VDD + 0.3 V
V
for 1.8 V I/O
1.26
VDD + 0.3 V
V
for 2.5 V I/O
–0.3
0.7
V
for 1.8 V I/O
–0.3
0.36
V
Input leakage current except ZZ GND  VI  VDDQ
and MODE
–5
5
A
Input current of MODE
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input = VDD
–
30
A
Input LOW voltage
[21]
Input current of ZZ
Input = VSS
IOZ
Output leakage current
GND  VI  VDDQ, output disabled
–5
5
A
IDD
VDD operating supply
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
5.0-ns cycle,
200 MHz
–
450
mA
6.0-ns cycle,
167 MHz
–
400
mA
Notes
19. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
20. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
21. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05290 Rev. *O
Page 24 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Electrical Characteristics (continued)
Over the Operating Range
Parameter [19, 20]
ISB1
Description
Automatic CE power-down
current – TTL inputs
Test Conditions
Min
Max
Unit
Max VDD, device deselected,
VIN  VIH or VIN  VIL,
f = fMAX = 1/tCYC
5.0-ns cycle,
200 MHz
–
200
mA
6.0-ns cycle,
167 MHz
–
200
mA
All speed
grades
–
120
mA
ISB2
Automatic CE power-down
current – CMOS inputs
Max. VDD, device deselected,
VIN  0.3 V or
VIN > VDDQ 0.3 V, f = 0
ISB3
Automatic CE power-down
current – CMOS inputs
Max VDD, device deselected,
5.0-ns cycle,
VIN  0.3 V or VIN > VDDQ 0.3 V, 200 MHz
f = fMAX = 1/tCYC
6.0-ns cycle,
167 MHz
–
200
mA
–
200
mA
Max VDD, device deselected,
VIN  VIH or VIN  VIL, f = 0
–
135
mA
ISB4
Automatic CE power-down
current – TTL inputs
All speed
grades
Capacitance
Parameter [22]
Description
CADDRESS
Address input capacitance
CDATA
Data input capacitance
CCTRL
Control input capacitance
CCLK
CI/O
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 2.5 V, VDDQ = 2.5 V
100-pin TQFP 165-ball FBGA 209-ball FBGA Unit
Max
Max
Max
6
6
6
pF
5
5
5
pF
8
8
8
pF
Clock input capacitance
6
6
6
pF
Input/output capacitance
5
5
5
pF
Thermal Resistance
Parameter [22]
JA
JC
Description
Test Conditions
Thermal resistance (junction Test
conditions
follow
to ambient)
standard test methods and
Thermal resistance (junction procedures for measuring
thermal impedance, per
to case)
EIA/JESD51.
100-pin TQFP 165-ball FBGA 209-ball FBGA Unit
Package
Package
Package
24.63
16.3
15.2
C/W
2.28
2.1
1.7
C/W
Note
22. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05290 Rev. *O
Page 25 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
2.5 V I/O Test Load
R = 1667 
2.5 V
OUTPUT
OUTPUT
RL = 50 
Z0 = 50 
GND
5 pF
R = 1538 
VL = 1.25 V
INCLUDING
JIG AND
SCOPE
(a)
1.8 V I/O Test Load
OUTPUT
RL = 50 
Z0 = 50 
Document Number: 38-05290 Rev. *O
INCLUDING
JIG AND
SCOPE
 1 ns
 1 ns
(c)
ALL INPUT PULSES
VDDQ - 0.2
0.2
5 pF
R = 14 k
(b)
90%
10%
90%
(b)
VL =0.9 V
(a)
10%
R = 14 k
1.8 V
OUTPUT
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
 1 ns
 1 ns
(c)
Page 26 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Switching Characteristics
Over the Operating Range
Parameter [23, 24]
tPower[25]
Description
VCC(typical) to the first access read or write
-200
-167
Unit
Min
Max
Min
Max
1
–
1
–
ms
5.0
–
6.0
–
ns
–
200
–
167
MHz
Clock
tCYC
Clock cycle time
FMAX
Maximum operating frequency
tCH
Clock HIGH
2.0
–
2.2
–
ns
tCL
Clock LOW
2.0
–
2.2
–
ns
Output Times
tCO
Data output valid after CLK rise
–
3.0
–
3.4
ns
tOEV
OE LOW to output valid
–
3.0
–
3.4
ns
tDOH
Data output hold after CLK rise
1.3
–
1.5
–
ns
tCHZ
Clock to high Z [26, 27, 28]
–
3.0
–
3.4
ns
1.3
–
1.5
–
ns
–
3.0
–
3.4
ns
0
–
0
–
ns
tCLZ
tEOHZ
tEOLZ
Clock to low Z
[26, 27, 28]
OE HIGH to output high Z
OE LOW to Output low Z
[26, 27, 28]
[26, 27, 28]
Set-up Times
tAS
Address set-up before CLK rise
1.4
–
1.5
–
ns
tDS
Data input set-up before CLK rise
1.4
–
1.5
–
ns
tCENS
CEN set-up before CLK rise
1.4
–
1.5
–
ns
tWES
WE, BWx set-up before CLK rise
1.4
–
1.5
–
ns
tALS
ADV/LD set-up before CLK rise
1.4
–
1.5
–
ns
tCES
Chip select set-up
1.4
–
1.5
–
ns
tAH
Address hold after CLK rise
0.4
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.4
–
0.5
–
ns
tCENH
CEN hold after CLK rise
0.4
–
0.5
–
ns
tWEH
WE, BWx hold after CLK rise
0.4
–
0.5
–
ns
tALH
ADV/LD hold after CLK rise
0.4
–
0.5
–
ns
tCEH
Chip select hold after CLK rise
0.4
–
0.5
–
ns
Hold Times
Notes
23. Timing reference is 1.25 V when VDDQ = 2.5 V and 0.9 V when VDDQ = 1.8 V.
24. Test conditions shown in (a) of Figure 4 on page 26 unless otherwise noted.
25. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated.
26. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of Figure 4 on page 26. Transition is measured ± 200 mV from steady-state voltage.
27. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
28. This parameter is sampled and not 100% tested.
Document Number: 38-05290 Rev. *O
Page 27 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Switching Waveforms
Figure 5. Read/Write/Timing [29, 30, 31]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCH
tCL
CEN
tCES
tCEH
CE
ADV/LD
WE
BWx
A1
ADDRESS
A2
tCO
tAS
tDS
tAH
Data
In-Out (DQ)
tDH
D(A1)
tCLZ
D(A2)
D(A2+1)
tDOH
Q(A3)
tOEV
Q(A4)
tCHZ
Q(A4+1)
D(A5)
Q(A6)
tOEHZ
tDOH
tOELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes
29. For this waveform ZZ is tied LOW.
30. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
31. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 38-05290 Rev. *O
Page 28 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Switching Waveforms (continued)
Figure 6. NOP, STALL and DESELECT Cycles [32, 33, 34]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
ADDRESS
A5
tCHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Figure 7. ZZ Mode Timing [35, 36]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I
t RZZI
DDZZ
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
32. For this waveform ZZ is tied LOW.
33. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
34. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
35. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
36. I/Os are in high Z when exiting ZZ sleep mode.
Document Number: 38-05290 Rev. *O
Page 29 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available.For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
167
200
Ordering Code
CY7C1470V25-167BZC
Package
Diagram
Part and Package Type
51-85165 165-ball FBGA (15 × 17 × 1.4mm)
Operating
Range
Commercial
CY7C1470V25-167BZXI
51-85165 165-ball FBGA (15 × 17 × 1.4mm) Pb-free
Industrial
CY7C1470V25-200AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1472V25-200AXC
51-85050
CY7C1470V25-200BZXC
51-85165 165-ball FBGA (15 × 17 × 1.4mm) Pb-free
CY7C1474V25-200BGC
51-85167 209-ball FBGA (14 × 22 × 1.76 mm)
CY7C1470V25-200BZI
51-85165 165-ball FBGA (15 × 17 × 1.4mm)
CY7C1470V25-200BZC
51-85165
CY7C1474V25-200BGI
51-85167 209-ball FBGA (14 × 22 × 1.76 mm)
CY7C1474V25-200BGXI
51-85167 209-ball FBGA (14 × 22 × 1.76 mm) Pb-free
Industrial
Commercial
Industrial
Ordering Code Definitions
CY 7
C 14XX V25 - XXX XX X
X
Temperature range: X = C or I
C = Commercial = 0 C to +70 C; I = Industrial = –40 C to +85 C
Pb-free
Package Type: XX = BZ or A or BG
BZ = 165-ball FBGA
A = 100-pin TQFP
BG = 209-ball FBGA
Speed Grade: XXX = 167 MHz or 200 MHz
V25 = 2.5 V
Part Identifier: 14XX = 1470 or 1472 or 1474
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05290 Rev. *O
Page 30 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *D
Document Number: 38-05290 Rev. *O
Page 31 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Package Diagrams (continued)
Figure 9. 165-ball FBGA (15 × 17 × 1.40 mm) (0.45 Ball Diameter) Package Outline, 51-85165
51-85165 *D
Document Number: 38-05290 Rev. *O
Page 32 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Package Diagrams (continued)
Figure 10. 209-ball FBGA (14 × 22 × 1.76 mm) BB209A Package Outline, 51-85167
51-85167 *B
Document Number: 38-05290 Rev. *O
Page 33 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Acronyms
Document Conventions
Acronym
Description
Units of Measure
BGA
ball grid array
CE
chip enable
°C
degree Celsius
CEN
clock enable
MHz
megahertz
CMOS
complementary metal oxide semiconductor
µA
microampere
EIA
electronic industries alliance
mA
milliampere
FBGA
fine-pitch ball grid array
mm
millimeter
I/O
input/output
ms
millisecond
JEDEC
joint electron devices engineering council
mV
millivolt
JTAG
joint test action group
ns
nanosecond
LSB
least significant bit

ohm
MSB
most significant bit
%
percent
NoBL
No Bus Latency
pF
picofarad
OE
output enable
V
volt
SRAM
static random access memory
W
watt
TAP
test access port
TCK
test clock
TDI
test data-in
TDO
test data-out
TMS
test mode select
TQFP
thin quad flat pack
TTL
transistor-transistor logic
WE
write enable
Document Number: 38-05290 Rev. *O
Symbol
Unit of Measure
Page 34 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Document History Page
Document Title: CY7C1470V25/CY7C1472V25/CY7C1474V25, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with
NoBL™ Architecture
Document Number: 38-05290
Rev.
ECN No.
Issue Date
Orig. of
Change
**
114677
08/06/02
PKS
New data sheet.
*A
121519
01/27/03
CJM
Changed status from Advanced Information to Preliminary.
Updated Features (For package offering, removed 300 MHz frequency related
information).
Updated Selection Guide (Removed 300 MHz frequency related information).
Updated Functional Overview (Removed 300 MHz frequency related
information).
Updated Electrical Characteristics (Removed 300 MHz frequency related
information).
Updated Switching Characteristics (Removed 300 MHz frequency related
information, changed maximum value of tCO, tEOV, tCHZ, tEOHZ parameters from
2.4 ns to 2.6 ns for 250 MHz frequency, changed minimum value of tDOH, tCLZ
parameters from 0.8 ns to 1.0 ns for 250 MHz frequency, changed minimum value
of tDOH, tCLZ parameters from 1.0 ns to 1.3 ns for 200 MHz frequency).
Updated Ordering Information (Updated part numbers).
*B
223721
See ECN
NJY
Updated Features (Removed 250 MHz frequency related information and
included 225 MHz frequency related information).
Updated Functional Description (description).
Updated Selection Guide (Removed 250 MHz frequency related information and
included 225 MHz frequency related information).
Updated Logic Block Diagram (Splitted Logic Block Diagram into three Logic
Block Diagrams).
Updated Functional Overview (description).
Updated Boundary Scan Exit Order (Replaced TBD with values for all packages).
Updated Electrical Characteristics (Removed 250 MHz frequency related
information and included 225 MHz frequency related information, replaced TBD
with values for maximum values of IDD, ISB1, ISB2, ISB3, ISB4 parameters).
Updated Capacitance (Replaced TBD with values for all packages).
Updated Thermal Resistance (Replaced TBD with values for all packages).
Updated Switching Characteristics (Removed 250 MHz frequency related
information and included 225 MHz frequency related information).
Updated Switching Waveforms.
Updated Package Diagrams (spec 51-85165 (Changed revision from ** to *A) for
165-ball FBGA package, removed 119-ball BGA package (spec 51-85115),
removed spec 51-85143 and incluuded spec 51-85167 for 209-ball BGA
package).
*C
235012
See ECN
RYQ
Minor Change (To match on the spec system and external web).
*D
243572
See ECN
NJY
Updated Pin Configurations (Updated Figure 2 (Changed ball C11, D11, E11,
F11, G11 from DQPb, DQb, DQb, DQb, DQb to DQPa, DQa, DQa, DQa, DQa
(corresponding to CY7C1472V25))).
Updated Capacitance (Splitted CIN parameter into CADDRESS, CDATA, CCLK
parameters and also updated the values).
Document Number: 38-05290 Rev. *O
Description of Change
Page 35 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Document History Page (continued)
Document Title: CY7C1470V25/CY7C1472V25/CY7C1474V25, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with
NoBL™ Architecture
Document Number: 38-05290
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
*E
299511
See ECN
SYT
Updated Features (Removed 225 MHz frequency related information and
included 250 MHz frequency related information).
Updated Selection Guide (Removed 225 MHz frequency related information and
included 250 MHz frequency related information).
Updated Electrical Characteristics (Removed 225 MHz frequency related
information and included 250 MHz frequency related information).
Updated Thermal Resistance (Changed value of JA from 16.8 C/W to
24.63 C/W, and changed value of JC from 3.3 C/W to 2.28 C/W for 100-pin
TQFP Package).
Updated Switching Characteristics (Removed 225 MHz frequency related
information and included 250 MHz frequency related information, changed
minimum value of tCYC from 4.4 ns to 4.0 ns for 250 MHz frequency).
Updated Ordering Information (Updated part numbers (Removed 225 MHz
frequency related information and included 250 MHz frequency related
information, added lead-free information for 100-pin TQFP Package and 165-ball
FBGA Package), added comment of ‘Lead-free BG packages availability’ below
the Ordering Information).
*F
320197
See ECN
PCI
Updated Partial Truth Table for Read/Write (Corrected typo in part numbers).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Corrected typo in part
numbers).
Updated Ordering Information (No change in part numbers, removed comment
of ‘Pb-free BG packages availability’ below the Ordering Information).
*G
331513
See ECN
PCI
Updated Pin Configurations (Address expansion pins/balls in the pinouts for all
packages are modified as per JEDEC standard).
Updated Pin Definitions (Added Address Expansion pins).
Updated Operating Range (Added Industrial Temperature Range).
Updated Electrical Characteristics (Updated Test Conditions of VOL, VOH
parameters).
Updated Ordering Information (Updated part numbers).
*H
416221
See ECN
RXU
Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation from “3901 North First
Street” to “198 Champion Court”.
Updated Electrical Characteristics (Updated Note 20 (Changed VDDQ < VDD to
VDDQ < VDD), changed description of IX parameter from Input Load Current
except ZZ and MODE to Input Leakage Current except ZZ and MODE, changed
minimum value of IX parameter (corresponding to Input Current of MODE
(Input = VSS)) from –5 µA to –30 µA, changed maximum value of IX parameter
(corresponding to Input Current of MODE (Input = VDD)) from 30 µA to 5 µA,
changed minimum value of IX parameter (corresponding to Input Current of ZZ
(Input = VSS)) from –30 µA to –5 µA, changed maximum value of IX parameter
(corresponding to Input Current of ZZ (Input = VDD)) from 5 µA to 30 µA).
Updated Ordering Information ((Updated part numbers), replaced Package Name
column with Package Diagram in the Ordering Information table).
Replaced Three-state with Tri-state in all instances across the document.
*I
472335
See ECN
VKN
Updated Pin Configurations (Updated Figure 3 (Corrected the ball name for H9
from VSSQ to VSS).
Updated TAP AC Switching Characteristics (Changed minimum value of tTH, tTL
parameters from 25 ns to 20 ns, changed maximum value of tTDOV parameter
from 5 ns to 10 ns).
Updated Maximum Ratings (Added Maximum Rating for Supply Voltage on VDDQ
Relative to GND).
Updated Ordering Information (Updated part numbers).
Document Number: 38-05290 Rev. *O
Page 36 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Document History Page (continued)
Document Title: CY7C1470V25/CY7C1472V25/CY7C1474V25, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with
NoBL™ Architecture
Document Number: 38-05290
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
*J
2898958
03/25/10
NJY
Updated Ordering Information (Removed inactive parts from the ordering
information table).
Updated Package Diagrams.
*K
3054137
10/10/2010
NJY
Updated Ordering Information (Updated part numbers) and added Ordering Code
Definitions.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
*L
3207715
03/28/2011
NJY
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams.
*M
3378887
09/21/2011
PRIT
Updated Package Diagrams.
*N
3403584
10/12/2011
PRIT
Updated
Ordering
Information
(Removed
prune
CY7C1470V25-167BZXI and CY7C1470V25-200BZC).
*O
3638614
06/06/2012
PRIT
Updated Features (Removed 250 MHz frequency related information, removed
165-ball FBGA package related information (corresponding to CY7C1472V25)).
Updated Selection Guide (Removed 250 MHz frequency related information).
Updated Pin Configurations (Updated Figure 2 (Removed CY7C1472V25 related
information)).
Updated Functional Overview (Removed 250 MHz frequency related
information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed CY7C1472V25
related information).
Updated Identification Register Definitions (Removed CY7C1472V25 related
information).
Updated Scan Register Sizes (Removed “Bit Size (× 18)” column).
Removed Boundary Scan Exit Order (Corresponding to CY7C1472V25).
Updated Electrical Characteristics (Removed 250 MHz frequency related
information).
Updated Switching Characteristics (Removed 250 MHz frequency related
information).
Updated Ordering Information (Updated part numbers).
Document Number: 38-05290 Rev. *O
part
numbers
Page 37 of 38
CY7C1470V25
CY7C1472V25
CY7C1474V25
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2002-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05290 Rev. *O
Revised June 6, 2012
Page 38 of 38
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this
document may be the trademarks of their respective holders.