CY7C1354C, CY7C1356C 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL Architecture Datasheet.pdf

CY7C1354C
CY7C1356C
9-Mbit (256 K × 36/512 K × 18)
Pipelined SRAM with NoBL™ Architecture
9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
■
Pin-compatible and functionally equivalent to ZBT
■
Supports 250 MHz bus operations with zero wait states
❐ Available speed grades are 250, 200, and 166 MHz
■
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■
Fully registered (inputs and outputs) for pipelined operation
■
Byte write capability
■
Single 3.3 V power supply (VDD)
■
3.3 V or 2.5 V I/O power supply (VDDQ)
■
Fast clock-to-output times
❐ 2.8 ns (for 250 MHz device)
■
Clock enable (CEN) pin to suspend operation
■
Synchronous self-timed writes
■
Available in Pb-free 100-pin TQFP package, Pb-free, and non
Pb-free 119-ball BGA package and 165-ball FBGA package
■
IEEE 1149.1 JTAG-compatible boundary scan
■
Burst capability – linear or interleaved burst order
■
“ZZ” sleep mode option and stop clock option
The
CY7C1354C/CY7C1356C[1]
are
3.3 V,
256 K × 36/512 K × 18 synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back read/write
operations with no wait states. The CY7C1354C/CY7C1356C
are equipped with the advanced (NoBL) logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature greatly improves the throughput
of data in systems that require frequent write/read transitions.
The CY7C1354C/CY7C1356C are pin compatible and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1354C and BWa–BWb for CY7C1356C)
and a write enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
For a complete list of related documentation, click here.
Logic Block Diagram – CY7C1354C
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BW a
BW b
BW c
BW d
MEMORY
ARRAY
WRITE
DRIVERS
A
M
P
S
WE
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
S
T
E
E
R
I
N
G
INPUT
REGISTER 0
B
U
F
F
E
R
S
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
E
E
READ LOGIC
SLEEP
CONTROL
ZZ
Cypress Semiconductor Corporation
Document Number: 38-05538 Rev. *R
E
O
U
T
P
U
T
D
A
T
A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 19, 2015
CY7C1354C
CY7C1356C
Logic Block Diagram – CY7C1356C
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
BW a
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
A
M
P
S
BW b
WE
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
O
U
T
P
U
T
D
A
T
A
B
U
F
F
E
R
S
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
ZZ
E
DQ s
DQ Pa
DQ Pb
E
INPUT
REGISTER 0
E
READ LOGIC
Sleep
Control
Note
1. For best-practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.
Document Number: 38-05538 Rev. *R
Page 2 of 35
CY7C1354C
CY7C1356C
Contents
Selection Guide ................................................................ 4
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Burst Read Accesses .................................................. 8
Single Write Accesses ................................................. 8
Burst Write Accesses .................................................. 9
Sleep Mode ................................................................. 9
Interleaved Burst Address Table ................................. 9
Linear Burst Address Table ......................................... 9
ZZ Mode Electrical Characteristics .............................. 9
Truth Table ...................................................................... 10
Partial Truth Table for Read/Write ................................ 11
Partial Truth Table for Read/Write ................................ 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
Test Access Port (TAP) ............................................. 12
PERFORMING A TAP RESET .................................. 12
TAP REGISTERS ...................................................... 12
TAP Instruction Set ................................................... 12
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 15
TAP Timing ...................................................................... 15
TAP AC Switching Characteristics ............................... 16
3.3 V TAP AC Test Conditions ....................................... 16
3.3 V TAP AC Output Load Equivalent ......................... 16
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
Document Number: 38-05538 Rev. *R
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Boundary Scan Exit Order ............................................. 19
Boundary Scan Exit Order ............................................. 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 25
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Package Diagrams .......................................................... 29
Acronyms ........................................................................ 32
Document Conventions ................................................. 32
Units of Measure ....................................................... 32
Document History Page ................................................. 33
Sales, Solutions, and Legal Information ...................... 35
Worldwide Sales and Design Support ....................... 35
Products .................................................................... 35
PSoC® Solutions ...................................................... 35
Cypress Developer Community ................................. 35
Technical Support ..................................................... 35
Page 3 of 35
CY7C1354C
CY7C1356C
Selection Guide
Description
250 MHz
200 MHz
166 MHz
Unit
Maximum access time
2.8
3.2
3.5
ns
Maximum operating current
250
220
180
mA
Maximum CMOS standby current
40
40
40
mA
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1356C
(512 K × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
NC(36)
NC(72)
VSS
VDD
NC(288)
NC(144)
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
DQPb
NC
DQb
NC
DQb
VDDQ VDDQ
VSS
VSS
NC
DQb
DQb
NC
DQb
DQb
DQb
DQb
VSS
VSS
VDDQ VDDQ
DQb
DQb
DQb
DQb
NC
VSS
VDD
NC
VDD
NC
VSS
ZZ
DQb
DQa
DQa
DQb
VDDQ VDDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa DQPb
NC
DQa
VSS
VSS
VDDQ VDDQ
NC
DQa
DQa
NC
DQPa
NC
MODE
A
A
A
A
A1
A0
Document Number: 38-05538 Rev. *R
NC(36)
NC(72)
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
VSS
VDD
NC
CY7C1354C
(256 K × 36)
NC(288)
NC(144)
DQc
DQc
NC
VDD
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DQPc
DQc
DQc
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
NC(18)
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
NC(18)
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
Page 4 of 35
CY7C1354C
CY7C1356C
Pin Configurations (continued)
Figure 2. 119-ball BGA (14 × 22 × 2.4 mm) pinout
CY7C1354C (256 K × 36)
1
2
3
4
5
6
7
A
VDDQ
A
A
NC/18M
A
A
VDDQ
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
NC/1G
DQc
CE2
A
DQPc
A
A
VSS
ADV/LD
VDD
NC
A
A
VSS
CE3
A
DQPb
NC
NC
DQb
DQc
DQc
VSS
CE1
VSS
DQb
DQb
VDDQ
DQc
VSS
DQb
VDDQ
DQc
BWb
DQb
DQb
DQc
VDDQ
DQc
VDD
BWc
VSS
NC
OE
A
VSS
DQc
WE
VDD
VSS
NC
DQb
VDD
DQb
VDDQ
DQd
DQd
DQd
DQd
CLK
NC
VSS
BWd
BWa
DQa
DQa
DQa
DQa
VDDQ
DQd
VSS
DQa
VDDQ
DQd
VSS
CEN
A1
VSS
DQd
VSS
DQa
DQa
DQd
DQPd
VSS
A0
VSS
DQPa
DQa
R
T
U
NC/144M
A
MODE
VDD
NC/288M
NC/72M
A
A
NC
A
A
NC
NC/36M
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
VSS
CY7C1356C (512 K × 18)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
2
3
4
5
6
7
VDDQ
A
A
NC/18M
A
A
VDDQ
NC/576M
CE2
A
A
VSS
A
VSS
CE3
A
DQPa
NC
A
NC
ADV/LD
VDD
NC
A
NC/1G
DQb
CE1
VSS
NC
DQa
OE
A
VSS
DQa
VDDQ
VSS
VSS
NC
NC
DQa
VDD
DQa
NC
VDDQ
DQa
NC
DQb
VSS
VDDQ
NC
VSS
NC
DQb
VDDQ
DQb
NC
VDD
BWb
VSS
NC
WE
VDD
NC
NC
NC
DQb
VSS
CLK
VSS
NC
DQb
NC
VSS
NC
DQa
NC
VDDQ
DQb
VSS
NC
VDDQ
DQb
NC
VSS
CEN
A1
BWa
VSS
VSS
DQa
NC
NC
DQPb
VSS
A0
VSS
NC
DQa
NC/144M
A
MODE
VDD
NC
A
NC/288M
NC/72M
A
A
NC/36M
A
A
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Document Number: 38-05538 Rev. *R
Page 5 of 35
CY7C1354C
CY7C1356C
Pin Configurations (continued)
Figure 3. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1354C (256 K × 36)
4
5
6
7
1
2
3
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
A
CE1
BWc
BWb
CE3
8
9
10
11
ADV/LD
A
A
NC
CLK
CEN
WE
NC/1G
A
NC
DQc
CE2
DQPc
DQc
VDDQ
VDDQ
BWd
VSS
VDD
BWa
VSS
VSS
OE
NC/18M
A
NC
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
NC
DQb
DQPb
DQb
DQc
DQc
VDDQ
VDD
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
NC
DQd
DQc
NC
DQd
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
DQb
NC
DQa
DQb
ZZ
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
DQPd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
DQa
DQPa
A
A
TDI
A1
TDO
A
A
A
NC/288M
R
MODE
A
A
TMS
A0
TCK
A
A
A
A
NC/144M NC/72M
NC/36M
NC
CY7C1356C (512 K × 18)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
7
8
9
10
11
NC/576M
A
CE1
NC
CE3
CEN
ADV/LD
A
A
A
NC/1G
CE2
BWa
CLK
NC
VSS
VDD
VSS
VDDQ
VSS
VSS
VSS
OE
VSS
VDD
A
VDDQ
VDDQ
WE
VSS
VSS
NC/18M
NC
NC
A
NC
DQb
BWb
NC
VDDQ
NC
NC
DQPa
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
NC
DQb
DQb
NC
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
NC
DQa
DQa
ZZ
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
DQPb
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
NC
NC
A
A
TDI
A1
TDO
A
A
A
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
NC/144M NC/72M
MODE
NC/36M
Document Number: 38-05538 Rev. *R
NC
Page 6 of 35
CY7C1354C
CY7C1356C
Pin Definitions
Pin Name
I/O Type
Pin Description
A0, A1, A
InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
synchronous
BWa, BWb,
BWc, BWd
InputByte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
synchronous the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc
and DQPc, BWd controls DQd and DQPd.
WE
InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/load input used to advance the on-chip address counter or load a new address. When
synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address
can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW to
load a new address.
CLK
Inputclock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
OE
InputOutput enable, active LOW. Combined with the synchronous logic block inside the device to control the
asynchronous direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted
HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the data portion of a Write
sequence, during the first clock when emerging from a deselected state and when the device has been
deselected.
CEN
InputClock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
DQS
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
addresses during the previous clock rise of the read cycle. The direction of the pins is controlled by OE
and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQa–DQd are placed in a tristate condition. The outputs are automatically tristated during the data portion
of a write sequence, during the first clock when emerging from a deselected state, and when the device
is deselected, regardless of the state of OE.
DQPX
I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQ[a:d]. During write
synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd.
MODE
Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled
LOW selects the linear burst order. MODE should not change states during operation. When left floating
MODE will default HIGH, to an interleaved burst order.
TDO
JTAG serial Serial data out to the JTAG circuit. Delivers data on the negative edge of TCK.
output
synchronous
TDI
JTAG serial Serial data in to the JTAG circuit. Sampled on the rising edge of TCK.
input
synchronous
TMS
Test mode This pin controls the test access port state machine. Sampled on the rising edge of TCK.
select
synchronous
Document Number: 38-05538 Rev. *R
Page 7 of 35
CY7C1354C
CY7C1356C
Pin Definitions (continued)
Pin Name
TCK
VDD
VDDQ
I/O Type
Pin Description
JTAG-clock Clock input to the JTAG circuitry.
Power supply Power supply inputs to the core of the device.
I/O power
supply
Power supply for the I/O circuitry.
VSS
Ground
NC
–
No connects. This pin is not connected to the die.
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
–
These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M, 288M,
576M, and 1G densities.
ZZ
Ground for the device. Should be connected to ground of the system.
InputZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with
asynchronous data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
Functional Overview
The CY7C1354C/CY7C1356C are synchronous-pipelined burst
NoBL SRAMs designed specifically to eliminate wait states
during write/read transitions. All synchronous inputs pass
through input registers controlled by the rising edge of the clock.
The clock signal is qualified with the clock enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and all
internal states are maintained. All synchronous operations are
qualified with CEN. All data outputs pass through output registers
controlled by the rising edge of the clock. Maximum access delay
from the clock rise (tCO) is 2.8 ns (250 MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW[d:a] can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected to
load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and enables the requested data to propagate to the
input of the output register. At the rising edge of the next clock
the requested data is allowed to propagate through the output
Document Number: 38-05538 Rev. *R
register and to the data bus within 2.8 ns (250 MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW for the device to drive out
the requested data. During the second clock, a subsequent
operation (read/write/deselect) can be initiated. Deselecting the
device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output tristates following the next clock rise.
Burst Read Accesses
The CY7C1354C/CY7C1356C have an on-chip burst counter
that enables the user the ability to supply a single address and
conduct up to four reads without reasserting the address inputs.
ADV/LD must be driven LOW to load a new address into the
SRAM, as described in Single Read Accesses. The sequence of
the burst counter is determined by the MODE input signal. A
LOW input on MODE selects a linear burst mode, a HIGH selects
an interleaved burst sequence. Both burst counters use A0 and
A1 in the burst sequence, and wrap around when incremented
sufficiently. A HIGH input on ADV/LD increments the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (read or write) is maintained throughout the
burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to A0–A16 is loaded into
the address register. The write signals are latched into the
control logic block.
On the subsequent clock rise the data lines are automatically
tristated regardless of the state of the OE input signal. This
enables the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354C and DQa,b/DQPa,b for
CY7C1356C). In addition, the address for the subsequent
Page 8 of 35
CY7C1354C
CY7C1356C
access (read/write/deselect) is latched into the address register
if the appropriate control signals are asserted.
driven in each cycle of the burst write to write the correct bytes
of data.
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354C and DQa,b/DQPa,b for
CY7C1356C or a subset for byte write operations, see the table
Partial Truth Table for Read/Write on page 11 for details) inputs
is latched into the device and the write is complete.
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1354C and BWa,b for CY7C1356C) signals.
The CY7C1354C/CY7C1356C provides byte write capability that
is described in the Write Cycle Description table. Asserting the
write enable input (WE) with the selected byte write select (BW)
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation remain unaltered. A
synchronous self-timed write mechanism is provided to simplify
the write operations. Byte write capability is included to greatly
simplify read/modify/write sequences, which can be reduced to
simple byte write operations.
Sleep Mode
Because the CY7C1354C/CY7C1356C are common I/O
devices, data should not be driven into the device while the
outputs are active. The output enable (OE) can be deasserted
HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354C and DQa,b/DQPa,b for
CY7C1356C) inputs. Doing so will tristate the output drivers. As
a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1354C and DQa,b/DQPa,b for CY7C1356C) are
automatically tristated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation ‘sleep’ mode. Two clock
cycles are required to enter into or exit from this ‘sleep’ mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
Linear Burst Address Table
(MODE = GND)
The CY7C1354C/CY7C1356C has an on-chip burst counter that
enables the user the ability to supply a single address and
conduct up to four write operations without reasserting the
address inputs. ADV/LD must be driven LOW to load the initial
address, as described in Single Write Accesses on page 8.
When ADV/LD is driven HIGH on the subsequent clock rise, the
chip enables (CE1, CE2, and CE3) and WE inputs are ignored
and the burst counter is incremented. The correct BW (BWa,b,c,d
for CY7C1354C and BWa,b for CY7C1356C) inputs must be
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Document Number: 38-05538 Rev. *R
Test Conditions
ZZ  VDD 0.2 V
ZZ VDD  0.2 V
ZZ  0.2 V
This parameter is sampled
This parameter is sampled
Min
–
–
2tCYC
–
0
Max
50
2tCYC
–
2tCYC
–
Unit
mA
ns
ns
ns
ns
Page 9 of 35
CY7C1354C
CY7C1356C
Truth Table
The Truth Table for CY7C1354C/CY7C1356C follows. [2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
CE ZZ ADV/LD WE BWx OE CEN CLK
DQ
Deselect cycle
None
H
L
L
X
X
X
L
L–H
Tri-state
Continue deselect cycle
None
X
L
H
X
X
X
L
L–H
Tri-state
Read cycle (begin burst)
External
L
L
L
H
X
L
L
L–H
Data out (Q)
Next
X
L
H
X
X
L
L
L–H
Data out (Q)
External
L
L
L
H
X
H
L
L–H
Tri-state
Next
X
L
H
X
X
H
L
L–H
Tri-state
External
L
L
L
L
L
X
L
L–H
Data in (D)
Write cycle (continue burst)
Next
X
L
H
X
L
X
L
L–H
Data in (D)
NOP/WRITE ABORT (begin burst)
None
L
L
L
L
H
X
L
L–H
Tri-state
WRITE ABORT (continue burst)
Next
X
L
H
X
H
X
L
L–H
Tri-state
Current
X
L
X
X
X
X
H
L–H
–
None
X
H
X
X
X
X
X
X
Tri-state
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
IGNORE CLOCK EDGE (stall)
SLEEP MODE
Notes
2. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWX = L signifies at least one byte write select is active, BWX = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
3. Write is defined by WE and BWX. See Write Cycle Description table for details.
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal.
6. CEN = H inserts wait states.
7. Device will power up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE is
inactive or when the device is deselected, and DQs = data when OE is active.
Document Number: 38-05538 Rev. *R
Page 10 of 35
CY7C1354C
CY7C1356C
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write for CY7C1354C follows. [9, 10, 11, 12]
Function (CY7C1354C)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write– no bytes written
L
H
H
H
H
Write byte a –(DQa and DQPa)
L
H
H
H
L
Write byte b – (DQb and DQPb)
L
H
H
L
H
Write bytes b, a
L
H
H
L
L
Write byte c –(DQc and DQPc)
L
H
L
H
H
Write bytes c, a
L
H
L
H
L
Write bytes c, b
L
H
L
L
H
Write bytes c, b, a
L
H
L
L
L
Write byte d –(DQd and DQPd)
L
L
H
H
H
Write bytes d, a
L
L
H
H
L
Write bytes d, b
L
L
H
L
H
Write bytes d, b, a
L
L
H
L
L
Write bytes d, c
L
L
L
H
H
Write bytes d, c, a
L
L
L
H
L
Write bytes d, c, b
L
L
L
L
H
Write all bytes
L
L
L
L
L
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write for CY7C1356C follows. [9, 10, 11, 12]
Function (CY7C1356C)
WE
BWb
BWa
Read
H
x
x
Write – no bytes written
L
H
H
Write byte a (DQa and DQPa)
L
H
L
Write byte b – (DQb and DQPb)
L
L
H
Write both bytes
L
L
L
Notes
9. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
10. Write is defined by WE and BWX. See Write Cycle Description table for details.
11. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
12. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document Number: 38-05538 Rev. *R
Page 11 of 35
CY7C1354C
CY7C1356C
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1354C/CY7C1356C incorporates a serial boundary
scan test access port (TAP) in the BGA package only. The TQFP
package does not offer this functionality. This part operates in
accordance with IEEE Standard 1149.1-1900, but does not have
the set of functions required for full 1149.1 compliance. These
functions from the IEEE specification are excluded because their
inclusion places an added delay in the critical speed path of the
SRAM. Note that the TAP controller functions in a manner that
does not conflict with the operation of other devices using 1149.1
fully compliant TAPs. The TAP operates using JEDEC-standard
3.3 V or 2.5 V I/O logic levels.
The CY7C1354C/CY7C1356C contains a TAP controller,
instruction register, boundary scan register, bypass register, and
ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
should be left unconnected. Upon power-up, the device comes
up in a reset state which does not interfere with the operation of
the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 14. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Instruction Codes on page 18).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Document Number: 38-05538 Rev. *R
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
enable data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 15. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to enable
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This enables data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Exit Order on page 19 and Boundary Scan
Exit Order on page 20 show the order in which the bits are
connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 18.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the Instruction
Page 12 of 35
CY7C1354C
CY7C1356C
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail in this section.
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in this SRAM TAP controller, and
therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a high Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and enables
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
Document Number: 38-05538 Rev. *R
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK# captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD enables an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required - that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 13 of 35
CY7C1354C
CY7C1356C
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCA N
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
0
1
EXIT1-DR
0
1
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 38-05538 Rev. *R
Page 14 of 35
CY7C1354C
CY7C1356C
TAP Controller Block Diagram
0
Bypass Register
2 1 0
Selection
Circuitry
TDI
Selection
Circuitry
Instruction Register
TDO
31 30 29 . . . 2 1 0
Identification Register
x . . . . . 2 1 0
Boundary Scan Register
TCK
TAP CONTROLLER
TM S
TAP Timing
1
2
Test Clock
(TCK )
3
t TH
t TM SS
t TM SH
t TDIS
t TDIH
t
TL
4
5
6
t CY C
Test M ode Select
(TM S)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CA RE
Document Number: 38-05538 Rev. *R
UNDEFINED
Page 15 of 35
CY7C1354C
CY7C1356C
TAP AC Switching Characteristics
Over the Operating Range
Parameter [13, 14]
Description
Min
Max
Unit
Clock
tTCYC
TCK clock cycle time
50
–
ns
tTF
TCK clock frequency
–
20
MHz
tTH
TCK clock HIGH time
20
–
ns
tTL
TCK clock LOW time
20
–
ns
tTDOV
TCK clock LOW to TDO valid
–
10
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
tTMSS
TMS setup to TCK clock rise
5
–
ns
tTDIS
TDI setup to TCK clock rise
5
–
ns
tCS
Capture setup to TCK rise
5
–
ns
tTMSH
TMS hold after TCK clock rise
5
–
ns
tTDIH
TDI hold after clock rise
5
–
ns
tCH
Capture hold after clock rise
5
–
ns
Output Times
Setup Times
Hold Times
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input rise and fall times ...................................................1 ns
Input pulse levels ............................................... VSS to 2.5 V
Input rise and fall time ....................................................1 ns
Input timing reference levels ......................................... 1.5 V
Input timing reference levels ....................................... 1.25 V
Output reference levels ................................................ 1.5 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage ............................ 1.5 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
TDO
50Ω
TDO
Z O= 50Ω
20pF
Z O= 50Ω
20pF
Notes
13. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
14. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document Number: 38-05538 Rev. *R
Page 16 of 35
CY7C1354C
CY7C1356C
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)
Parameter [15]
VOH1
Description
Output HIGH voltage
Min
Max
Unit
IOH = –4.0 mA, VDDQ = 3.3 V
Test Conditions
2.4
–
V
IOH = –1.0 mA, VDDQ = 2.5 V
2.0
–
V
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
VDDQ = 3.3 V
–
0.4
V
VDDQ = 2.5 V
–
0.4
V
VDDQ = 3.3 V
–
0.2
V
VOH2
Output HIGH voltage
IOH = –100 µA
VOL1
Output LOW voltage
IOL = 8.0 mA
VOL2
Output LOW voltage
VIH
Input HIGH voltage
VIL
Input LOW voltage
IX
Input load current
IOL = 100 µA
GND < VIN < VDDQ
VDDQ = 2.5 V
–
0.2
V
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 3.3 V
–0.3
0.8
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
Note
15. All voltages referenced to VSS (GND).
Document Number: 38-05538 Rev. *R
Page 17 of 35
CY7C1354C
CY7C1356C
Identification Register Definitions
Instruction Field
CY7C1354C
CY7C1356C
000
000
01011001000100110
01011001000010110
00000110100
00000110100
1
1
Revision number (31:29)
Cypress device ID (28:12) [16]
Cypress JEDEC ID (11:1)
ID register presence (0)
Description
Reserved for version number.
Reserved for future use.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 36)
Bit Size (× 18)
3
3
Instruction
Bypass
1
1
ID
32
32
Boundary scan order (119-ball BGA package)
69
69
Boundary scan order (165-ball FBGA package)
69
69
Instruction Codes
Code
Description
EXTEST
Instruction
000
Captures the input/output ring contents. Places the boundary scan register between the TDI
and TDO. Forces all SRAM outputs to high Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input/output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the input/output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Note
16. Bit #24 is “1” in the Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 38-05538 Rev. *R
Page 18 of 35
CY7C1354C
CY7C1356C
Boundary Scan Exit Order
(256 K × 36)
Bit #
119-ball ID
165-ball ID
Bit #
119-ball ID
165-ball ID
1
K4
B6
31
B5
R9
2
H4
B7
32
A5
P9
3
M4
A7
33
C6
R8
4
F4
B8
34
A6
P8
5
B4
A8
35
P4
R6
6
G4
A9
36
N4
P6
7
C3
B10
37
R6
R4
8
B3
A10
38
T5
P4
9
D6
C11
39
T3
R3
10
H7
E10
40
R2
P3
11
G6
F10
41
R3
R1
12
E6
G10
42
P2
N1
13
D7
D10
43
P1
L2
14
E7
D11
44
L2
K2
15
F6
E11
45
K1
J2
16
G7
F11
46
N2
M2
17
H6
G11
47
N1
M1
18
T7
H11
48
M2
L1
19
K7
J10
49
L1
K1
20
L6
K10
50
K2
J1
21
N6
L10
51
22
P7
M10
52
H1
Not Bonded (Preset to 1) Not Bonded (Preset to 1)
G2
23
N7
J11
53
G2
F2
24
M6
K11
54
E2
E2
25
L7
L11
55
D1
D2
26
K6
M11
56
H2
G1
27
P6
N11
57
G1
F1
28
T4
R11
58
F2
E1
29
A3
R10
59
E1
D1
30
C5
P10
60
D2
C1
61
C2
B2
Document Number: 38-05538 Rev. *R
Page 19 of 35
CY7C1354C
CY7C1356C
Boundary Scan Exit Order
(512 K × 18)
Bit #
119-ball ID
165-ball ID
Bit #
119-ball ID
165-ball ID
1
K4
B6
37
R6
R4
2
H4
B7
38
T5
P4
3
M4
A7
39
T3
R3
4
F4
B8
40
R2
P3
5
B4
A8
41
R3
R1
6
G4
A9
42
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
7
C3
B10
43
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
8
B3
A10
44
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
T2
A11
45
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
9
10
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
46
11
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
12
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
P2
N1
47
N1
M1
48
M2
L1
13
D6
C11
49
L1
K1
14
E7
D11
50
K2
J1
15
F6
E11
51
16
G7
F11
52
H1
17
H6
G11
53
G2
F2
18
T7
H11
54
E2
E2
19
K7
J10
55
D1
D2
20
L6
K10
56
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
21
N6
L10
57
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
22
P7
M10
58
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
Not Bonded (Preset to 1) Not Bonded (Preset to 1)
G2
23
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
59
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
24
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
60
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
25
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
61
C2
B2
26
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
62
A2
A2
27
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
63
E4
A3
T6
R11
64
B2
B3
29
A3
R10
65
30
C5
P10
66
G3
Not Bonded (Preset to 0)
31
B5
R9
67
Not Bonded (Preset to 0)
A4
32
A5
P9
68
L5
B5
33
C6
R8
69
B6
A6
34
A6
P8
35
P4
R6
36
N4
P6
28
Document Number: 38-05538 Rev. *R
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
Page 20 of 35
CY7C1354C
CY7C1356C
Maximum Ratings
Operating Range
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Range
Ambient
Temperature
Storage temperature ................................ –65 °C to +150 °C
Commercial
0 °C to +70 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Industrial
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC to outputs in tri-state ...................–0.5 V to VDDQ + 0.5 V
DC input voltage ................................. –0.5 V to VDD + 0.5 V
–40 °C to +85 °C
VDDQ
3.3 V– 5% / 2.5 V – 5% to
+ 10%
VDD
Neutron Soft Error Immunity
Parameter
Description
Test
Conditions Typ
Max*
Unit
LSBU
Logical
single-bit
upsets
25 °C
320
368
FIT/
Mb
LMBU
Logical
multi-bit
upsets
25 °C
0
0.01
FIT/
Mb
Single event
latch-up
85 °C
0
0.1
FIT/
Dev
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) .......................... > 2001 V
VDD
Latch-up current .................................................... > 200 mA
SEL
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to Application
Note AN 54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter [17, 18]
Description
VDD
Power supply voltage
VDDQ
I/O supply voltage
VOH
VOL
VIH
VIL
IX
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Min
Max
Unit
3.135
3.6
V
for 3.3 V I/O
3.135
VDD
V
for 2.5 V I/O
2.375
2.625
V
for 3.3 V I/O, IOH =4.0 mA
2.4
–
V
for 2.5 V I/O, IOH =1.0 mA
2.0
–
V
for 3.3 V I/O, IOL=8.0 mA
–
0.4
V
for 2.5 V I/O, IOL=1.0 mA
–
0.4
V
for 3.3 V I/O
2.0
VDD + 0.3 V
V
for 2.5 V I/O
1.7
VDD + 0.3 V
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
Input leakage current except ZZ GND  VI  VDDQ
and MODE
–5
5
A
Input current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input = VDD
–
30
A
GND  VI  VDDQ, output disabled
–5
5
A
Input LOW voltage
[19]
Input current of ZZ
IOZ
Test Conditions
Output leakage current
Notes
17. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
18. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ <VDD.
19. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05538 Rev. *R
Page 21 of 35
CY7C1354C
CY7C1356C
Electrical Characteristics (continued)
Over the Operating Range
Parameter [17, 18]
IDD
Description
Test Conditions
VDD operating supply
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
Automatic CE power-down
current — TTL inputs
ISB1
Max VDD, device deselected,
VIN  VIH or VIN  VIL,
f = fMAX = 1/tCYC
Min
Max
Unit
4 ns cycle,
250 MHz
–
250
mA
5 ns cycle,
200 MHz
–
220
mA
6 ns cycle,
166 MHz
–
180
mA
4 ns cycle,
250 MHz
–
130
mA
5 ns cycle,
200 MHz
–
120
mA
6 ns cycle,
166 MHz
–
110
mA
ISB2
Automatic CE power-down
current — CMOS inputs
All speed
Max VDD, device deselected,
VIN  0.3 V or VIN > VDDQ 0.3 V, grades
f=0
–
40
mA
ISB3
Automatic CE power-down
current — CMOS inputs
Max VDD, device deselected,
4 ns cycle,
VIN  0.3 V or VIN > VDDQ 0.3 V, 250 MHz
f = fMAX = 1/tCYC
5 ns cycle,
200 MHz
–
120
mA
–
110
mA
6 ns cycle,
166 MHz
–
100
mA
All speed
grades
–
40
mA
Automatic CE power-down
current — TTL inputs
ISB4
Max VDD, device deselected,
VIN  VIH or VIN  VIL, f = 0
Capacitance
Parameter [20]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/output capacitance
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
100-pin TQFP 119-ball BGA 165-ball FBGA Unit
Max
Max
Max
5
5
5
pF
5
5
5
pF
5
7
7
pF
Thermal Resistance
Parameter [20]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Test
conditions
follow
standard test methods and
procedures for measuring
thermal impedance, per
EIA/JESD51.
100-pin TQFP 119-ball BGA 165-ball FBGA Unit
Max
Max
Max
29.41
34.1
16.8
°C/W
6.13
14.0
3.0
°C/W
Note
20. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05538 Rev. *R
Page 22 of 35
CY7C1354C
CY7C1356C
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317 
3.3 V
OUTPUT
OUTPUT
RL = 50 
Z0 = 50 
VT = 1.5 V
(a)
INCLUDING
JIG AND
SCOPE
OUTPUT
RL = 50 
VT = 1.25 V
(a)
Document Number: 38-05538 Rev. *R
R = 351 
10%
(c)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
 1 ns
(b)
GND
5 pF
R = 1538 
(b)
90%
10%
90%
 1 ns
R = 1667 
2.5 V
Z0 = 50 
GND
5 pF
2.5 V I/O Test Load
OUTPUT
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
 1 ns
 1 ns
(c)
Page 23 of 35
CY7C1354C
CY7C1356C
Switching Characteristics
Over the Operating Range
Parameter [21, 22]
tPower[23]
-250
Description
VCC(typical) to the first access read or
write
-200
-166
Min
Max
Min
Max
Min
Max
1
–
1
–
1
–
Unit
ms
Clock
tCYC
Clock cycle time
FMAX
Maximum operating frequency
4.0
–
5
–
6
–
ns
–
250
–
200
–
166
MHz
tCH
Clock HIGH
1.8
–
2.0
–
2.4
–
ns
tCL
Clock LOW
1.8
–
2.0
–
2.4
–
ns
tEOV
OE LOW to output valid
–
2.8
–
3.2
–
3.5
ns
tCLZ
Clock to low Z [24, 25, 26]
1.25
–
1.5
–
1.5
–
ns
–
2.8
–
3.2
–
3.5
ns
Output Times
tCO
Data output valid after CLK rise
tEOV
OE LOW to output valid
tDOH
Data output hold after CLK rise
tCHZ
tCLZ
tEOHZ
tEOLZ
Clock to high Z
Clock to low Z
[24, 25, 26]
[24, 25, 26]
OE HIGH to output high Z
OE LOW to output low Z
[24, 25, 26]
[24, 25, 26]
–
2.8
–
3.2
–
3.5
ns
1.25
–
1.5
–
1.5
–
ns
1.25
2.8
1.5
3.2
1.5
3.5
ns
1.25
–
1.5
–
1.5
–
ns
–
2.8
–
3.2
–
3.5
ns
0
–
0
–
0
–
ns
Setup Times
tAS
Address setup before CLK rise
1.4
–
1.5
–
1.5
–
ns
tDS
Data input setup before CLK rise
1.4
–
1.5
–
1.5
–
ns
tCENS
CEN setup before CLK rise
1.4
–
1.5
–
1.5
–
ns
tWES
WE, BWx setup before CLK rise
1.4
–
1.5
–
1.5
–
ns
tALS
ADV/LD setup before CLK rise
1.4
–
1.5
–
1.5
–
ns
tCES
Chip select setup
1.4
–
1.5
–
1.5
–
ns
tAH
Address hold after CLK rise
0.4
–
0.5
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.4
–
0.5
–
0.5
–
ns
tCENH
CEN hold after CLK rise
0.4
–
0.5
–
0.5
–
ns
tWEH
WE, BWx hold after CLK rise
0.4
–
0.5
–
0.5
–
ns
tALH
ADV/LD hold after CLK rise
0.4
–
0.5
–
0.5
–
ns
tCEH
Chip select hold after CLK rise
0.4
–
0.5
–
0.5
–
ns
Hold Times
Notes
21. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
22. Test conditions shown in (a) of Figure 4 on page 23 unless otherwise noted.
23. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be initiated.
24. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
25. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
26. This parameter is sampled and not 100% tested.
Document Number: 38-05538 Rev. *R
Page 24 of 35
CY7C1354C
CY7C1356C
Switching Waveforms
Figure 5. Read/Write Timing [27, 28, 29]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
10
CLK
t CENS
t CENH
t CES
t CEH
t CH
t CL
CEN
CE
ADV/LD
WE
BW x
A1
ADDRESS
A2
A7
t CO
t AS
t DS
t AH
Data
In-Out (DQ)
t DH
D(A1)
t CLZ
D(A2)
D(A2+1)
t DOH
Q(A3)
t OEV
Q(A4)
t CHZ
Q(A4+1)
D(A5)
Q(A6)
t OEHZ
t DOH
t OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
DON’T CARE
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes
27. For this waveform ZZ is tied low.
28. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
29. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 38-05538 Rev. *R
Page 25 of 35
CY7C1354C
CY7C1356C
Switching Waveforms (continued)
Figure 6. NOP, STALL, and DESELECT Cycles [30, 31, 32]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
ADDRESS
A5
t CHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
DON’T CARE
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Notes
30. For this waveform ZZ is tied low.
31. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
32. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
Document Number: 38-05538 Rev. *R
Page 26 of 35
CY7C1354C
CY7C1356C
Switching Waveforms (continued)
Figure 7. ZZ Mode Timing [33, 34]
CLK
t ZZ
ZZ
I
t
t ZZREC
ZZI
SUPPLY
I DDZZ
t RZZI
A LL INPUTS
DESELECT or READ Only
(except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Notes
33. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
34. I/Os are in high Z when exiting ZZ sleep mode.
Document Number: 38-05538 Rev. *R
Page 27 of 35
CY7C1354C
CY7C1356C
Ordering Information
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices
Speed
(MHz)
166
Ordering Code
CY7C1354C-166AXC
Package
Diagram
Part and Package Type
Operating
Range
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Industrial
CY7C1354C-200AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1354C-200AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Industrial
CY7C1356C-250AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1356C-166AXC
CY7C1354C-166AXI
CY7C1356C-166AXI
200
250
Ordering Code Definitions
CY
7
C 135X
C - XXX XX
X X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = A or BG
A = 100-pin TQFP
BG = 119-ball BGA
Speed Grade:
XXX = 166 MHz or 200 MHz or 250 MHz
Process Technology  90 nm
135X = 1354 or 1356
1354 = PL, 256 Kb × 36 (9 Mb)
1356 = PL, 512 Kb × 18 (9 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05538 Rev. *R
Page 28 of 35
CY7C1354C
CY7C1356C
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 38-05538 Rev. *R
Page 29 of 35
CY7C1354C
CY7C1356C
Package Diagrams (continued)
Figure 9. 119-ball PBGA (14 × 22 × 2.4 mm) BG119 Package Outline, 51-85115
51-85115 *D
Document Number: 38-05538 Rev. *R
Page 30 of 35
CY7C1354C
CY7C1356C
Package Diagrams (continued)
Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *G
Document Number: 38-05538 Rev. *R
Page 31 of 35
CY7C1354C
CY7C1356C
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BGA
Ball Grid Array
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CEN
Clock Enable
µA
microampere
EIA
Electronic Industries Alliance
mA
milliampere
FBGA
Fine-Pitch Ball Grid Array
mm
millimeter
I/O
Input/Output
ms
millisecond
JEDEC
Joint Electron Devices Engineering Council
mV
millivolt
JTAG
Joint Test Action Group
ns
nanosecond
LMBU
Logical Multi-Bit Upsets
LSB
Least Significant Bit
LSBU
Logical Single-Bit Upsets
MSB
Most Significant Bit
NoBL
No Bus Latency
OE
Output Enable
SEL
Single Event Latch-up
SRAM
Static Random Access Memory
TAP
Test Access Port
TCK
Test Clock
TDI
Test Data-In
TDO
Test Data-Out
TMS
Test Mode Select
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
WE
Write Enable
Document Number: 38-05538 Rev. *R
Symbol
Unit of Measure

ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 32 of 35
CY7C1354C
CY7C1356C
Document History Page
Document Title: CY7C1354C/CY7C1356C, 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05538
Revision
ECN
Submission
Date
Orig. of
Change
**
242032
See ECN
RKF
New data sheet
*A
278130
See ECN
RKF
Changed Boundary Scan order to match the B Rev of these devices
Changed TQFP pkg to Lead-free TQFP in Ordering Information section
Added comment of Lead-free BG and BZ packages availability
*B
284431
See ECN
VBL
Changed ISB1 and ISB3 from DC Characteristic table as follows
ISB1: 225 mA-> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA
ISB3: 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA
Add BG and BZ pkg lead-free part numbers to ordering info section
*C
320834
See ECN
PCI
Changed 225 MHz to 250 MHz
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Unshaded frequencies of 250, 200, 166 MHz in AC/DC Tables and Selection
Guide
Changed JA and JC for TQFP Package from 25 and 9 C/W to 29.41 and
6.13 C/W respectively
Changed JA and JC for BGA Package from 25 and 6 C/W to 34.1 and
14.0 C/W respectively
Changed JA and JC for FBGA Package from 27 and 6 C/W to 16.8 and
3.0 C/W respectively
Modified VOL, VOH test conditions
Added Lead-Free product information
Updated Ordering Information Table
Changed from Preliminary to Final
*D
351895
See ECN
PCI
Changed ISB2 from 35 to 40 mA
Updated Ordering Information Table
*E
377095
See ECN
PCI
Modified test condition in note# 15 from VDDQ < VDD to VDDQ  VDD
*F
408298
See ECN
RXU
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed three-state to tri-state.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Replaced Package Name column with Package Diagram in the Ordering
Information table.
*G
501793
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC
Switching Characteristics table.
Updated the Ordering Information table.
*H
2756340
08/26/2009
*I
3033272
09/19/2010
*J
3052882
10/08/2010
NJY
Removed obsolete part numbers.
*K
3186089
03/02/2011
NJY
Updated Ordering Information.
Updated Package Diagrams.
Document Number: 38-05538 Rev. *R
Description of Change
VKN/AESA Updated template
Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are available and
modified the disclaimer for the Ordering information.
NJY
Added Ordering Code Definitions under Ordering Information.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
Page 33 of 35
CY7C1354C
CY7C1356C
Document History Page (continued)
Document Title: CY7C1354C/CY7C1356C, 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05538
Revision
ECN
Submission
Date
Orig. of
Change
Description of Change
*L
3210400
03/30/2011
NJY
Removed pruned part “CY7C1354C-200BGC” from the ordering information
table.
*M
3385314
09/29/2011
PRIT
No technical updates.
*N
3754982
09/25/2012
PRIT
Updated Package Diagrams (spec 51-85115 (Changed revision from *C to *D),
(spec 51-85180 (Changed revision from *C to *F)).
*O
3861238
01/10/2013
PRIT
Updated Ordering Information (Updated part numbers).
*P
4537527
10/14/2014
PRIT
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
*Q
4574263
11/19/2014
PRIT
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Ordering Information:
Removed pruned part CY7C1354C-250AXC.
*R
4974141
10/19/2015
PRIT
Updated Package Diagrams:
spec 51-85180 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05538 Rev. *R
Page 34 of 35
CY7C1354C
CY7C1356C
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05538 Rev. *R
Revised October 19, 2015
Page 35 of 35
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.