CYPRESS CY7C1441AV25

CY7C1441AV25
CY7C1447AV25
36-Mbit (1 M × 36/512 K × 72)
Flow-Through SRAM
36-Mbit (1 M × 36/512 K × 72) Flow-Through SRAM
Features
Functional Description
■
Supports 133 MHz bus operations
■
1 M × 36/512 K × 72 common I/O
■
2.5 V core power supply
■
2.5 V and 1.8 V I/O power supply
■
Fast clock-to-output times
❐ 6.5 ns (133 MHz version)
■
Provide high performance 2-1-1-1 access rate
■
User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self timed write
■
Asynchronous output enable
■
CY7C1441AV25 available in Pb-free 165-ball FBGA package.
CY7C1447AV25 available in non Pb-free 209-ball FBGA
package.
■
JTAG boundary scan for FBGA package
■
ZZ sleep mode option
The
CY7C1441AV25/CY7C1447AV25
are
2.5 V,
1 M × 36/512 K × 72 Synchronous Flow-Through SRAMs,
designed to interface with high speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133 MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining Chip Enable (CE1), depth expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BWx and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
The CY7C1441AV25/CY7C1447AV25 allows either interleaved
or linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence and a LOW selects
a linear burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either ADSP or ADSC are active. Subsequent burst
addresses can be internally generated as controlled by the ADV.
The CY7C1441AV25/CY7C1447AV25 operates from a
+2.5 V core power supply while all outputs may operate with
either a +2.5 V or 1.8 V supply. All inputs and outputs are
JEDEC-standard JESD8-5 compatible.
Selection Guide
Description
133 MHz
Unit
Maximum Access Time
6.5
ns
Maximum Operating Current
270
mA
Maximum CMOS Standby Current
120
mA
Cypress Semiconductor Corporation
Document Number: 001-75380 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 7, 2013
CY7C1441AV25
CY7C1447AV25
Logic Block Diagram – CY7C1441AV25
ADDRESS
REGISTER
A 0, A1, A
A [1:0]
MODE
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADV
CLK
ADSC
ADSP
DQ D , DQP D
BW D
BYTE
WRITE REGISTER
DQ C, DQP C
BW C
BYTE
WRITE REGISTER
DQ D , DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B , DQP B
BW B
DQ B , DQP B
BYTE
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQ s
DQP A
DQP B
DQP C
DQP D
WRITE REGISTER
DQ A , DQP A
BW A
BWE
DQ A , DQPA
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
GW
ENABLE
REGISTER
CE1
CE2
INPUT
REGISTERS
CE3
OE
ZZ
SLEEP
CONTROL
Document Number: 001-75380 Rev. *B
Page 2 of 33
CY7C1441AV25
CY7C1447AV25
Logic Block Diagram – CY7C1447AV25
ADDRESS
REGISTER
A0, A1,A
A[1:0]
MODE
BURST Q1
COUNTER
AND LOGIC
CLR
Q0
ADV
CLK
ADSC
ADSP
BW H
DQ H , DQPH
WRITE REGISTER
DQ H , DQPH
WRITE DRIVER
BW G
DQ F, DQPF
WRITE REGISTER
DQ G , DQPG
WRITE DRIVER
BW F
DQ F, DQPF
WRITE REGISTER
DQ F, DQPF
WRITE DRIVER
BW E
DQ E , DQPE
WRITE REGISTER
DQ
E , DQP
“a” E
BYTE
WRITE DRIVER
BW D
DQ D , DQPD
WRITE REGISTER
DQ D , DQPD
WRITE DRIVER
BW C
DQ C, DQPC
WRITE REGISTER
DQ C, DQPC
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
BW B
BW A
BWE
GW
CE1
CE2
CE3
OE
ZZ
DQ B , DQPB
WRITE REGISTER
DQ A , DQPA
WRITE REGISTER
ENABLE
REGISTER
OUTPUT
BUFFERS
DQs
DQP A
DQP B
DQP C
DQP D
DQP E
DQP F
DQP G
DQP H
DQ B , DQPB
WRITE DRIVER
DQ A , DQPA
WRITE DRIVER
INPUT
REGISTERS
SLEEP
CONTROL
Document Number: 001-75380 Rev. *B
Page 3 of 33
CY7C1441AV25
CY7C1447AV25
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Single Write Accesses Initiated by ADSP ................... 8
Single Write Accesses Initiated by ADSC ................... 8
Burst Sequences ......................................................... 9
Sleep Mode ................................................................. 9
Interleaved Burst Address Table ................................. 9
Linear Burst Address Table ......................................... 9
ZZ Mode Electrical Characteristics .............................. 9
Truth Table ...................................................................... 10
Partial Truth Table for Read/Write ................................ 11
Partial Truth Table for Read/Write ................................ 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
Test Access Port (TAP) ............................................. 12
Performing a TAP Reset ........................................... 12
TAP Registers ........................................................... 12
TAP Instruction Set ................................................... 12
Tap Controller State Diagram ........................................ 14
Tap Controller Block Diagram ....................................... 15
TAP Timing ...................................................................... 15
TAP AC Switching Characteristics ............................... 16
2.5 V TAP AC Test Conditions ....................................... 17
2.5 V TAP AC Output Load Equivalent ......................... 17
1.8 V TAP AC Test Conditions ....................................... 17
1.8 V TAP AC Output Load Equivalent ......................... 17
Document Number: 001-75380 Rev. *B
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Identification Codes ....................................................... 18
Boundary Scan Order .................................................... 19
Boundary Scan Order .................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Electrical Characteristics ............................................... 21
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Timing Diagrams ............................................................ 24
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Package Diagrams .......................................................... 29
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC Solutions ......................................................... 33
Page 4 of 33
CY7C1441AV25
CY7C1447AV25
Pin Configurations
Figure 1. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1441AV25 (1 M × 36)
1
2
3
4
5
6
7
8
9
10
BWC
BWB
CE3
ADV
A
11
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
A
CE1
BWE
ADSC
NC/144M
A
CE2
BWD
BWA
CLK
GW
OE
ADSP
A
NC/576M
DQPC
DQC
NC
DQC
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
DQB
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
DQC
NC
DQD
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
R
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
Document Number: 001-75380 Rev. *B
Page 5 of 33
CY7C1441AV25
CY7C1447AV25
Pin Configurations (continued)
Figure 2. 209-ball FBGA (14 × 22 × 1.76 mm) pinout
CY7C1447AV25 (512 K × 72)
1
2
4
5
6
7
8
9
10
11
A
DQG
DQG
B
DQG
CE2
ADSP
ADSC
ADV
CE3
A
DQB
DQB
DQG
BWSC
BWSG NC/288M BW
A
BWSB
BWSF
DQB
DQB
C
DQG
DQG
BWSH
BWSD NC/144M CE1
NC/576M
BWSE
BWSA
DQB
DQB
D
DQG
DQG
VSS
NC
NC/1G
OE
NC
VSS
E
DQB
DQB
DQPG
DQPC
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPF
DQPB
F
DQC
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQF
DQF
G
DQC
DQC
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQF
DQF
H
DQC
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQF
DQF
J
DQC
DQC
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQF
DQF
K
NC
NC
CLK
NC
VSS
VSS
VSS
NC
NC
NC
NC
L
DQH
DQH
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
M
DQH
DQH
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQA
DQA
N
DQH
DQH
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
P
DQH
DQH
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
DQA
DQA
R
DQPD
DQPH
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
T
DQD
DQD
VSS
NC
NC
MODE
NC
NC
VSS
DQE
DQE
U
DQD
DQD
A
A
A
A
A
A
DQE
DQE
V
DQD
DQD
A
A
A
A1
A
A
A
DQE
DQE
W
DQD
DQD
TMS
TDI
A
A0
A
TCK
DQE
DQE
Document Number: 001-75380 Rev. *B
3
A
NC/72M
GW
TDO
DQPA
DQPE
Page 6 of 33
CY7C1441AV25
CY7C1447AV25
Pin Definitions
Name
A0, A1, A
I/O
Description
InputAddress Inputs. Used to select one of the address locations. Sampled at the rising edge of the CLK if
Synchronous ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter.
InputByte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
BWA, BWB,
BWC, BWD, Synchronous Sampled on the rising edge of CLK.
BWE, BWF,
BWG, BWH
GW
CLK
InputGlobal Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
InputClock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW during a burst operation.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
OE
InputOutput Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated and act as input data pins.
OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
InputAdvance Input Signal. Sampled on the rising edge of CLK. When asserted, it automatically increments
Synchronous the address in a burst cycle.
ADSP
InputAddress Strobe from Processor. Sampled on the rising edge of CLK, active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
InputAddress Strobe from Controller. Sampled on the rising edge of CLK, active LOW. When asserted LOW,
Synchronous addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
BWE
InputByte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a byte write.
ZZ
InputZZ Sleep Input, Active HIGH. When asserted HIGH places the device in a non time-critical “sleep”
Asynchronous condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ
pin has an internal pull down.
DQs
I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed
in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence,
during the first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
DQPX
I/OBidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPx is controlled by BWX correspondingly.
MODE
Input-Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode pin has an internal pull up.
VDD
VDDQ
Power Supply Power Supply Inputs to the Core of the Device.
I/O Power
Supply
Power Supply for I/O Circuitry.
Document Number: 001-75380 Rev. *B
Page 7 of 33
CY7C1441AV25
CY7C1447AV25
Pin Definitions (continued)
Name
VSS
VSSQ
I/O
Ground
Description
Ground for the Core of the Device.
I/O Ground Ground for I/O Circuitry.
TDO
JTAG Serial Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG feature is
not utilized, this pin should be left unconnected.
Output
Synchronous
TDI
JTAG Serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not utilized,
Input
this pin can be left floating or connected to VDD through a pull up resistor.
Synchronous
TMS
JTAG Serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not utilized,
Input
this pin can be disconnected or connected to VDD.
Synchronous
TCK
JTAGClock
Clock Input to the JTAG Circuitry. If the JTAG feature is not utilized, this pin must be connected to VSS.
NC
–
No Connects. Not internally connected to the die.
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
–
No Connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M, and NC/1G
are address expansion pins and are not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t CDV) is 6.5 ns (133 MHz device).
The CY7C1441AV25/CY7C1447AV25 supports secondary
cache in systems utilizing either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium and
i486™ processors. The linear burst sequence is suited for
processors that utilize a linear burst sequence. The burst order
is user selectable and is determined by sampling the MODE
input. Accesses are initiated with either ADSP or ADSC. Address
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWx) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous self
timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter or control
logic and presented to the memory core. If the OE input is
Document Number: 001-75380 Rev. *B
asserted LOW, the requested data is available as the data
outputs a maximum to tCDV after clock rise. ADSP is ignored if
CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BWX) are ignored during this first clock cycle. If the write
inputs are asserted active (see Truth Table on page 10 for
appropriate states that indicate a write) on the next clock rise, the
appropriate data is latched and written into the device. Byte
writes are allowed. All I/Os are tri-stated during a byte write.
Because this is a common I/O device, the asynchronous OE
input signal must be deasserted and the I/Os must be tri-stated
prior to the presentation of data to DQs. As a safety precaution,
the data lines are tri-stated when a write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter or control logic and delivered to the
memory core. The information presented to DQS is written into
the specified address location. Byte writes are allowed. All I/Os
are tri-stated when a write is detected, even a byte write.
Because this is a common I/O device, the asynchronous OE
input signal must be deasserted and the I/Os must be tri-stated
prior to the presentation of data to DQs. As a safety precaution,
Page 8 of 33
CY7C1441AV25
CY7C1447AV25
the data lines are tri-stated when a write cycle is detected,
regardless of the state of OE.
Interleaved Burst Address Table
Burst Sequences
(MODE = Floating or VDD)
The CY7C1441AV25/CY7C1447AV25 provides an on-chip
two-bit wraparound burst counter inside the SRAM. The burst
counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of
the MODE input. A LOW on MODE selects a linear burst
sequence. A HIGH on MODE selects an interleaved burst order.
Leaving MODE unconnected causes the device to default to a
interleaved burst sequence.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1:A0
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. When in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE1, CE2, CE3,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
tZZREC
ZZ recovery time
ZZ < 0.2 V
tZZI
ZZ active to sleep current
tRZZI
ZZ Inactive to exit sleep current
Document Number: 001-75380 Rev. *B
Min
Max
Unit
–
100
mA
–
2tCYC
ns
2tCYC
–
ns
This parameter is sampled
–
2tCYC
ns
This parameter is sampled
0
–
ns
Page 9 of 33
CY7C1441AV25
CY7C1447AV25
Truth Table
The truth table for CY7C1441AV25/CY7C1447AV25 follows. [1, 2, 3, 4, 5]
Cycle Description
Address Used CE1 CE2 CE3 ZZ
ADSP
ADSC ADV WRITE OE CLK
DQ
Deselected Cycle, Power Down
None
H
X
X
L
X
L
X
X
X
L–H Tri-State
Deselected Cycle, Power Down
None
L
L
X
L
L
X
X
X
X
L–H Tri-State
Deselected Cycle, Power Down
None
L
X
H
L
L
X
X
X
X
L–H Tri-State
Deselected Cycle, Power Down
None
L
L
X
L
H
L
X
X
X
L–H Tri-State
Deselected Cycle, Power Down
None
X
X
X
L
H
L
X
X
X
L–H Tri-State
Sleep Mode, Power Down
None
X
X
X
H
X
X
X
X
X
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
External
External
External
External
External
Next
Next
Next
L
L
L
L
L
X
X
H
H
H
H
H
H
X
X
X
L
L
L
L
L
X
X
X
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
X
X
X
L
L
L
H
H
H
X
X
X
X
X
L
L
L
X
X
L
H
H
H
H
H
L
H
X
L
H
L
H
L
L–H
Q
L–H Tri-State
L–H
D
L–H
Q
L–H Tri-State
L–H
Q
L–H Tri-State
L–H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L–H Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L–H
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L–H Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
X
Tri-State
Q
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for
the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 001-75380 Rev. *B
Page 10 of 33
CY7C1441AV25
CY7C1447AV25
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1441AV25 follows. [6, 7]
Read
Function (CY7C1441AV25)
GW
H
BWE
H
BWD
X
BWC
X
BWB
X
BWA
X
Read
H
L
H
H
H
H
Write Byte A (DQA, DQPA)
H
L
H
H
H
L
Write Byte B(DQB, DQPB)
H
L
H
H
L
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
H
L
H
H
L
L
Write Byte C (DQC, DQPC)
H
L
H
L
H
H
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
H
L
H
L
H
L
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
L
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB,
DQPA)
H
L
H
L
L
L
Write Byte D (DQD, DQPD)
H
L
L
H
H
H
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
H
L
L
H
H
L
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
L
H
L
H
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
H
L
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
L
L
L
H
H
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC,
DQPA)
H
L
L
L
H
L
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1447AV25 follows. [6, 8]
GW
BWE
BWx
Read
Function (CY7C1447AV25)
H
H
X
Read
H
L
All BW = H
Write Byte x – (DQx and DQPx)
H
L
L
Write All Bytes
H
L
All BW = L
Write All Bytes
L
X
X
Notes
6. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
7. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active.
8. BWx represents any byte write signal BWX.To enable any byte write BWx, a logic LOW signal should be applied at clock rise. Any number of bye writes can be enabled
at the same time for any given write.
Document Number: 001-75380 Rev. *B
Page 11 of 33
CY7C1441AV25
CY7C1447AV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1441AV25/CY7C1447AV25 incorporates a serial
boundary scan test access port (TAP). This part is fully compliant
with 1149.1. The TAP operates using JEDEC-standard
2.5 V/1.8V I/O logic level.
The
CY7C1441AV25/CY7C1447AV25 contains a TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
must be left unconnected. On power up, the device comes up in
a reset state, which does not interfere with the operation of the
device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This ball can be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see Tap Controller State Diagram
on page 14. TDI is internally pulled up and can be unconnected
if the TAP is unused in an application. TDI is connected to the
most significant bit (MSB) of any register.
Test Data-Out (TDO)
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the Tap Controller Block Diagram on
page 15. On power up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to allow fault
isolation of the board level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that is placed between the TDI and
TDO balls. This allows data to be shifted through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state.
It is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions are used to
capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 18.
The TDO output ball is used to serially clock data out from the
registers. The output is active depending on the current state of
the TAP state machine (see Identification Codes on page 18).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Overview
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Eight different instructions are possible with the three bit
instruction register.All combinations are listed in the Identification
Codes on page 18. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Document Number: 001-75380 Rev. *B
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
Page 12 of 33
CY7C1441AV25
CY7C1447AV25
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor specific, 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register on
power up or whenever the TAP controller is given a test logic
reset state.
SAMPLE Z
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High Z state until the next command is given
during the “Update IR” state.
EXTEST
SAMPLE/PRELOAD
EXTEST OUTPUT BUS TRI-STATE
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output may undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the Shift-DR controller state.
The boundary scan register has a special bit located at bit #138
(for 209-ball FBGA package). When this scan cell, called the
“extest output bus tri-state”, is latched into the preload register
during the Update-DR state in the TAP controller, it directly
controls the state of the output (Q-bus) pins when the EXTEST
is entered as the current instruction. When HIGH, it enables the
output buffers to drive the output bus. When LOW, this bit places
the output bus into a High Z condition.
This bit can be set by entering the SAMPLE/PRELOAD, or
EXTEST command and then shifting the desired bit into that cell
during the Shift-DR state. During Update-DR, the value loaded
into that shift register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up and also when the TAP
controller is in the Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
When the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Document Number: 001-75380 Rev. *B
Page 13 of 33
CY7C1441AV25
CY7C1447AV25
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
UPDATE-IR
1
0
1
EXIT1-DR
0
1
0
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 001-75380 Rev. *B
Page 14 of 33
CY7C1441AV25
CY7C1447AV25
TAP Controller Block Diagram
TAP Timing
Figure 3. TAP Timing
1
2
Test Clock
(TCK)
3
t
t TH
t TMSS
t TMSH
t TDIS
t TDIH
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
Document Number: 001-75380 Rev. *B
UNDEFINED
Page 15 of 33
CY7C1441AV25
CY7C1447AV25
TAP AC Switching Characteristics
Over the Operating Range
Parameter [9, 10]
Clock
tTCYC
tTF
tTH
tTL
Output Times
tTDOV
tTDOX
Setup Times
tTMSS
tTDIS
tCS
Hold Times
tTMSH
tTDIH
tCH
Parameter
Min
Max
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
–
20
20
–
20
–
–
ns
MHz
ns
ns
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
–
0
10
–
ns
ns
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture SetUp to TCK Rise
5
5
5
–
–
–
ns
ns
ns
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
–
–
–
ns
ns
ns
Notes
9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document Number: 001-75380 Rev. *B
Page 16 of 33
CY7C1441AV25
CY7C1447AV25
2.5 V TAP AC Test Conditions
1.8 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 2.5 V
Input pulse levels ................................ 0.2 V to VDDQ – 0.2 V
Input rise and fall time ....................................................1 ns
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
Input timing reference levels ......................................... 0.9 V
Output reference levels .............................................. 1.25 V
Output reference levels ................................................ 0.9 V
Test load termination supply voltage .......................... 1.25 V
Test load termination supply voltage ............................ 0.9 V
2.5 V TAP AC Output Load Equivalent
1.8 V TAP AC Output Load Equivalent
1.25V
0.9V
50 Ω
50Ω
TDO
TDO
Z O = 50 Ω
Z O = 50 Ω
20p F
20p F
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 2.5 V ± 0.125 V unless otherwise noted)
Parameter [11]
Description
Description
Conditions
Min
Max
Unit
VOH1
Output HIGH Voltage
IOH = –1.0 mA
VDDQ = 2.5 V
2.0
–
V
VOH2
Output HIGH Voltage
IOH = –100 µA
VDDQ = 2.5 V
2.1
–
V
VDDQ = 1.8 V
1.6
–
V
VOL1
Output LOW Voltage
IOL = 1.0 mA
VDDQ = 2.5 V
–
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
VDDQ = 2.5 V
–
0.2
V
VDDQ = 1.8 V
–
0.2
V
VIH
VIL
IX
Input HIGH Voltage
Input LOW Voltage
Input Load Current
GND < VIN < VDDQ
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 1.8 V
1.26
VDD + 0.3
V
VDDQ = 2.5 V
–0.3
0.7
V
VDDQ = 1.8 V
–0.3
0.36
V
–5
5
µA
Note
11. All voltages referenced to VSS (GND).
Document Number: 001-75380 Rev. *B
Page 17 of 33
CY7C1441AV25
CY7C1447AV25
Identification Register Definitions
Bit Configuration
Bit Configuration
CY7C1441AV25 (1 M × 36) CY7C1447AV25 (512 K × 72)
Instruction Field
Revision Number (31:29)
000
Device Depth (28:24)
000
Description
Describes the version number.
01011
01011
Reserved for internal use.
Architecture and Memory Type
(23:18)
000001
000001
Defines memory type and
architecture.
Bus Width and Density (17:12)
100111
110111
Defines width and density.
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
1
1
ID Register Presence Indicator (0)
Allows unique identification of
SRAM vendor.
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size (× 36)
Bit Size (× 72)
Instruction Bypass
3
3
Bypass
1
1
ID
32
32
Boundary Scan Order (165-ball FBGA package)
89
–
Boundary Scan Order (209-ball FBGA package)
–
138
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 001-75380 Rev. *B
Page 18 of 33
CY7C1441AV25
CY7C1447AV25
Boundary Scan Order
165-ball FBGA [12, 13]
CY7C1441AV25 (1 M × 36)
Bit #
Ball ID
1
N6
2
N7
3
N10
4
P11
5
P8
6
R8
7
R9
8
P9
9
P10
10
R10
11
R11
12
H11
13
N11
14
M11
15
L11
16
K11
17
J11
18
M10
19
L10
20
K10
21
J10
22
H9
23
H10
24
G11
25
F11
Bit #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Ball ID
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
A9
B9
C10
A8
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
Bit #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Ball ID
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
G1
D2
E2
F2
G2
H1
H3
J1
K1
L1
M1
J2
K2
L2
M2
Bit #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
N1
N2
P1
R1
R2
P3
R3
P2
R4
P4
N5
P6
R6
Internal
Notes
12. Balls which are NC (No Connect) are preset LOW.
13. Bit# 89 is preset HIGH.
Document Number: 001-75380 Rev. *B
Page 19 of 33
CY7C1441AV25
CY7C1447AV25
Boundary Scan Order
209-ball FBGA [14, 15]
CY7C1447AV25 (512 K × 72)
Bit #
Ball ID
1
W6
2
V6
3
U6
4
W7
5
V7
6
U7
7
T7
8
V8
9
U8
10
T8
11
V9
12
U9
13
P6
14
W11
15
W10
16
V11
17
V10
18
U11
19
U10
20
T11
21
T10
22
R11
23
R10
24
P11
25
P10
26
N11
27
N10
28
M11
29
M10
30
L11
31
L10
32
K11
33
M6
34
L6
35
J6
Bit #
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Ball ID
F6
K8
K9
K10
J11
J10
H11
H10
G11
G10
F11
F10
E10
E11
D11
D10
C11
C10
B11
B10
A11
A10
C9
B9
A9
D7
C8
B8
A8
D8
C7
B7
A7
D6
G6
Bit #
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
Ball ID
H6
C6
B6
A6
A5
B5
C5
D5
D4
C4
A4
B4
C3
B3
A3
A2
A1
B2
B1
C2
C1
D2
D1
E1
E2
F2
F1
G1
G2
H2
H1
J2
J1
K1
N6
Bit #
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
Ball ID
K3
K4
K6
K2
L2
L1
M2
M1
N2
N1
P2
P1
R2
R1
T2
T1
U2
U1
V2
V1
W2
W1
T6
U3
V3
T4
T5
U4
V4
5W
5V
5U
Internal
Notes
14. Balls which are NC (No Connect) are preset LOW.
15. Bit# 138 is preset HIGH.
Document Number: 001-75380 Rev. *B
Page 20 of 33
CY7C1441AV25
CY7C1447AV25
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage on VDD Relative to GND .....–0.3 V to +3.6 V
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch Up Current ................................................... > 200 mA
Operating Range
Ambient
Temperature
VDD
VDDQ
–40 °C to +85 °C
2.5 V+ 5%
1.7 V to VDD
Range
Industrial
Electrical Characteristics
Over the Operating Range
Parameter [16, 17]
Description
Power Supply Voltage
VDD
I/O Supply Voltage
VDDQ
VOH
VOL
VIH
VIL
IX
IOZ
IDD
ISB1
ISB2
ISB3
ISB4
Test Conditions
for 2.5 V I/O
for 1.8 V I/O
Output HIGH Voltage
for 2.5 V I/O, IOH = –1.0 mA
for 1.8 V I/O, IOH = –100 A
Output LOW Voltage
for 2.5 V I/O, IOL = 1.0 mA
for 1.8 V I/O, IOL= 100 A
Input HIGH Voltage [16]
for 2.5 V I/O
for 1.8 V I/O
Input LOW Voltage [16]
for 2.5 V I/O
for 1.8 V I/O
Input Leakage Current except ZZ GND  VI  VDDQ
and MODE
Input Current of MODE
Input = VSS
Input = VDD
Input Current of ZZ
Input = VSS
Input = VDD
Output Leakage Current
GND  VI  VDDQ, Output Disabled
VDD Operating Supply Current
VDD = Max, IOUT = 0 mA,
7.5 ns cycle,
f = fMAX = 1/tCYC
133 MHz
7.5 ns cycle,
Automatic CE Power Down
Max VDD, Device Deselected,
133 MHz
Current – TTL Inputs
VIN  VIH or VIN  VIL, f = fMAX,
Inputs Switching
7.5 ns cycle,
Automatic CE Power Down
Max VDD, Device Deselected,
Current – CMOS Inputs
VIN  VDD – 0.3 V or VIN  0.3 V, 133 MHz
f = 0, Inputs Static
7.5 ns cycle,
Automatic CE Power Down
Max VDD, Device Deselected,
Current – CMOS Inputs
VIN  VDDQ – 0.3 V or VIN  0.3 V, 133 MHz
f = fMAX, Inputs Switching
7.5 ns cycle,
Automatic CE Power Down
Max VDD, Device Deselected,
Current – TTL Inputs
VIN  VDD – 0.3 V or VIN  0.3 V, 133 MHz
f = 0, Inputs Static
Min
2.375
2.375
1.7
2.0
1.6
–
–
1.7
1.26
–0.3
–0.3
–5
Max
Unit
2.625
V
2.625
V
1.9
V
–
V
–
V
0.4
V
0.2
V
VDD + 0.3 V
V
VDD + 0.3 V
V
0.7
V
0.36
V
5
A
–30
–
–5
–
–5
–
–
5
–
30
5
270
A
A
A
A
A
mA
–
150
mA
–
120
mA
–
150
mA
–
135
mA
Notes
16. Overshoot: VIH(AC) < VDD +1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
17. TPower-up: Assumes a linear ramp from V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 001-75380 Rev. *B
Page 21 of 33
CY7C1441AV25
CY7C1447AV25
Capacitance
Parameter [18]
Description
165-ball FBGA 209-ball FBGA Unit
Max
Max
Test Conditions
TA = 25 C, f = 1 MHz, VDD = 3.3 V,
VDDQ = 2.5 V
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/Output capacitance
7
5
pF
7
5
pF
6
7
pF
Thermal Resistance
Parameter [18]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
165-ball FBGA 209-ball FBGA Unit
Package
Package
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
20.8
25.31
°C/W
3.2
4.48
°C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
3.3 V I/O Test Load
3.3V
OUTPUT
R = 317
Z0 = 50
VT = 1.5V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
2.5 V I/O Test Load
2.5V
OUTPUT
GND
R = 351
VT = 1.25V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
 1 ns
 1 ns
(b)
(c)
R = 1667
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
Z0 = 50
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
GND
R = 1538
(b)
10%
90%
10%
90%
 1 ns
 1 ns
(c)
Note
18. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-75380 Rev. *B
Page 22 of 33
CY7C1441AV25
CY7C1447AV25
Switching Characteristics
Over the Operating Range
Parameter [19, 20]
tPOWER
Description
VDD(typical) to the first access [21]
-133
Unit
Min
Max
1
–
ms
Clock
tCYC
Clock cycle time
7.5
–
ns
tCH
Clock HIGH
2.5
–
ns
tCL
Clock LOW
2.5
–
ns
Output Times
tCDV
Data output valid after CLK rise
–
6.5
ns
tDOH
Data output hold after CLK rise
2.5
–
ns
2.5
–
ns
–
3.8
ns
tCLZ
Clock to low Z
[22, 23, 24]
[22, 23, 24]
tCHZ
Clock to high Z
tOEV
OE LOW to output valid
–
3.0
ns
tOELZ
OE LOW to output low Z [22, 23, 24]
0
–
ns
–
3.0
ns
tOEHZ
OE HIGH to output high Z
[22, 23, 24]
Setup Times
tAS
Address setup before CLK rise
1.5
–
ns
tADS
ADSP, ADSC setup before CLK rise
1.5
–
ns
tADVS
ADV setup before CLK rise
1.5
–
ns
tWES
GW, BWE, BWX setup before CLK rise
1.5
–
ns
tDS
Data input setup before CLK rise
1.5
–
ns
tCES
Chip enable setup
1.5
–
ns
tAH
Address hold after CLK rise
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.5
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.5
–
ns
tADVH
ADV hold after CLK rise
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
ns
Hold Times
Notes
19. Timing reference level is 1.25 V when VDDQ = 2.5 V and 0.9 V when VDDQ = 1.8 V.
20. Test conditions shown in (a) of Figure 4 on page 22 unless otherwise noted.
21. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can
be initiated.
22. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 22. Transition is measured ±200 mV from steady-state voltage.
23. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
24. This parameter is sampled and not 100% tested.
Document Number: 001-75380 Rev. *B
Page 23 of 33
CY7C1441AV25
CY7C1447AV25
Timing Diagrams
Figure 5. Read Cycle Timing [25]
tCYC
CLK
t
t ADS
CH
t CL
tADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t
GW, BWE,BW
WES
t
WEH
X
t CES
Deselect Cycle
t CEH
CE
t
ADVS
t
ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t CDV
t OELZ
t CHZ
t DOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
25. In this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 001-75380 Rev. *B
Page 24 of 33
CY7C1441AV25
CY7C1447AV25
Timing Diagrams (continued)
Figure 6. Write Cycle Timing [26, 27]
t CYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW
X
t
WES
t
WEH
GW
t CES
tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
26. In this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
27. Full width write is initiated by either GW LOW; or by GW HIGH, BWE LOW, and BWX LOW.
Document Number: 001-75380 Rev. *B
Page 25 of 33
CY7C1441AV25
CY7C1447AV25
Timing Diagrams (continued)
Figure 7. Read/Write Cycle Timing [28, 29, 30]
tCYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
ADSC
t AS
ADDRESS
A1
tAH
A2
A3
A4
t
WES
t
A5
A6
WEH
BWE, BW X
t CES
tCEH
CE
ADV
OE
t DS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
t OELZ
D(A3)
D(A5)
Q(A4)
Q(A2)
Back-to-Back READs
D(A6)
t CDV
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
28. In this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
29. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
30. GW is HIGH.
Document Number: 001-75380 Rev. *B
Page 26 of 33
CY7C1441AV25
CY7C1447AV25
Timing Diagrams (continued)
Figure 8. ZZ Mode Timing [31, 32]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
31. Device must be deselected when entering ZZ mode. See Truth Table on page 10 for all possible signal conditions to deselect the device.
32. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-75380 Rev. *B
Page 27 of 33
CY7C1441AV25
CY7C1447AV25
Ordering Information
Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
133
Ordering Code
Package
Diagram
Part and Package Type
CY7C1441AV25-133BZXI
51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
CY7C1447AV25-133BGI
51-85167 209-ball FBGA (14 × 22 × 1.76 mm)
Operating
Range
lndustrial
Ordering Code Definitions
CY
7
C 144X A V25 - 133 XX
X
I
Temperature Grade:
I = Industrial
Pb-free
Package Type: XX = BZ or BG
BZ = 165-ball FBGA; BG = 209-ball FBGA
Speed Grade: 133 MHz
V25 = 2.5 V
Die Revision
Part Identifier: 144X = 1441 or 1447
1441 = FT, 1 M × 36 (36 Mb); 1447 = FT, 512 kb × 72 (36 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-75380 Rev. *B
Page 28 of 33
CY7C1441AV25
CY7C1447AV25
Package Diagrams
Figure 9. 165-ball FBGA (15 × 17 × 1.40 mm) (0.45 Ball Diameter) Package Outline, 51-85165
51-85165 *D
Document Number: 001-75380 Rev. *B
Page 29 of 33
CY7C1441AV25
CY7C1447AV25
Package Diagrams (continued)
Figure 10. 209-ball FBGA (14 × 22 × 1.76 mm) BB209A Package Outline, 51-85167
51-85167 *C
Document Number: 001-75380 Rev. *B
Page 30 of 33
CY7C1441AV25
CY7C1447AV25
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
chip enable
CMOS
complementary metal oxide semiconductor
°C
degree Celsius
EIA
electronic industries alliance
MHz
megahertz
FBGA
fine-pitch ball grid array
µA
microampere
I/O
input/output
mA
milliampere
JEDEC
joint electron devices engineering council
mm
millimeter
JTAG
joint test action group
ms
millisecond
OE
output enable
mV
millivolt
SRAM
static random access memory
ns
nanosecond
TAP
test access port

ohm
TCK
test clock
%
percent
TDI
test data-in
pF
picofarad
TDO
test data-out
V
volt
TMS
test mode select
W
watt
TTL
transistor-transistor logic
Document Number: 001-75380 Rev. *B
Symbol
Unit of Measure
Page 31 of 33
CY7C1441AV25
CY7C1447AV25
Document History Page
Document Title: CY7C1441AV25/CY7C1447AV25, 36-Mbit (1 M × 36/512 K × 72) Flow-Through SRAM
Document Number: 001-75380
Rev.
ECN No.
Issue Date
Orig. of
Change
**
3534404
02/28/2012
GOPA
New data sheet.
*A
3606230
05/02/2012
PRIT /
GOPA
Updated Features (Included CY7C1441AV25 related information).
Updated Functional Description (Included CY7C1441AV25 related
information).
Included Logic Block Diagram – CY7C1441AV25.
Updated Pin Configurations (Included CY7C1441AV25 related information,
included 165-ball FBGA package related information).
Updated Functional Overview (Included CY7C1441AV25 related information).
Updated Truth Table (Included CY7C1441AV25 related information).
Added Partial Truth Table for Read/Write (Corresponding to CY7C1441AV25).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Included
CY7C1441AV25 related information).
Updated Identification Register Definitions (Included CY7C1441AV25 related
information).
Updated Scan Register Sizes (Included 165-ball FBGA package related
information, added Bit Size (× 36) column).
Added Boundary Scan Order (Corresponding to CY7C1441AV25).
Updated Capacitance (Included 165-ball FBGA package related information).
Updated Thermal Resistance (Included 165-ball FBGA package related
information).
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams (Included 165-ball FBGA package related
information (spec 51-85165)).
*B
3925180
03/07/2013
PRIT
Updated Package Diagrams:
spec 51-85167 – Changed revision from *B to *C.
Document Number: 001-75380 Rev. *B
Description of Change
Page 32 of 33
CY7C1441AV25
CY7C1447AV25
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2012-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-75380 Rev. *B
Revised March 7, 2013
Page 33 of 33
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All products and company names mentioned in this document
may be the trademarks of their respective holders.