CYPRESS CY7C1444AV33

CY7C1444AV33
CY7C1445AV33
36-Mbit (1 M × 36/2 M × 18)
Pipelined DCD Sync SRAM
36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM
Features
Functional Description[1]
■
Supports bus operation up to 250 MHz
■
Available speed grades are 250, 200, and 167 MHz
■
Registered inputs and outputs for pipelined operation
■
Optimal for performance (double-cycle deselect)
■
Depth expansion without wait state
■
3.3 V core power supply
■
2.5 V/3.3 V I/O power supply
■
Fast clock-to-output times
❐ 2.6 ns (for 250-MHz device)
■
Provide high-performance 3-1-1-1 access rate
■
User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed writes
■
Asynchronous output enable
■
CY7C1444AV33, CY7C1445AV33 available in
JEDEC-standard Pb-free 100-pin TQFP package and Pb-free
and non Pb-free 165-ball FBGA package
■
IEEE 1149.1 JTAG-compatible boundary scan
■
“ZZ” sleep mode option
The CY7C1444AV33/CY7C1445AV33 SRAM integrates
1 M × 36/2 M × 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable (CE1), depth-expansion chip
enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and
ADV), write enables (BWX, and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle. This part supports byte write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as controlled
by the byte write control inputs. GW active LOW causes all bytes
to be written. This device incorporates an additional pipelined
enable register which delays turning off the output buffers an
additional cycle when a deselect is executed. This feature allows
depth expansion without penalizing system performance.
The CY7C1444AV33/CY7C1445AV33 operates from a +3.3 V
core power supply while all outputs operate with a +3.3 V or a
+2.5 V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 38-05352 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 29, 2010
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CY7C1444AV33
CY7C1445AV33
Logic Block Diagram – CY7C1444AV33 (1 M × 36)
ADDRESS
REGISTER
A0,A1,A
2 A[1:0]
MODE
ADV
CLK
BURST
Q1
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
BWD
DQD,DQPD
BYTE
WRITE REGISTER
DQD,DQPD
BYTE
WRITE DRIVER
BWC
DQc,DQPC
BYTE
WRITE REGISTER
DQc,DQPC
BYTE
WRITE DRIVER
DQB,DQPB
BYTE
WRITE REGISTER
DQB,DQPB
BYTE
WRITE DRIVER
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs
DQPA
DQPB
DQPC
DQPD
E
DQA,DQPA
BYTE
WRITE DRIVER
DQA,DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
MEMORY
ARRAY
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
Logic Block Diagram – CY7C1445AV33 (2 M × 18)
A0, A1, A
ADDRESS
REGISTER
2
MODE
ADV
CLK
A[1:0]
Q1
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
BWB
BWA
BWE
GW
CE1
CE2
CE3
DQB , DQPB
BYTE
WRITE DRIVER
DQB, DQPB
BYTE
WRITE REGISTER
DQA, DQPA
BYTE
WRITE DRIVER
DQA , DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs,
DQPA
DQPB
E
INPUT
REGISTERS
OE
ZZ
Document Number: 38-05352 Rev. *G
SLEEP
CONTROL
Page 2 of 28
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CY7C1444AV33
CY7C1445AV33
Contents
Selection Guide ................................................................ 4
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Single Write Accesses Initiated by ADSP ................... 7
Single Write Accesses Initiated by ADSC ................... 7
Burst Sequences ......................................................... 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table
(MODE = Floating or VDD) ................................................ 8
Linear Burst Address Table (MODE = GND) .................. 8
ZZ Mode Electrical Characteristics ................................. 8
Truth Table ........................................................................ 9
Partial Truth Table for Read/Write ................................ 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
TAP Controller State Diagram ....................................... 11
Test Access Port (TAP) ............................................. 11
TAP Controller Block Diagram ...................................... 11
PERFORMING A TAP RESET .................................. 11
TAP REGISTERS ...................................................... 11
TAP Instruction Set ................................................... 12
TAP Timing ...................................................................... 13
TAP AC Switching Characteristics ............................... 13
3.3 V TAP AC Test Conditions ....................................... 14
3.3 V TAP AC Output Load Equivalent ......................... 14
2.5 V TAP AC Test Conditions ....................................... 14
2.5 V TAP AC Output Load Equivalent ........................ 14
Document Number: 38-05352 Rev. *G
TAP DC Electrical Characteristics
And Operating Conditions ............................................. 14
Identification Register Definitions ................................ 15
Scan Register Sizes ....................................................... 15
Identification Codes ....................................................... 15
165-ball FBGA Boundary Scan Order ........................... 16
Maximum Ratings ........................................................... 17
Operating Range ............................................................. 17
Electrical Characteristics ............................................... 17
Capacitance .................................................................... 18
Thermal Resistance ........................................................ 18
AC Test Loads and Waveforms ..................................... 18
Switching Characteristics .............................................. 19
Switching Waveforms .................................................... 20
Read Cycle Timing .................................................... 20
Write Cycle Timing .................................................... 21
Read/Write Cycle Timing ........................................... 22
ZZ Mode Timing ........................................................ 23
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagram .......................................................... 25
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 28
Worldwide Sales and Design Support ....................... 28
Products .................................................................... 28
PSoC Solutions ......................................................... 28
Page 3 of 28
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CY7C1444AV33
CY7C1445AV33
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum access time
2.6
3.2
3.4
ns
Maximum operating current
475
425
375
mA
Maximum CMOS standby current
120
120
120
mA
Pin Configurations
NC
NC
NC
CY7C1445AV33
(2 M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document Number: 38-05352 Rev. *G
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1444AV33
(1 M × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
A
A
A
A
A
A
A
A
A
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-pin TQFP Pinout
Page 4 of 28
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CY7C1444AV33
CY7C1445AV33
Pin Configurations (continued)
165-ball FBGA (15 × 17 × 1.4 mm) Pinout
CY7C1444AV33 (1 M × 36)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
A
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
R
NC/144M
A
CE2
BWD
BWA
CLK
NC/576M
VDDQ
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VSS
VDD
OE
VSS
VDD
A
NC
DQC
GW
VSS
VSS
ADSP
DQPC
DQC
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
DQB
DQB
DQC
NC
DQD
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
CY7C1445AV33 (2 M × 18)
1
2
3
4
5
6
7
8
9
10
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
A
NC/144M
A
CE1
CE2
BWB
NC
CE3
BWA
CLK
BWE
GW
ADSC
OE
ADV
ADSP
A
NC
NC
NC
NC
DQB
VDDQ
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
NC/1G
NC
DQPA
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
NC
NC
DQB
DQB
VDDQ
VDDQ
NC
VDDQ
VDD
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
‘VSS
VSS
DQB
NC
NC
NC
NC
DQA
DQA
DQA
ZZ
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
R
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
Document Number: 38-05352 Rev. *G
A
11
A
NC/576M
Page 5 of 28
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CY7C1444AV33
CY7C1445AV33
Pin Definitions
Name
I/O
Description
A0, A1, A
Inputsynchronous
Address inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:
A0 are fed to the two-bit counter..
BWA, BWB
BWC, BWD
Inputsynchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
GW
Inputsynchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (all bytes are written, regardless of the values on BWX and BWE).
BWE
Inputsynchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
CLK
Inputclock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
CE1
Inputsynchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is
sampled only when a new external address is loaded.
CE2
Inputsynchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external
address is loaded.
CE3
Inputsynchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device.Not connected for BGA. Where referenced,
CE3 is assumed active throughout this document for BGA. CE3 is sampled only when a new
external address is loaded.
OE
Inputasynchronous
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
ADV
Inputsynchronous
Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted,
it automatically increments the address in a burst cycle.
ADSP
Inputsynchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1:
A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Inputsynchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1:
A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
ZZ
Inputasynchronous
ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW
or left floating. ZZ pin has an internal pull-down.
DQs, DQPs
I/Osynchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory
location specified by the addresses presented during the previous clock rise of the read
cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins
behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.
VDD
Power supply
Power supply inputs to the core of the device.
VSS
Ground
VSSQ
VDDQ
MODE
I/O ground
Ground for the core of the device.
Ground for the I/O circuitry.
I/O power supply Power supply for the I/O circuitry.
Inputstatic
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or
left floating selects interleaved burst sequence. This is a strap pin and should remain static
during device operation. Mode pin has an internal pull-up.
Document Number: 38-05352 Rev. *G
Page 6 of 28
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CY7C1444AV33
CY7C1445AV33
Pin Definitions (continued)
Name
I/O
Description
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature
synchronous
is not being utilized, this pin should be disconnected. This pin is not available on TQFP packages.
TDI
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
synchronous
is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TMS
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
synchronous
is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TCK
JTAGclock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to VSS. This pin is not available on TQFP packages.
NC
–
No Connects. Not internally connected to the die.
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
–
No Connects. Not internally connected to the die. 72M, 144M, 288M, 576M and 1G are
address expansion pins are not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock.
The CY7C1444AV33/CY7C1445AV33 supports secondary
cache in systems utilizing either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium and
i486 processors. The linear burst sequence is suited for
processors that utilize a linear burst sequence. The burst order
is user selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the processor
address strobe (ADSP) or the controller address strobe (ADSC).
Address advancement through the burst sequence is controlled
by the ADV input. A two-bit on-chip wraparound burst counter
captures the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Synchronous chip selects CE1, CE2, CE3 and an asynchronous
output enable (OE) provide for easy bank selection and output
tri-state control. ADSP is ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is
HIGH. The address presented to the address inputs is stored into
the address advancement logic and the address register while
being presented to the memory core. The corresponding data is
allowed to propagate to the input of the output registers. At the
rising edge of the next clock the data is allowed to propagate
through the output register and onto the data bus within tCO if OE
is active LOW. The only exception occurs when the SRAM is
Document Number: 38-05352 Rev. *G
emerging from a deselected state to a selected state, its outputs
are always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single read cycles are supported.
The CY7C1444AV33/CY7C1445AV33 is a double-cycle
deselect part. Once the SRAM is deselected at clock rise by the
chip select and either ADSP or ADSC signals, its output will
tri-state immediately after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip
select is asserted active. The address presented is loaded into
the address register and the address advancement logic while
being delivered to the memory core. The write signals (GW,
BWE, and BWX) and ADV inputs are ignored during this first
cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the
corresponding address location in the memory core. If GW is
HIGH, then the write operation is controlled by BWE and BWX
signals. The CY7C1444AV33/CY7C1445AV33 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the byte write enable input (BWE) with the
selected byte write input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Because the CY7C1444AV33/CY7C1445AV33 is a common I/O
device, the output enable (OE) must be deasserted HIGH before
presenting data to the DQ inputs. Doing so will tri-state the output
drivers. As a safety precaution, DQ are automatically tri-stated
whenever a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
Page 7 of 28
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CY7C1444AV33
CY7C1445AV33
HIGH, (3) chip select is asserted active, and (4) the appropriate
combination of the write inputs (GW, BWE, and BWX) are
asserted active to conduct a write to the desired byte(s). ADSC
triggered write accesses require a single clock cycle to complete.
The address presented is loaded into the address register and
the address advancement logic while being delivered to the
memory core. The ADV input is ignored during this cycle. If a
global write is conducted, the data presented to the DQX is
written into the corresponding address location in the memory
core. If a byte write is conducted, only the selected bytes are
written. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Because the CY7C1444AV33/CY7C1445AV33 is a common I/O
device, the output enable (OE) must be deasserted HIGH before
presenting data to the DQX inputs. Doing so will tri-state the
output drivers. As a safety precaution, DQX are automatically
tri-stated whenever a write cycle is detected, regardless of the
state of OE.
Burst Sequences
The CY7C1444AV33/CY7C1445AV33 provides a two-bit
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input. Both read
and write burst operations are supported.
Asserting ADV LOW at clock rise will automatically increment the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CEs,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
00
11
10
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
10
11
00
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ inactive to exit sleep current
Document Number: 38-05352 Rev. *G
Test Conditions
ZZ > VDD– 0.2 V
ZZ > VDD – 0.2 V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
Min
–
–
2tCYC
–
0
Max
100
2tCYC
–
2tCYC
–
Unit
mA
ns
ns
ns
ns
Page 8 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Truth Table[2, 3, 4, 5, 6, 7]
Add. Used
CE1
CE2
CE3
ZZ
ADSP
ADSC
ADV
Deselect cycle, power-down
Operation
None
H
X
X
L
X
L
X
X
X
L-H
Tri-state
Deselect cycle, power-down
None
L
L
X
L
L
X
X
X
X
L-H
Tri-state
Deselect cycle, power-down
None
L
X
H
L
L
X
X
X
X
L-H
Tri-state
Deselect cycle, power-down
None
L
L
X
L
H
L
X
X
X
L-H
Tri-state
Deselect cycle, power-down
None
L
X
H
L
H
L
X
X
X
L-H
Tri-state
None
X
X
X
H
X
X
X
X
X
X
Tri-state
External
L
H
L
L
L
X
X
X
L
L-H
Q
Sleep mode, power-down
Read cycle, begin burst
WRITE OE CLK
DQ
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
H
L-H
Tri-state
Write cycle, begin burst
External
L
H
L
L
H
L
X
L
X
L-H
D
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
H
L-H
Tri-state
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
H
L-H
Tri-state
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
H
L-H
Tri-state
Write cycle, continue burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write cycle, continue burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
H
L-H
Tri-state
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
H
L-H
Tri-state
Write cycle, suspend burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write cycle, suspend burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05352 Rev. *G
Page 9 of 28
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CY7C1444AV33
CY7C1445AV33
Partial Truth Table for Read/Write[8, 9]
GW
BWE
BWD
BWC
BWB
BWA
Read
Function (CY7C1444AV33)
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write byte A – (DQA and DQPA)
H
L
H
H
H
L
Write byte B – (DQB and DQPB)
H
L
H
H
L
H
Write bytes B, A
H
L
H
H
L
L
Write byte C – (DQC and DQPC)
H
L
H
L
H
H
Write bytes C, A
H
L
H
L
H
L
Write bytes C, B
H
L
H
L
L
H
Write bytes C, B, A
H
L
H
L
L
L
Write byte D – (DQD and DQPD)
H
L
L
H
H
H
Write bytes D, A
H
L
L
H
H
L
Write bytes D, B
H
L
L
H
L
H
Write bytes D, B, A
H
L
L
H
L
L
Write bytes D, C
H
L
L
L
H
H
Write bytes D, C, A
H
L
L
L
H
L
Write bytes D, C, B
H
L
L
L
L
H
Write all bytes
H
L
L
L
L
L
Write all bytes
L
X
X
X
X
X
Truth Table for Read/Write[8, 9]
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write byte A – (DQA and DQPA)
H
L
H
L
Write byte B – (DQB and DQPB)
H
L
L
H
Write all bytes
H
L
L
L
Write all bytes
L
X
X
X
Function (CY7C1445AV33)
Notes
8. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
9. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active.
Document Number: 38-05352 Rev. *G
Page 10 of 28
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CY7C1444AV33
CY7C1445AV33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1444AV33/CY7C1445AV33 incorporates a serial
boundary scan test access port (TAP). This part is fully compliant
with the 1149.1 IEEE Standard 1149.1. The TAP operates using
JEDEC-standard 3.3 V or 2.5 V I/O logic levels.
The CY7C1444AV33/CY7C1445AV33 contains a TAP controller,
instruction register, boundary scan register, bypass register, and
ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in a
reset state which will not interfere with the operation of the
device.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register. (See TAP Controller Block Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See TAP Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
TAP Controller State Diagram
1
2 1 0
TEST-LOGIC
RESET
TDI
Selection
Circuitry
0
0
RUN-TEST/
IDLE
Instruction Register
31 30 29 . . . 2 1 0
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
1
0
SHIFT-IR
1
0
1
EXIT1-DR
1
TCK
EXIT1-IR
0
1
TMS
TAP CONTROLLER
0
PAUSE-DR
0
PAUSE-IR
1
0
Performing a TAP Reset
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
x . . . . . 2 1 0
Boundary Scan Register
0
SHIFT-DR
0
Identification Register
CAPTURE-IR
0
TDO
1
0
CAPTURE-DR
Selection
Circuitry
0
UPDATE-IR
1
0
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
TAP Registers
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Document Number: 38-05352 Rev. *G
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
Page 11 of 28
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CY7C1444AV33
CY7C1445AV33
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions
table.
TAP Instruction Set
Overview
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a high Z state until the next command is given
during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there
is no guarantee as to the value that will be captured. Repeatable
results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK captured in the boundary scan
register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data can be shifted in.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
IDCODE
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
Document Number: 38-05352 Rev. *G
BYPASS
EXTEST
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit# 89
(for 165-ball FBGA packages).When this scan cell, called the
Page 12 of 28
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CY7C1444AV33
CY7C1445AV33
“extest output bus tri-state”, is latched into the preload register
during the “Update-DR” state in the TAP controller, it will directly
control the state of the output (Q-bus) pins, when the EXTEST is
entered as the current instruction. When HIGH, it will enable the
output buffers to drive the output bus. When LOW, this bit will
place the output bus into a high Z condition.
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is preset
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t TH
t TMSS
t TMSH
t TDIS
t TDIH
t
TL
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range[10,11]
Parameter
Description
Min
Max
Unit
50
–
ns
Clock
tTCYC
TCK clock cycle time
tTF
TCK clock frequency
–
20
MHz
tTH
TCK clock HIGH time
20
–
ns
tTL
TCK clock LOW time
20
–
ns
Output Times
tTDOV
TCK clock LOW to TDO valid
–
10
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
Set-up Times
tTMSS
TMS set-up to TCK clock rise
5
–
ns
tTDIS
TDI set-up to TCK clock rise
5
–
ns
tCS
Capture set-up to TCK rise
5
–
ns
tTMSH
TMS hold after TCK clock rise
5
–
ns
tTDIH
TDI hold after clock rise
5
–
ns
tCH
Capture hold after clock rise
5
–
ns
Hold Times
Notes
10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document Number: 38-05352 Rev. *G
Page 13 of 28
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CY7C1444AV33
CY7C1445AV33
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels................................................VSS to 3.3 V
Input pulse levels................................................ VSS to 2.5 V
Input rise and fall times....................................................1 ns
Input rise and fall time .....................................................1 ns
Input timing reference levels.......................................... 1.5 V
Input timing reference levels........................................ 1.25 V
Output reference levels ................................................. 1.5 V
Output reference levels ............................................... 1.25 V
Test load termination supply voltage ............................. 1.5 V
Test load termination supply voltage ............................ 1.25V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50
50
TDO
TDO
Z O= 50
Z O= 50
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 V to 3.6 V unless otherwise noted)[12]
Parameter
Description
Test Conditions
Min
Max
Unit
2.4
–
V
VOH1
Output HIGH voltage
IOH = –1.0 mA, VDDQ = 2.5 V
2.0
–
V
VOH2
Output HIGH voltage
IOH = –100 µA
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
VOL1
Output LOW voltage
IOL = 8.0 mA, VDDQ = 3.3 V
–
0.4
V
IOL = 1.0 mA, VDDQ = 2.5 V
–
0.4
V
VOL2
Output LOW voltage
IOL = 100 µA
–
0.2
V
VIH
Input HIGH voltage
VDDQ = 3.3 V
VIL
Input LOW voltage
IX
Input load current
GND < VIN < VDDQ
IOH = –4.0 mA, VDDQ = 3.3 V
VDDQ = 3.3 V
VDDQ = 2.5 V
–
0.2
V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 3.3 V
–0.5
0.7
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
Note
12. All voltages referenced to VSS (GND).
Document Number: 38-05352 Rev. *G
Page 14 of 28
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CY7C1444AV33
CY7C1445AV33
Identification Register Definitions
Instruction Field
CY7C1444AV33
CY7C1445AV33
Description
Revision number (31:29)
000
000
Device depth (28:24)[13]
01011
01011
Architecture/memory type (23:18)
000110
000110
Defines memory type and architecture
Bus width/density(17:12)
100111
010111
Defines width and density
00000110100
00000110100
1
1
Cypress JEDEC ID code (11:1)
ID register presence indicator (0)
Describes the version number.
Reserved for Internal Use
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 18)
Bit Size (× 36)
3
3
Instruction
Bypass
1
1
ID
32
32
Boundary scan order (165-ball FBGA package)
89
89
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
13. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 38-05352 Rev. *G
Page 15 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
165-ball FBGA Boundary Scan Order[14,15]
CY7C1444AV33 (1 M × 36), CY7C1445AV33 (2 M × 18)
Bit #
Ball ID
Bit #
Ball ID
1
26
E11
N6
2
27
D11
N7
3
N10
28
G10
4
P11
29
F10
5
P8
30
E10
6
R8
31
D10
7
R9
32
C11
8
P9
33
A11
9
P10
34
B11
10
R10
35
A10
11
R11
36
B10
12
H11
37
A9
13
N11
38
B9
14
M11
39
C10
15
L11
40
A8
16
K11
41
B8
17
J11
42
A7
18
M10
43
B7
19
L10
44
B6
20
K10
45
A6
21
J10
46
B5
22
H9
47
A5
23
H10
48
A4
24
G11
49
B4
25
F11
50
B3
Bit #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Ball ID
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
G1
D2
E2
F2
G2
H1
H3
J1
K1
L1
M1
J2
K2
L2
M2
Bit #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
N1
N2
P1
R1
R2
P3
R3
P2
R4
P4
N5
P6
R6
Internal
Notes
14. Balls which are NC (No Connect) are pre-set LOW.
15. Bit# 89 is pre-set HIGH.
Document Number: 38-05352 Rev. *G
Page 16 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Maximum Ratings
DC input voltage .................................. –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, method 3015)
Latch-up current .................................................... > 200 mA
Operating Range
Supply voltage on VDD relative to GND ........–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND....... –0.5 V to +VDD
Range
Ambient
Temperature
VDD
VDDQ
DC voltage applied to outputs
in tri-state...........................................–0.5 V to VDDQ + 0.5 V
Commercial
0 °C to +70 °C
3.3 V– 5% /
+ 10%
2.5 V – 5%
to VDD
Industrial
–40 °C to +85 °C
Electrical Characteristics
Over the Operating Range [16, 17]
Parameter
Description
VDD
Power supply voltage
VDDQ
I/O supply voltage
VOH
VOL
VIH
VIL
IX
Output HIGH voltage
Output LOW voltage
Input HIGH
Input LOW
voltage[16]
voltage[16]
Test Conditions
Min
Max
Unit
3.135
3.6
V
for 3.3 V I/O
3.135
VDD
V
for 2.5V I/O
2.375
2.625
V
for 3.3 V I/O, IOH =4.0 mA
2.4
–
V
for 2.5 V I/O,I OH =1.0 mA
2.0
–
V
for 3.3 V I/O, IOL =8.0 mA
–
0.4
V
for 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
for 3.3 V I/O
2.0
VDD + 0.3V
V
for 2.5 V I/O
1.7
VDD + 0.3V
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
Input leakage current
except ZZ and MODE
GND  VI  VDDQ
–5
5
µA
Input current of MODE
Input = VSS
–30
–
µA
Input = VDD
–
5
µA
Input = VSS
–5
–
µA
Input = VDD
–
30
µA
Input current of ZZ
IOZ
Output leakage current GND  VI  VDDQ, output disabled
IDD
VDD operating supply
current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
–5
5
µA
4-ns cycle, 250 MHz
–
475
mA
5-ns cycle, 200 MHz
–
425
mA
6-ns cycle, 167 MHz
–
375
mA
ISB1
Automatic CE
power-down
current—TTL inputs
VDD = Max, device deselected,
VIN  VIH or VIN  VIL
f = fMAX = 1/tCYC
All speeds
–
225
mA
ISB2
Automatic CE
power-down
current—CMOS inputs
VDD = Max, device deselected,
All speeds
VIN  0.3V or VIN > VDDQ – 0.3 V,
f=0
–
120
mA
ISB3
Automatic CE
power-down
current—CMOS inputs
VDD = Max, device deselected, or All speeds
VIN  0.3 V or VIN > VDDQ – 0.3 V
f = fMAX = 1/tCYC
–
200
mA
ISB4
Automatic CE
power-down
current—TTL inputs
VDD = Max, device deselected,
VIN  VIH or VIN  VIL,
f=0
All speeds
–
135
mA
Notes
16. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
17. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05352 Rev. *G
Page 17 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Capacitance[18]
Parameter
Test Conditions
100 TQFP
Max
165 FBGA
Max
Unit
TA = 25 C, f = 1 MHz,
VDD = 3.3 V
VDDQ = 2.5 V
6.5
7
pF
3
7
pF
5.5
6
pF
Test Conditions
100 TQFP
Package
165 FBGA
Package
Unit
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA/JESD51.
25.21
20.8
C/W
2.28
3.2
C/W
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/output capacitance
Thermal Resistance[18]
Parameter
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317 
3.3 V
OUTPUT
OUTPUT
RL = 50 
Z0 = 50 
GND
5 pF
R = 351 
VT = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
 1 ns
 1 ns
(c)
(b)
2.5 V I/O Test Load
R = 1667 
2.5 V
OUTPUT
OUTPUT
RL = 50 
Z0 = 50 
GND
5 pF
R = 1538 
VT = 1.25 V
(a)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
 1 ns
 1 ns
(c)
Note
18. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05352 Rev. *G
Page 18 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Switching Characteristics
Over the Operating Range[19, 20]
Description
Parameter
tPOWER
VDD(Typical) to the first access[21]
–250
–200
–167
Unit
Min
Max
Min
Max
Min
Max
1
–
1
–
1
–
ms
Clock
tCYC
Clock cycle time
4.0
–
5
–
6
–
ns
tCH
Clock HIGH
1.5
–
2.0
–
2.4
–
ns
tCL
Clock LOW
1.5
–
2.0
–
2.4
–
ns
Output Times
tCO
Data output valid after CLK rise
–
2.6
–
3.2
–
3.4
ns
tDOH
Data output hold after CLK rise
1.0
–
1.5
–
1.5
–
ns
tCLZ
Clock to low Z[22, 23, 24]
1.0
–
1.3
–
1.5
–
ns
tCHZ
Clock to high
Z[22, 23, 24]
–
2.6
–
3.0
–
3.4
ns
tOEV
OE LOW to output valid
–
2.6
–
3.0
–
3.4
ns
Z[22, 23, 24]
tOELZ
OE LOW to output low
tOEHZ
OE HIGH to output high Z[22, 23, 24]
0
–
0
–
0
–
ns
–
2.6
–
3.0
–
3.4
ns
Set-up Times
tAS
Address set-up before CLK rise
1.2
–
1.4
–
1.5
–
ns
tADS
ADSC, ADSP set-up before CLK rise
1.2
–
1.4
–
1.5
–
ns
tADVS
ADV set-up before CLK rise
1.2
–
1.4
–
1.5
–
ns
tWES
GW, BWE, BWX set-up before CLK rise
1.2
–
1.4
–
1.5
–
ns
tDS
Data input set-up before CLK rise
1.2
–
1.4
–
1.5
–
ns
tCES
Chip enable set-up before CLK rise
1.2
–
1.4
–
1.5
–
ns
tAH
Address hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tADVH
ADV hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
Hold Times
Notes
19. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
21. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
22. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
23. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve high Z prior to low Z under the same system conditions.
24. This parameter is sampled and not 100% tested.
Document Number: 38-05352 Rev. *G
Page 19 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Switching Waveforms
Read Cycle Timing[25]
tCYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
tADH
ADSC
tAS
ADDRESS
tAH
A1
A2
tWES
A3
Burst continued with
new base address
tWEH
GW, BWE,BW
X
Deselect
cycle
tCES tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t
Data Out (DQ)
High-Z
CLZ
t OEHZ
Q(A1)
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
t CO
Single READ
BURST READ
DON’T CARE
Burst wraps around
to its initial state
UNDEFINED
Note
25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 38-05352 Rev. *G
Page 20 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Switching Waveforms
Write Cycle Timing[26, 27]
t CYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BWX
tWES tWEH
GW
tCES
tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t
DS
Data in (D)
High-Z
t
OEHZ
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document Number: 38-05352 Rev. *G
Page 21 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Switching Waveforms
Read/Write Cycle Timing[28, 29, 30]
tCYC
CLK
tCL
tCH
tADS
tADH
tAS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
tWES tWEH
BWE, BWX
tCES
tCEH
CE
ADV
OE
tDS
tCO
Data In (D)
tOELZ
High-Z
tOEHZ
tCLZ
Data Out (Q)
tDH
High-Z
Q(A1)
D(A3)
Q(A2)
Back-to-Back READs
Q(A4)
BURST READ
Single WRITE
DON’T CARE
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
28. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
29. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
30. GW is HIGH.
Document Number: 38-05352 Rev. *G
Page 22 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Switching Waveforms
ZZ Mode Timing[31, 32]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
31. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
32. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05352 Rev. *G
Page 23 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only
the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com
and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress
maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at t http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
167
Ordering Code
CY7C1444AV33-167AXC
Package
Diagram
Part and Package Type
51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free
Operating
Range
Commercial
Ordering Code Definitions
CY7C 1444
A V33 - 167 AX
C
Temperature range:
C = Commercial
Package Type:
AX = 100-pin TQFP (Pb-free)
Speed Grade (167 MHz)
V33 = 3.3 V
Process Technology  90 nm
1444 = DCD, 1 Mb × 36 (36 Mb)
CY7C = Cypress SRAMs
Document Number: 38-05352 Rev. *G
Page 24 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Package Diagram
51-85050 *C
Document Number: 38-05352 Rev. *G
Page 25 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Acronyms
Document Conventions
Acronym
Description
Units of Measure
CE
chip enable
CEN
clock enable
ns
nano seconds
FPBGA
fine-pitch ball grid array
V
Volts
I/O
input/output
µA
micro Amperes
JTAG
Joint Test Action Group
mA
milli Amperes
NoBL
No Bus Latency
ms
milli seconds
OE
output enable
MHz
Mega Hertz
SRAM
static random access memory
pF
pico Farad
TCK
test clock
W
Watts
TMS
test mode select
°C
degree Celcius
TDI
test data-in
TDO
test data-out
TQFP
thin quad flat pack
WE
write enable
Document Number: 38-05352 Rev. *G
Symbol
Unit of Measure
Page 26 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Document History Page
Document Title: CY7C1444AV33/CY7C1445AV33 36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM
Document Number: 38-05352
REV.
ECN NO.
Submission
Date
Orig. of
Change
Description of Change
**
124419
03/04/03
CGM
New data sheet
*A
254910
See ECN
SYT
Part number changed from previous revision. New and old part number
differ by the letter “A”
Modified Functional Block diagrams
Modified switching waveforms
Added boundary scan information
Added footnote #13 (32-Bit Vendor I.D Code changed)
Added IDD, IX and ISB values in DC Electrical Characteristics
Added tPOWER specifications in Switching Characteristics table
Removed 119 PBGA package
Changed 165 FBGA package from BB165 (15 x 17 x 1.20 mm) to
BB165C
(15 x 17 x 1.40 mm)
*B
303533
See ECN
SYT
Changed the test condition from VDD = Min. to VDD = Max for VOL in the
Electrical Characteristics table
Replaced JA and JC from TBD to respective Thermal Values for All
Packages on the Thermal Resistance Table
Changed IDD from 450, 400 & 350 mA to 475, 425 & 375 mA for 250,
200 and 167 Mhz respectively
Changed ISB1 from 190, 180 and 170 mA to 225 mA for 250, 200 and
167 Mhz respectively
Changed ISB2 from 80 mA to 100 mA for all frequencies
Changed ISB3 from 180, 170 & 160 mA to 200 mA for 250, 200 and 167
MHz respectively
Changed ISB4 from 100 mA to 110 mA for all frequencies
Changed CIN, CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for
TQFP Package
Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200
MHz Speed Bin
Added lead-free information for 100-pin TQFP and 165 FBGA packages
*C
331778
See ECN
SYT
Modified Address Expansion balls in the pinouts for 165 FBGA Package
as per JEDEC standards and updated the Pin Definitions accordingly
Modified VOL, VOH test conditions
Changed CIN, CCLK and CI/O to 7, 7and 6 pF from 5, 5 and 7 pF for 165
FBGA Package
Added Industrial Temperature Grades
Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively
Updated the Ordering Information by Shading and Unshading MPNs as
per availability
*D
417509
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1
from “3901 North First Street” to “198 Champion Court”
Changed IX current value in MODE from –5 & 30 A to –30 & 5 A
respectively and also Changed IX current value in ZZ from –30 & 5 A
to –5 & 30 A respectively on page# 16
Modified test condition from VIH < VDD to VIH VDD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE”
in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the
Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Document Number: 38-05352 Rev. *G
Page 27 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Document Title: CY7C1444AV33/CY7C1445AV33 36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM
Document Number: 38-05352
REV.
ECN NO.
Submission
Date
Orig. of
Change
*E
473229
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to
GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in
TAP AC Switching Characteristics table
Updated the Ordering Information table.
*F
2898663
03/24/2010
NJY
Removed inactive parts from Ordering Information table. Updated
package diagram.
*G
3042209
09/29/2010
NJY
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
Description of Change
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2003-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05352 Rev. *G
Revised September 29, 2010
Page 28 of 28
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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