CY7C1364C 9-Mbit (256 K × 32) Pipelined Sync SRAM 9-Mbit (256 K × 32) Pipelined Sync SRAM Features Functional Description ■ Registered inputs and outputs for pipelined operation ■ 256 K × 32 common I/O architecture ■ 3.3 V core power supply (VDD) ■ 2.5 V/3.3 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 3.5 ns (for 166-MHz device) ■ Provide high-performance 3-1-1-1 access rate ■ User-selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed writes ■ Asynchronous output enable ■ Available in 165-ball FBGA package ■ “ZZ” Sleep Mode Option ■ IEEE 1149.1 JTAG-compatible boundary scan The CY7C1364C SRAM integrates 256 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the Byte Write control inputs. GW when active LOW causes all bytes to be written. The CY7C1364C operates from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. For a complete list of related documentation, click here. Selection Guide Description 166 MHz Unit Maximum Access Time 3.5 ns Maximum Operating Current 180 mA Maximum CMOS Standby Current 40 mA Cypress Semiconductor Corporation Document Number: 001-74592 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 4, 2016 CY7C1364C Logic Block Diagram – CY7C1364C A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV CLK Q1 BURST COUNTER CLR AND Q0 LOGIC ADSC ADSP BWD DQD BYTE WRITE REGISTER DQD BYTE WRITE DRIVER BWC DQC BYTE WRITE REGISTER DQC BYTE WRITE DRIVER DQB BYTE WRITE REGISTER DQB BYTE WRITE DRIVER BWB BWA BWE GW CE1 CE2 CE3 OE ZZ SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQA BYTE WRITE DRIVER DQA BYTE WRITE REGISTER ENABLE REGISTER MEMORY ARRAY PIPELINED ENABLE INPUT REGISTERS SLEEP CONTROL Document Number: 001-74592 Rev. *E Page 2 of 29 CY7C1364C Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 5 Functional Overview ........................................................ 6 Single Read Accesses ................................................ 6 Single Write Accesses Initiated by ADSP ................... 6 Single Write Accesses Initiated by ADSC ................... 6 Burst Sequences ......................................................... 7 Sleep Mode ................................................................. 7 Interleaved Burst Address Table ................................. 7 Linear Burst Address Table ......................................... 7 ZZ Mode Electrical Characteristics .............................. 7 Truth Table ........................................................................ 8 Truth Table for Read/Write .............................................. 9 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 10 Disabling the JTAG Feature ...................................... 10 Test Access Port (TAP) ............................................. 10 PERFORMING A TAP RESET .................................. 10 TAP REGISTERS ...................................................... 10 TAP Instruction Set ................................................... 10 TAP Controller State Diagram ....................................... 12 TAP Controller Block Diagram ...................................... 13 TAP Timing ...................................................................... 13 TAP AC Switching Characteristics ............................... 14 3.3 V TAP AC Test Conditions ....................................... 14 3.3 V TAP AC Output Load Equivalent ......................... 14 2.5 V TAP AC Test Conditions ....................................... 14 2.5 V TAP AC Output Load Equivalent ......................... 14 Document Number: 001-74592 Rev. *E TAP DC Electrical Characteristics and Operating Conditions ............................................. 15 Identification Register Definitions ................................ 16 Scan Register Sizes ....................................................... 16 Instruction Codes ........................................................... 16 Boundary Scan Order .................................................... 17 Maximum Ratings ........................................................... 18 Operating Range ............................................................. 18 Electrical Characteristics ............................................... 18 Capacitance .................................................................... 19 Thermal Resistance ........................................................ 19 AC Test Loads and Waveforms ..................................... 19 Switching Characteristics .............................................. 20 Switching Waveforms .................................................... 21 Ordering Information ...................................................... 25 Ordering Code Definitions ......................................... 25 Package Diagram ............................................................ 26 Acronyms ........................................................................ 27 Document Conventions ................................................. 27 Units of Measure ....................................................... 27 Document History Page ................................................. 28 Sales, Solutions, and Legal Information ...................... 29 Worldwide Sales and Design Support ....................... 29 Products .................................................................... 29 PSoC® Solutions ...................................................... 29 Cypress Developer Community ................................. 29 Technical Support ..................................................... 29 Page 3 of 29 CY7C1364C Pin Configurations Figure 1. 165-ball FBGA (15 × 17 × 1.40 mm) pinout CY7C1364C (256 K × 32) 1 A B C D E F G H J K L M N P NC/288M R 2 3 4 5 6 7 8 9 10 BWE ADSC ADV A 11 NC CE1 BWC BWB CE3 NC/144M A CE2 BWD BWA CLK NC DQC VDDQ VSS VSS VSS VSS VDDQ VDDQ VSS VDD OE VSS VDD ADSP NC DQC GW VSS VSS A VDDQ NC/1G DQB NC DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC NC DQD DQC VDDQ VDD VSS VSS VSS VDD DQB VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ VDDQ NC VDDQ DQB DQC VSS DQD DQB NC DQA DQB ZZ DQA A NC/576M DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD NC DQD NC VDDQ VDDQ VDD VSS VSS NC VSS NC/18M VSS NC VDD VSS VDDQ VDDQ DQA NC DQA NC NC NC/72M A A TDI A1 TDO A A A A MODE NC/36M A A TMS TCK A A A A Document Number: 001-74592 Rev. *E A0 Page 4 of 29 CY7C1364C Pin Definitions Name A0, A1, A I/O Description InputAddress Inputs used to select one of the 256K address locations. Sampled at the rising edge of the Synchronous CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. BWA, BWB, InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. BWC, BWD Synchronous Sampled on the rising edge of CLK. GW InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global Write Synchronous is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE). BWE InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted Synchronous LOW to conduct a Byte Write. CLK InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 Synchronous and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE2 to select/deselect the device.CE3 is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. CE3 OE Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, InputAsynchronou the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a Read cycle when emerging from a deselected state. s ADV InputAdvance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it Synchronous automatically increments the address in a burst cycle. ADSP InputAddress Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted Synchronous LOW, A is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputAddress Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted Synchronous LOW, A is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ ZZ “sleep” Input, active HIGH. This input, when High places the device in a non-time-critical “sleep” InputAsynchronou condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. s DQs I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by “A” during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ are placed in a tri-state condition. VDD Power Supply Power supply inputs to the core of the device. VSS Ground Ground for the core of the device. VDDQ I/O Power Supply Power supply for the I/O circuitry. VSSQ I/O Ground Ground for the I/O circuitry. MODE TDO InputStatic Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode pin has an internal pull-up. JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being used, this pin should be disconnected. output synchronous Document Number: 001-74592 Rev. *E Page 5 of 29 CY7C1364C Pin Definitions (continued) Name I/O Description TDI JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being used, this pin can be disconnected or connected to VDD. input synchronous TMS JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being input used, this pin can be disconnected or connected to VDD. synchronous TCK JTAGclock NC – Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected to VSS. No Connects. Not internally connected to the die. Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1364C supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the Write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the address register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the output registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tCO if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately. Document Number: 001-74592 Rev. *E Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the RAM array. The Write signals (GW, BWE, and BW[A:D]) and ADV inputs are ignored during this first cycle. ADSP-triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQ inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the Write operation is controlled by BWE and BW[A:D] signals. The CY7C1364C provides Byte Write capability that is described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW[A:D]) input, will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1364C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BW[A:D]) are asserted active to conduct a Write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to the DQ is written into the corresponding address location in the memory core. If a Byte Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1364C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will tri-state the output drivers. As a Page 6 of 29 CY7C1364C safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Burst Sequences Interleaved Burst Address Table (MODE = Floating or VDD) The CY7C1364C provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. First Address A1:A0 Second Address A1:A0 Third Address A1:A0 00 01 10 11 01 00 11 10 10 11 00 01 Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported. 11 10 01 00 Fourth Address A1:A0 Sleep Mode Linear Burst Address Table The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. (MODE = GND) Fourth Address A1:A0 First Address A1:A0 Second Address A1:A0 Third Address A1:A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 50 mA tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC – ns tZZI ZZ Active to Sleep current This parameter is sampled – 2tCYC ns tRZZI ZZ Inactive to exit Sleep current This parameter is sampled 0 – ns Document Number: 001-74592 Rev. *E Page 7 of 29 CY7C1364C Truth Table The truth table for CY7C1364C follows. [1, 2, 3, 4, 5] Next Cycle Address Used ZZ CE3 CE2 CE1 ADSP ADSC ADV OE DQ Write Unselected None L X X H X L X X Tri-State X Unselected None L H X L L X X X Tri-State X Unselected None L X L L L X X X Tri-State X Unselected None L H X L H L X X Tri-State X Unselected None L X L L H L X X Tri-State X Begin Read External L L H L L X X X Tri-State X Begin Read External L L H L H L X X Tri-State Read Continue Read Next L X X X H H L H Tri-State Read Continue Read Next L X X X H H L L Continue Read Next L X X H X H L H Continue Read Next L X X H X H L L Suspend Read Current L X X X H H H H Suspend Read Current L X X X H H H L Suspend Read Current L X X H X H H H Suspend Read Current L X X H X H H L Begin Write Current L X X X H H H X Tri-State Write Begin Write Current L X X H X H H X Tri-State Write Begin Write External L L H L H H X X Tri-State Write Continue Write Next L X X X H H H X Tri-State Write Continue Write Next L X X H X H H X Tri-State Write Suspend Write Current L X X X H H H X Tri-State Write Suspend Write Current L X X H X H H X Tri-State Write None H X X X X X X X Tri-State ZZ “Sleep” DQ Read Tri-State Read DQ Read Tri-State Read DQ Read Tri-State Read DQ Read X Notes 1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 2. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA,BWB,BWC,BWD), BWE, GW = H. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the Write cycle. 5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 001-74592 Rev. *E Page 8 of 29 CY7C1364C Truth Table for Read/Write The Truth Table for Read/Write for CY7C1364C follows. [6, 7] GW BWE BWD BWC BWB BWA Read Function H H X X X X Read H L H H H H Write Byte A – DQA H L H H H L Write Byte B – DQB H L H H L H Write Bytes B, A H L H H L L Write Byte C – DQC H L H L H H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – DQD H L L H H H Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, C H L L L H H Write Bytes D, C, A H L L L H L Write Bytes D, C, B H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Notes 6. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 7. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA,BWB,BWC,BWD), BWE, GW = H. Document Number: 001-74592 Rev. *E Page 9 of 29 CY7C1364C IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Registers The CY7C1364C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic levels. The CY7C1364C contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Registers are connected between the TDI and TDO balls and enable data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device comes up in a reset state which does not interfere with the operation of the device. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram on page 12. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction Codes on page 16). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 13. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to enable fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This enables data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order on page 17 show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 16. TAP Instruction Set Performing a TAP Reset Overview A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Instruction Codes on page 16. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail in this section. At power-up, the TAP is reset internally to ensure that TDO comes up in a high Z state. Document Number: 001-74592 Rev. *E Page 10 of 29 CY7C1364C The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a high Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a high Z state. Document Number: 001-74592 Rev. *E SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required – that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 11 of 29 CY7C1364C TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCA N 1 SELECT IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-IR 0 1 0 PAUSE-DR 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR 1 0 1 EXIT1-DR 0 1 0 UPDATE-IR 1 0 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Document Number: 001-74592 Rev. *E Page 12 of 29 CY7C1364C TAP Controller Block Diagram 0 Bypass Register 2 1 0 Selection Circuitry TDI Selection Circuitry Instruction Register TDO 31 30 29 . . . 2 1 0 Identification Register x . . . . . 2 1 0 Boundary Scan Register TCK TAP CONTROLLER TM S TAP Timing 1 2 Test Clock (TCK ) 3 t TH t TM SS t TM SH t TDIS t TDIH t TL 4 5 6 t CY C Test M ode Select (TM S) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CA RE Document Number: 001-74592 Rev. *E UNDEFINED Page 13 of 29 CY7C1364C TAP AC Switching Characteristics Over the Operating Range Parameter [8, 9] Description Min Max Unit Clock tTCYC TCK clock cycle time 50 – ns tTF TCK clock frequency – 20 MHz tTH TCK clock HIGH time 20 – ns tTL TCK clock LOW time 20 – ns tTDOV TCK clock LOW to TDO valid – 10 ns tTDOX TCK clock LOW to TDO invalid 0 – ns tTMSS TMS setup to TCK clock rise 5 – ns tTDIS TDI setup to TCK clock rise 5 – ns tCS Capture setup to TCK rise 5 – ns tTMSH TMS hold after TCK clock rise 5 – ns tTDIH TDI hold after clock rise 5 – ns tCH Capture hold after clock rise 5 – ns Output Times Setup Times Hold Times 3.3 V TAP AC Test Conditions 2.5 V TAP AC Test Conditions Input pulse levels ...............................................VSS to 3.3 V Input rise and fall times ...................................................1 ns Input pulse levels ............................................... VSS to 2.5 V Input rise and fall time ....................................................1 ns Input timing reference levels ......................................... 1.5 V Input timing reference levels ....................................... 1.25 V Output reference levels ................................................ 1.5 V Output reference levels .............................................. 1.25 V Test load termination supply voltage ............................ 1.5 V Test load termination supply voltage .......................... 1.25 V 3.3 V TAP AC Output Load Equivalent 2.5 V TAP AC Output Load Equivalent 1.5V 1.25V 50Ω TDO 50Ω TDO Z O= 50Ω 20pF Z O= 50Ω 20pF Notes 8. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 9. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document Number: 001-74592 Rev. *E Page 14 of 29 CY7C1364C TAP DC Electrical Characteristics and Operating Conditions (0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted) Parameter [10] VOH1 Description Output HIGH voltage Min Max Unit IOH = –4.0 mA Conditions VDDQ = 3.3 V 2.4 – V IOH = –1.0 mA VDDQ = 2.5 V 2.0 – V VDDQ = 3.3 V 2.9 – V VOH2 Output HIGH voltage IOH = –100 µA VDDQ = 2.5 V 2.1 – V VOL1 Output LOW voltage IOL = 8.0 mA VDDQ = 3.3 V – 0.4 V IOL = 8.0 mA VDDQ = 2.5 V – 0.4 V IOL = 100 µA VDDQ = 3.3 V – 0.2 V VOL2 Output LOW voltage VIH Input HIGH voltage VIL Input LOW voltage IX Input load current GND < VIN < VDDQ VDDQ = 2.5 V – 0.2 V VDDQ = 3.3 V 2.0 VDD + 0.3 V VDDQ = 2.5 V 1.7 VDD + 0.3 V VDDQ = 3.3 V –0.5 0.7 V VDDQ = 2.5 V –0.3 0.7 V –5 5 µA Note 10. All voltages referenced to VSS (GND). Document Number: 001-74592 Rev. *E Page 15 of 29 CY7C1364C Identification Register Definitions Instruction Field CY7C1364C (256 K × 32) Revision number (31:29) 000 Device depth (28:24) [11] 01011 Device width (23:18) 165-ball FBGA 000000 Cypress device ID (17:12) 011110 Cypress JEDEC ID code (11:1) 00000110100 ID register presence indicator (0) 1 Description Describes the version number Reserved for internal use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor Indicates the presence of an ID register Scan Register Sizes Register Name Bit Size (× 32) Instruction 3 Bypass 1 ID 32 Boundary scan order (165-ball FBGA package) 71 Instruction Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to high Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Note 11. Bit #24 is “1” in the Register Definitions for both 2.5 V and 3.3 V versions of this device. Document Number: 001-74592 Rev. *E Page 16 of 29 CY7C1364C Boundary Scan Order 165-ball FBGA CY7C1364C (256 K × 32) Bit# Ball ID Signal Name Bit# Ball ID Signal Name 1 B6 CLK 37 R6 A0 2 B7 GW 38 P6 A1 3 A7 BWE 39 R4 A 4 B8 OE 40 P4 A 5 A8 ADSC 41 R3 A 6 B9 ADSP 42 P3 A 7 A9 ADV 43 R1 MODE 8 B10 A 44 N1 NC 9 A10 A 45 L2 DQD 10 C11 NC 46 K2 DQD 11 E10 DQB 47 J2 DQD 12 F10 DQB 48 M2 DQD 13 G10 DQB 49 M1 DQD 14 D10 DQB 50 L1 DQD 15 D11 DQB 51 K1 DQD 16 E11 DQB 52 J1 DQD 17 F11 DQB 53 Internal Internal 18 G11 DQB 54 G2 DQC 19 H11 ZZ 55 F2 DQC 20 J10 DQA 56 E2 DQC 21 K10 DQA 57 D2 DQC 22 L10 DQA 58 G1 DQC 23 M10 DQA 59 F1 DQC 24 J11 DQA 60 E1 DQC 25 K11 DQA 61 D1 DQC 26 L11 DQA 62 C1 NC 27 M11 DQA 63 B2 A 28 N11 NC 64 A2 A 29 R11 A 65 A3 CE1 30 R10 A 66 B3 CE2 31 P10 A 67 B4 BWD 32 R9 A 68 A4 BWC 33 P9 A 69 A5 BWB 34 R8 A 70 B5 BWA 71 A6 CE3 35 P8 A 36 P11 A Document Number: 001-74592 Rev. *E Page 17 of 29 CY7C1364C Maximum Ratings DC Input Voltage ................................ –0.5 V to VDD + 0.5 V Exceeding maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied ......................................... –55 C to +125 C Supply Voltage on VDD Relative to GND .....–0.5 V to +4.6 V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) .......................... >2001 V Latch-up Current ..................................................... >200 mA Operating Range Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD DC Voltage Applied to Outputs in tri-state ..........................................–0.5 V to VDDQ + 0.5 V Ambient Temperature Range Industrial –40 °C to +85 °C VDD VDDQ 3.3 V– 5% / 2.5 V – 5% to + 10% VDD Electrical Characteristics Over the Operating Range Parameter [12, 13] Description VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH VOL VIH VIL IX Output HIGH Voltage Output LOW Voltage Input HIGH Voltage [12] Input LOW Voltage [12] Test Conditions Min Max Unit 3.135 3.6 V for 3.3 V I/O 3.135 VDD V for 2.5 V I/O 2.375 2.625 V for 3.3 V I/O, IOH = –4.0 mA 2.4 – V for 2.5 V I/O, IOH = –1.0 mA 2.0 – V for 3.3 V I/O, IOL = 8.0 mA – 0.4 V for 2.5 V I/O, IOL = 1.0 mA – 0.4 V for 3.3 V I/O 2.0 VDD + 0.3 V for 2.5 V I/O 1.7 VDD + 0.3 V for 3.3 V I/O –0.3 0.8 V for 2.5 V I/O –0.3 0.7 V Input Leakage Current except ZZ GND VI VDDQ and MODE –5 5 A Input Current of MODE Input = VSS –30 – A Input = VDD – 5 A Input = VSS –5 – A Input Current of ZZ Input = VDD – 30 A IOZ Output Leakage Current GND VI VDDQ, Output Disabled –5 5 A IDD VDD Operating Supply Current VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC 6-ns cycle, 166 MHz – 180 mA ISB1 Automatic CE Power-down Current – TTL Inputs VDD = Max, Device Deselected, 6-ns cycle, VIN VIH or VIN VIL, 166 MHz f = fMAX = 1/tCYC – 110 mA ISB2 Automatic CE Power-down Current – CMOS Inputs VDD = Max, Device Deselected, 6-ns cycle, VIN 0.3 V or VIN > VDDQ – 0.3 V, 166 MHz f=0 – 40 mA Notes 12. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2). 13. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document Number: 001-74592 Rev. *E Page 18 of 29 CY7C1364C Electrical Characteristics (continued) Over the Operating Range Parameter [12, 13] Description Test Conditions Min Max Unit ISB3 Automatic CE Power-down Current – CMOS Inputs VDD = Max, Device Deselected, 6-ns cycle, VIN 0.3 V or VIN > VDDQ – 0.3 V, 166 MHz f = fMAX = 1/tCYC – 100 mA ISB4 Automatic CE Power-down Current – TTL Inputs VDD = Max, Device Deselected, 6-ns cycle, VIN VIH or VIN VIL, f = 0 166 MHz – 40 mA Capacitance Parameter [14] Description CIN Input capacitance CCLK CI/O 165-ball FBGA Unit Max. Test Conditions TA = 25 °C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V 5 pF Clock input capacitance 5 pF Input/Output capacitance 7 pF Thermal Resistance Parameter [14] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) 165-ball FBGA Unit Package Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 16.8 C/W 3 C/W AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms 3.3 V I/O Test Load R = 317 3.3V OUTPUT OUTPUT RL = 50 Z0 = 50 VT = 1.5V (a) INCLUDING JIG AND SCOPE Z0 = 50 VT = 1.25V (a) R = 351 10% (c) ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE 1 ns (b) GND 5 pF 90% 10% 90% 1 ns R = 1667 2.5V OUTPUT RL = 50 GND 5 pF 2.5 V I/O Test Load OUTPUT ALL INPUT PULSES VDDQ R =1538 (b) 10% 90% 10% 90% 1 ns 1 ns (c) Note 14. Tested initially and after any design or process change that may affect these parameters. Document Number: 001-74592 Rev. *E Page 19 of 29 CY7C1364C Switching Characteristics Over the Operating Range Parameter [15, 16] tPOWER Description VDD(typical) to the first access [17] -166 Unit Min Max 1 – ms Clock tCYC Clock cycle time 6.0 – ns tCH Clock HIGH 2.4 – ns tCL Clock LOW 2.4 – ns Output Times tCO Data output valid after CLK rise – 3.5 ns tDOH Data output hold after CLK rise 1.25 – ns 1.25 – ns 1.25 3.5 ns – 3.5 ns 0 – ns – 3.5 ns [18, 19, 20] tCLZ Clock to low Z tCHZ Clock to high Z [18, 19, 20] tOEV OE LOW to output valid tOELZ tOEHZ OE LOW to output low Z [18, 19, 20] OE HIGH to output high Z [18, 19, 20] Set-up Times tAS Address set-up before CLK rise 1.5 – ns tADS ADSC, ADSP set-up before CLK rise 1.5 – ns tADVS ADV set-up before CLK rise 1.5 – ns tWES GW, BWE, BW[A:D] set-up before CLK rise 1.5 – ns tDS Data input set-up before CLK rise 1.5 – ns tCES Chip enable set-up before CLK rise 1.5 – ns tAH Address hold after CLK rise 0.5 – ns tADH ADSP, ADSC hold after CLK rise 0.5 – ns tADVH ADV hold after CLK rise 0.5 – ns tWEH GW, BWE, BW[A:D] hold after CLK rise 0.5 – ns tDH Data input hold after CLK rise 0.5 – ns tCEH Chip enable hold after CLK rise 0.5 – ns Hold Times Notes 15. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 16. Test conditions shown in (a) of Figure 2 on page 19 unless otherwise noted. 17. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation can be initiated. 18. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 19. Transition is measured ±200 mV from steady-state voltage. 19. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z prior to Low Z under the same system conditions. 20. This parameter is sampled and not 100% tested. Document Number: 001-74592 Rev. *E Page 20 of 29 CY7C1364C Switching Waveforms Figure 3. Read Cycle Timing [21] t CYC CLK t CH t ADS t CL t ADH ADSP tADS tADH ADSC tAS tAH A1 ADDRESS A2 tWES A3 Burst continued with new base address tWEH GW, BWE, BW[A:D] tCES Deselect cycle tCEH CE tADVS tADVH ADV ADV suspends burst. OE t OEHZ t CLZ Data Out (Q) High-Z Q(A1) tOEV tCO t OELZ tDOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) t CO Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note 21. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document Number: 001-74592 Rev. *E Page 21 of 29 CY7C1364C Switching Waveforms (continued) Figure 4. Write Cycle Timing [22, 23] t CYC CLK tCH tADS tCL tADH ADSP tADS ADSC extends burst tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst tWES tWEH BWE, BW[A :D] tWES tWEH GW tCES tCEH CE t t ADVS ADVH ADV ADV suspends burst OE tDS Data In (D) High-Z t OEHZ tDH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Notes 22. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 23. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW. Document Number: 001-74592 Rev. *E Page 22 of 29 CY7C1364C Switching Waveforms (continued) Figure 5. Read/Write Cycle Timing [24, 25, 26] tCYC CLK tCL tCH tADS tADH ADSP ADSC tAS ADDRESS A1 tAH A2 A3 A4 tWES tWEH tDS tDH A5 A6 D(A5) D(A6) BWE, BW[A:D] tCES tCEH CE ADV OE tCO tOELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) tOEHZ D(A3) Q(A4) Q(A2) Back-to-Back READs Single WRITE Q(A4+1) BURST READ DON’T CARE Q(A4+2) Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes 24. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 25. The data bus (Q) remains in High Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed. 26. GW is HIGH. Document Number: 001-74592 Rev. *E Page 23 of 29 CY7C1364C Switching Waveforms (continued) Figure 6. ZZ Mode Timing [27, 28] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 27. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 28. DQs are in High Z when exiting ZZ sleep mode. Document Number: 001-74592 Rev. *E Page 24 of 29 CY7C1364C Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 166 Package Diagram Ordering Code CY7C1364C-166BZI Part and Package Type 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Operating Range Industrial Ordering Code Definitions CY 7 C 1364 C - 166 BZ I Temperature range: I = Industrial = –40 °C to +85 °C Package Type: BZ = 165-ball FBGA Speed Grade: 166 MHz Process Technology: C 90 nm Part Identifier: 1364 = DCD, 256 K × 32 (9 Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-74592 Rev. *E Page 25 of 29 CY7C1364C Package Diagram Figure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180 51-85180 *G Document Number: 001-74592 Rev. *E Page 26 of 29 CY7C1364C Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius EIA Electronic Industries Alliance MHz megahertz FBGA Fine-Pitch Ball Grid Array µA microampere I/O Input/Output mA milliampere JEDEC Joint Electron Devices Engineering Council mm millimeter OE Output Enable ms millisecond SRAM Static Random Access Memory mV millivolt TTL Transistor-Transistor Logic Document Number: 001-74592 Rev. *E Symbol Unit of Measure ns nanosecond ohm % percent pF picofarad V volt W watt Page 27 of 29 CY7C1364C Document History Page Document Title: CY7C1364C, 9-Mbit (256 K × 32) Pipelined Sync SRAM Document Number: 001-74592 Rev. ECN No. Issue Date Orig. of Change ** 3489597 01/10/2012 PRIT Description of Change New data sheet. *A 3508648 01/25/2012 PRIT Changed status from Preliminary to Final. *B 3537338 02/28/2012 PRIT Updated Pin Definitions. Added IEEE 1149.1 Serial Boundary Scan (JTAG). Added TAP Controller State Diagram. Added TAP Controller Block Diagram. Added TAP Timing. Added TAP AC Switching Characteristics. Added 3.3 V TAP AC Test Conditions. Added 3.3 V TAP AC Output Load Equivalent. Added 2.5 V TAP AC Test Conditions. Added 2.5 V TAP AC Output Load Equivalent. Added TAP DC Electrical Characteristics and Operating Conditions. Added Identification Register Definitions. Added Scan Register Sizes. Added Instruction Codes. Added Boundary Scan Order. *C 3800880 11/02/2012 PRIT Updated Package Diagram (spec 51-85180 (Changed revision from *E to *F)). *D 4576419 11/24/2014 PRIT Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *E 5071299 01/04/2016 PRIT Updated Package Diagram: spec 51-85180 – Changed revision from *F to *G. Updated to new template. Completing Sunset Review. Document Number: 001-74592 Rev. *E Page 28 of 29 CY7C1364C Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2012-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-74592 Rev. *E Revised January 4, 2016 Page 29 of 29 i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark of IBM Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.