TPS62175, TPS62177 www.ti.com SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 28V, 0.5A Step-Down Converter with Sleep Mode Check for Samples: TPS62175, TPS62177 FEATURES DESCRIPTION • • • • • • • • • • • • • • The TPS62175/7 is a high efficiency synchronous step-down DC-DC converter, based on the DCSControl™ topology. 1 2 DCS-Control™ Topology Input Voltage Range 4.75 to 28V Quiescent Current typ. 4.8µA (Sleep Mode) 100% Duty Cycle Mode Active Output Discharge Power Good Output Output Current of 500mA Output Voltage Range 1V to 6V Switching Frequency of Typically 1MHz Seamless Power Save Mode Transition Undervoltage Lockout Short Circuit Protection Over Temperature Protection Available in 2 x 3 mm 10-pin WSON Package With a wide operating input voltage range of 4.75 to 28V, the device is ideally suited for systems powered from multi cell Li-Ion as well as 12V and even higher intermediate supply rails, providing up to 500mA output current. The TPS62175/7 automatically enters Power Save Mode at light loads, to maintain high efficiency across the whole load range. As well, it features a Sleep Mode to supply applications with advanced power save modes like ultra low power micro controllers. The Power Good output may be used for power sequencing and/or Power On Reset. The device features a typical quiescent current of 22uA in normal mode and 4.8uA in Sleep Mode. In Sleep Mode, the efficiency at very low load currents can be increased by as much as 20%. In shutdown mode, the shutdown current is less than 2uA and the output is actively discharged. APPLICATIONS • • • • • General 12V/24V Point Of Load Supply Ultra Mobile PC, Embedded PC Low Power Supply for Microprocessor High Efficiency LDO Alternative Industrial Sensors The TPS62175/7, available in an adjustable and a fixed output voltage version, is packaged in a small 2x3mm 10-pin WSON package. spacingspacing spacingspacing spacingspacing 10uH 4.75 to 28V VIN EN 2.2uF 3.3V/0.5A SW TPS62177 VOS SLEEP PG AGND FB PGND NC 100k 22uF Figure 1. Typical Application and Efficiency 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DCS-Control is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS62175, TPS62177 SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (2) TA OUTPUT VOLTAGE -40°C to 85°C (1) (2) (2) PART NUMBER adjustable TPS62175 3.3 V TPS62177 PACKAGE 10-Pin WSON ORDERING PACKAGE MARKING TPS62175DQC 62175 TPS62177DQC 62177 For detailed ordering information please check the PACKAGE OPTION ADDENDUM section at the end of this datasheet. Contact the factory to check availability of other output voltage or current limit versions. ABSOLUTE MAXIMUM RATINGS (1) Pin Voltage Range (2) MIN MAX UNIT VIN -0.3 30 V EN, SW -0.3 VIN+0.3 V FB, PG, VOS, SLEEP, NC -0.3 7 V 10 mA Power Good Sink Current PG Temperature Range Operating junction temperature, TJ -40 125 Storage temperature, Tstg -65 150 HBM Human body model ESD rating (3) (1) (2) (3) CDM Charge device model °C 2 kV 0.5 kV Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. All voltages are with respect to network ground terminal. ESD testing is performed according to the respective JESD22 JEDEC standard. THERMAL INFORMATION THERMAL METRIC (1) TPS62175/7 UNITS DQC (10) PINS θJA Junction-to-ambient thermal resistance 61.6 θJC(TOP) Junction-to-case(top) thermal resistance 65.5 θJB Junction-to-board thermal resistance 22.5 ψJT Junction-to-top characterization parameter 1.4 ψJB Junction-to-board characterization parameter 22.4 θJC(BOTTOM) Junction-to-case(bottom) thermal resistance 5.3 °C/W spacingspacing (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS MIN MAX Supply Voltage, VIN 4.75 28 V Operating free air temperature, TA –40 85 °C Operating junction temperature, TJ –40 125 °C 2 Submit Documentation Feedback UNIT Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 TPS62175, TPS62177 www.ti.com SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 ELECTRICAL CHARACTERISTICS over free-air temperature range (TA=-40°C to +85°C) and VIN=4.75 to 28V. Typical values at VIN=12V and TA=25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VIN Input Voltage Range IQ Operating Quiescent Current EN=High, SLEEP=High, IOUT=0mA, device not switching 4.75 IQ_SLEEP Sleep Mode Quiescent Current EN=High, SLEEP=Low, IOUT=0mA, device not switching ISD Shutdown Current EN=Low, current into VIN pin VUVLO Undervoltage Lockout Threshold Rising Input Voltage TSD Thermal Shutdown Temperature Rising Junction Temperature 4.5 Falling Input Voltage 28 V 22 36 µA 4.8 10 µA 1.5 5 µA 4.6 4.7 V 2.9 V 150 °C Thermal Shutdown Hysteresis 20 CONTROL (EN, PG, SLEEP) VH VL High Level Input Threshold Voltage (EN, SLEEP) 0.9 V Low Level Input Threshold Voltage (EN, SLEEP) ILKG_EN Input Leakage Current (EN) EN=VIN ILKG_SLEEP Input Leakage Current (SLEEP) VSLEEP = 3.3V VTH_PG Power Good Threshold Voltage VOL_PG Power Good Output Low Voltage IPG = -2mA ILKG_PG Input Leakage Current (PG) VPG = 5V 5 0.3 V 300 nA 1.4 µA Rising (%VOUT) 93 96 99 Falling (%VOUT) 87 90 93 5 % 0.3 V 300 nA POWER SWITCH RDS(ON) High-Side MOSFET ON-Resistance VIN ≥ 6V 850 1430 mΩ Low-Side MOSFET ON-Resistance VIN ≥ 6V 320 mΩ High-Side MOSFET Current Limit Normal Operation 800 Startup Mode 450 VOUT Output Voltage Range (TPS62175) VIN ≥ VOUT VREF Internal Reference Voltage IOUT_SLEEP Output Current in Sleep SLEEP= Low, VOUT=3.3V, L=10µH Mode ILKG_FB Input Leakage Current (FB) ILIMF 530 1000 1200 525 600 mA OUTPUT 1 6 0.8 VFB= 0.8V V 15 mA 1 100 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 V nA 3 TPS62175, TPS62177 SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over free-air temperature range (TA=-40°C to +85°C) and VIN=4.75 to 28V. Typical values at VIN=12V and TA=25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TPS62175 (adjustable Vout), VIN ≥ VOUT +1V Output Voltage Accuracy (1) Power Save Mode, L=10µH Sleep Mode, IOUT≤15mA TPS62177 (3.3V fixed Vout) VOUT Power Save Mode, 4 Output Discharge Resistance EN=Low Load Regulation VOUT=3.3V, PWM mode operation Line Regulation VOUT=3.3V, IOUT= 500mA, PWM mode operation TYP MAX -1.8 1.8 VOUT ≥ 2.5V, COUT=22µF -1.8 3 VOUT < 2.5V, COUT=44µF -1.8 3.7 COUT=22µF, L=10µH -1.6 2.9 -2 2 -2 2.9 -1.6 2.7 PWM Mode Sleep Mode, IOUT≤15mA (1) MIN PWM Mode COUT=22µF, L=10µH UNIT % 175 Ω 0.02 %/A 0.015 %/V The output voltage accuracy in Power Save and Sleep Mode can be improved by increasing the output capacitor value, reducing the output voltage ripple (see APPLICATION INFORMATION section). Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 TPS62175, TPS62177 www.ti.com SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 DEVICE INFORMATION DQC PACKAGE (TOP VIEW) PGND 1 10 VOS VIN 2 9 SW EN 3 8 SLEEP NC 4 7 PG FB 5 6 AGND Exposed Thermal Pad spacingspacing TERMINAL FUNCTIONS PIN (1) I/O DESCRIPTION NAME NO. PGND 1 VIN 2 I Supply voltage for the converter. EN 3 I Enable input (High=Enabled, Low= Disabled) NC 4 FB 5 AGND 6 PG 7 O Output power good. (open drain, requires pull-up resistor) SLEEP 8 I Sleep mode input (High=Normal Operation, Low=Sleep mode Operation). Can be operated dynamically during operation. SW 9 O Switch node, connected to the internal MOSFET switches. Connect inductor between SW and output capacitor. VOS 10 I Output voltage sense pin and connection for the control loop circuitry. Exposed Thermal Pad (1) Power ground connection. This pin is recommended to be connected to AGND but can left be floating. I Voltage feedback of adjustable version. Connect resistive divider to this pin. It is recommended to connect FB to AGND for fixed voltage versions for improved thermal performance. Analog ground connection. Must be connected to AGND and PGND. Must be soldered to achieve appropriate power dissipation and mechanical reliability. For more information about connecting pins, see DETAILED DESCRIPTION and APPLICATION INFORMATION sections. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 5 TPS62175, TPS62177 SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM PG Soft start Thermal Shtdwn UVLO VIN PG control HS lim comp EN* td=1ms control logic power control NC SLEEP* gate drive SW sleep control VOS direct control & compensation ramp 175 _ FB comparator + EN VREF timer tON, tOFF error amplifier DCS - ControlTM * This pin is connected to a pull down resistor internally (see Detailed Description section). AGND PGND Figure 2. TPS62175 (adjustable output voltage) 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 TPS62175, TPS62177 www.ti.com SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 PG Soft start Thermal Shtdwn UVLO VIN PG control HS lim comp EN* td=1ms control logic power control NC SLEEP* gate drive SW Sleep control VOS direct control & compensation 1.25M ramp 175 _ FB comparator 400k + EN VREF timer tON,tOFF error amplifier DCS - ControlTM * This pin is connected to a pull down resistor internally (see Detailed Description section). AGND PGND Figure 3. TPS62177 (fixed output voltage) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 7 TPS62175, TPS62177 SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION List of Components REFERENCE DESCRIPTION MANUFACTURER IC 28V, 0.5A Step-Down Converter, WSON TPS62175DQC, Texas Instruments L1 10uH, (4 x 4 x 1.2) mm Cin 2.2µF, 50V, Ceramic, 0805, X5R Standard Cout 22µF, 6.3V, Ceramic, 0805, X5R Standard R1 depending on Vout R2 depending on Vout R3 100kΩ, Chip, 0603, 1/16W, 1% LPS4012, Coilcraft Standard spacing spacing 10uH VIN VIN EN CIN VOUT SW TPS62175 VOS SLEEP PG AGND FB PGND NC R3 R1 COUT R2 Figure 4. Measurement Setup TYPICAL CHARACTERISTICS Table of Graphs DESCRIPTION Efficiency Output voltage Switching Frequency FIGURE vs Output Current, vs Input Voltage 5 - 20 vs Output current (Load regulation) 21 vs Input Voltage (Line regulation) 22 vs Input Voltage 23 vs Output Current 24 Quiescent Current vs Input Voltage Shutdown Current vs Input Voltage Power FET RDS(on) vs Input Voltage (High-Side, Low-Side) Maximum Output Current vs Input Voltage Waveforms 25, 26 27 30 Sleep Mode Transition 31, 32 Load Transient Response 33 - 38 Line Transient Response 39, 40 Startup 41 - 43 Output Discharge 8 28, 29 44 Typical Operation (PWM Mode, Power Save Mode, Sleep Mode, Short Circuit) 45 - 52 Triangular Load Sweep with Mode Transitions 53, 54 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 TPS62175, TPS62177 www.ti.com SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 100.0 100.0 90.0 90.0 80.0 80.0 Efficiency (%) 70.0 VIN=24V 60.0 VIN=12V 50.0 40.0 VIN=7.5 30.0 10.0 0.0 0.01 VIN=6V 0.1 1 10 Output Current (mA) 100 0.0 500 6 8 10 12 G001 14 16 18 20 Input Voltage (V) Figure 5. Vout=5V Figure 6. Vout=5V EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs INPUT VOLTAGE 22 24 26 28 G001 IOUT=1mA 80.0 VIN=7.5 70.0 VIN=24V VIN=6V VIN=12V 50.0 40.0 70.0 60.0 50.0 IOUT=100uA 40.0 IOUT=10uA 30.0 VOUT=5V L=10uH (LPS4012) Cout=22uF 20.0 10.0 0.01 0.1 1 Output Current (mA) VOUT=5V L=10uH (LPS4012) Cout=22uF 20.0 10.0 0.0 10 20 6 8 10 12 G001 14 16 18 20 Input Voltage (V) 22 24 Figure 8. Vout=5V (Sleep Mode) EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs INPUT VOLTAGE 90.0 80.0 80.0 70.0 70.0 60.0 VIN=24V VIN=12V 50.0 Efficiency (%) 100.0 90.0 40.0 VIN=7.5 30.0 20.0 VIN=5V 0.1 26 28 G001 Figure 7. Vout=5V (Sleep Mode) 100.0 0.0 0.01 VOUT=5V L=10uH (LPS4012) Cout=22uF 10.0 90.0 10.0 IOUT=100mA 40.0 100.0 0.0 0.001 IOUT=10mA 50.0 90.0 60.0 IOUT=1mA 60.0 20.0 30.0 Efficiency (%) 70.0 100.0 80.0 IOUT=500mA 30.0 VOUT=5V L=10uH (LPS4012) Cout=22uF 20.0 Efficiency (%) EFFICIENCY vs INPUT VOLTAGE Efficiency (%) Efficiency (%) EFFICIENCY vs OUTPUT CURRENT IOUT=500mA IOUT=1mA 60.0 IOUT=10mA 50.0 IOUT=100mA 40.0 30.0 VOUT=3.3V L=10uH (LPS4012) Cout=22uF 1 10 Output Current (mA) 100 VOUT=3.3V L=10uH (LPS4012) Cout=22uF 20.0 10.0 500 0.0 4 6 8 G001 Figure 9. Vout=3.3V 10 12 14 16 18 20 Input Voltage (V) 22 24 26 Product Folder Links: TPS62175 TPS62177 G001 Figure 10. Vout=3.3V Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated 28 9 TPS62175, TPS62177 SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com EFFICIENCY vs INPUT VOLTAGE 100.0 100.0 90.0 90.0 80.0 80.0 70.0 60.0 Efficiency (%) Efficiency (%) EFFICIENCY vs OUTPUT CURRENT VIN=24V VIN=12V 50.0 40.0 VIN=7.5 30.0 VOUT=3.3V L=10uH (LPS4012) Cout=22uF VIN=5V 10.0 50.0 0.1 1 Output Current (mA) 0.0 10 20 6 8 10 12 14 16 18 20 Input Voltage (V) 22 24 EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs INPUT VOLTAGE 90.0 80.0 80.0 70.0 70.0 60.0 VIN=12V 50.0 VIN=24V VIN=7.5V 40.0 26 28 G001 Figure 12. Vout=3.3V (Sleep Mode) 100.0 IOUT=500mA 60.0 IOUT=1mA 50.0 IOUT=10mA 40.0 IOUT=100mA 30.0 VIN=5V 10.0 0.1 VOUT=1.8V L=10uH (LPS4012) Cout=22uF 1 10 Output Current (mA) 100 VOUT=1.8V L=10uH (LPS4012) Cout=22uF 20.0 10.0 0.0 500 4 6 8 10 12 G001 14 16 18 20 Input Voltage (V) Figure 13. Vout=1.8V Figure 14. Vout=1.8V EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs INPUT VOLTAGE 100.0 100.0 90.0 90.0 80.0 80.0 70.0 70.0 Efficiency (%) VIN=7.5 60.0 VIN=5V 40.0 VIN=12V VIN=24V 30.0 IOUT=1mA VOUT=1.8V L=10uH (LPS4012) Cout=22uF 10.0 0.01 0.1 1 Output Current (mA) Figure 15. Vout=1.8V (Sleep Mode) 22 24 26 28 G001 VOUT=1.8V L=10uH (LPS4012) Cout=22uF 60.0 50.0 40.0 IOUT=100uA 30.0 20.0 0.0 0.001 4 Figure 11. Vout=3.3V (Sleep Mode) 90.0 50.0 IOUT=1mA IOUT=10uA G001 100.0 0.0 0.01 IOUT=100uA 40.0 10.0 Efficiency (%) Efficiency (%) 0.01 20.0 Efficiency (%) 60.0 20.0 30.0 10 70.0 30.0 20.0 0.0 0.001 VOUT=3.3V L=10uH (LPS4012) Cout=22uF IOUT=10uA 20.0 10.0 10 20 0.0 4 6 8 G001 10 12 14 16 18 20 Input Voltage (V) 22 24 26 28 G001 Figure 16. Vout=1.8V (Sleep Mode) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 TPS62175, TPS62177 www.ti.com SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs INPUT VOLTAGE 100.0 100.0 90.0 80.0 70.0 60.0 VIN=7.5 50.0 40.0 30.0 VOUT=1V L=10uH (LPS4012) Cout=2x22uF VIN=5V 10.0 0.1 1 10 Output Current (mA) 100 IOUT=1mA 40.0 0.0 500 VOUT=1V L=10uH (LPS4012) Cout=2x22uF 4 6 8 12 14 16 18 20 Input Voltage (V) EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs INPUT VOLTAGE 22 24 26 28 G001 100.0 VOUT=1V L=10uH (LPS4012) Cout=22uF 90.0 VIN=24V 80.0 VIN=12V VIN=7.5 50.0 VIN=5V 30.0 IOUT=100uA 70.0 IOUT=1mA 60.0 50.0 40.0 30.0 VOUT=1V L=10uH (LPS4012) Cout=22uF 20.0 10.0 0.01 0.1 1 Output Current (mA) IOUT=10uA 20.0 10.0 0.0 10 20 4 6 8 10 12 G001 14 16 18 20 Input Voltage (V) 22 24 26 28 G001 Figure 19. Vout=1V (Sleep Mode) Figure 20. Vout=1V (Sleep Mode) OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs INPUT VOLTAGE 3.35 3.35 IOUT=1mA Output Voltage (V) VIN=12V Output Voltage (V) 10 Figure 18. Vout=1V 70.0 3.30 VIN=5V VIN=7.5V VIN=24V 3.25 0.1 1 10 Output Current (mA) 100 IOUT=10mA 3.30 IOUT=500mA IOUT=100mA 3.25 VOUT=3.3V L=2.2uH (LPS4012) Cout=22uF VOUT=3.3V L=2.2uH (LPS4012) Cout=22uF 3.20 0.01 IOUT=10mA G001 Efficiency (%) Efficiency (%) 50.0 Figure 17. Vout=1V 80.0 0.0 0.001 60.0 10.0 90.0 40.0 70.0 20.0 100.0 60.0 IOUT=500mA 30.0 20.0 0.0 0.01 IOUT=100mA 80.0 VIN=12V Efficiency (%) Efficiency (%) 90.0 VIN=24V 500 3.20 4 7 G001 Figure 21. Output Voltage Accuracy (Load Regulation) 10 13 16 19 Input Voltage (V) 22 25 28 G001 Figure 22. Output Voltage Accuracy (Line Regulation) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 11 TPS62175, TPS62177 SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com SWITCHING FREQUENCY vs OUTPUT CURRENT SWITCHING FREQUENCY vs INPUT VOLTAGE 1.5 Switching Frequency (MHz) Switching Frequency (MHz) 1.5 1 0.5 VIN=12V, VOUT=3.3V L=10uH (LPS4012) Cout=22uF 0 0 100 200 300 Output Current (mA) 400 1 IOUT=500mA IOUT=10mA 0 500 VOUT=3.3V L=10uH (LPS4012) Cout=22uF 0.5 4 6 8 10 12 G000 14 16 18 20 Input Voltage (V) 22 24 26 28 G000 Figure 23. Switching Frequency Figure 24. Switching Frequency INPUT CURRENT vs INPUT VOLTAGE INPUT CURRENT vs INPUT VOLTAGE 10.0 50.0 45.0 8.0 85°C 35.0 Input Current (µA) Input Current (µA) 40.0 25°C 30.0 25.0 20.0 15.0 10.0 85°C 6.0 4.0 2.0 −40°C −40°C 25°C 5.0 3.0 6.0 0.0 0.0 9.0 12.0 15.0 18.0 21.0 24.0 27.0 30.0 Input Voltage (V) G001 STATIC DRAIN-SOURCE-RESISTANCE (RDSon) vs INPUT VOLTAGE 2000 1800 3.0 85°C 2.5 2.0 1.5 1.0 0.5 −40°C 6.0 25°C 9.0 12.0 15.0 18.0 21.0 24.0 27.0 30.0 Input Voltage (V) G001 1600 85°C 125°C −10°C −40°C 1400 1200 1000 800 600 400 25°C 200 0 0.0 3.0 Figure 27. Shutdown Current 12 9.0 12.0 15.0 18.0 21.0 24.0 27.0 30.0 Input Voltage (V) G001 INPUT CURRENT vs INPUT VOLTAGE 3.5 3.0 6.0 Figure 26. Quiescent Current (Sleep Mode) 4.0 0.0 0.0 3.0 Figure 25. Quiescent Current RDSon High−Side (mΩ) Input Current (µA) 0.0 0.0 Submit Documentation Feedback 6.0 9.0 12.0 15.0 18.0 21.0 24.0 27.0 30.0 Input Voltage (V) G001 Figure 28. High-Side Switch Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 TPS62175, TPS62177 www.ti.com SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 STATIC DRAIN-SOURCE-RESISTANCE (RDSon) vs INPUT VOLTAGE OUTPUT CURRENT vs INPUT VOLTAGE 700 1000 85°C 125°C 800 Output Current (mA) RDSon Low−Side (mΩ) 600 500 400 300 200 600 25°C −40°C 400 VOUT=3.3V L=10uH (LPS4012) Cout=22uF 200 25°C 100 0 0.0 3.0 6.0 −10°C −40°C 9.0 12.0 15.0 18.0 21.0 24.0 27.0 30.0 Input Voltage (V) G001 85°C 0 4 6 8 10 12 14 16 18 20 Input Voltage (V) 22 24 28 G000 Figure 29. Low-Side Switch Figure 30. Maximum Output Current SLEEP MODE ENTRY/EXIT SLEEP MODE ENTRY/EXIT SLEEP OFF SLEEP OFF SLEEP ON 26 SLEEP ON Figure 31. VIN=12V, VOUT=3.3V, Iout=1mA SLEEP ON SLEEP ON Figure 32. VIN=12V, VOUT=3.3V, Iout=10mA Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 13 TPS62175, TPS62177 SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 14 www.ti.com LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE Figure 33. PWM Mode, VIN=12V, VOUT=3.3V, Iout (200mA to 500mA) Figure 34. PWM Mode, VIN=12V, VOUT=3.3V, Iout (200mA to 500mA), rising edge LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE Figure 35. PWM Mode, VIN=12V, VOUT=3.3V, Iout (200mA to 500mA), falling edge Figure 36. Power Save Mode, VIN=12V, VOUT=3.3V, Iout (50mA to 500mA) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 TPS62175, TPS62177 www.ti.com SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE Figure 37. Power Save Mode, VIN=12V, VOUT=3.3V, Iout (50mA to 500mA), rising edge Figure 38. Power Save Mode, VIN=12V, VOUT=3.3V, Iout (50mA to 500mA), falling edge LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE Figure 39. PWM Mode, VIN (6V to 12V), Iout=500mA Figure 40. Power Save Mode, VIN (6V to 12V), Iout=10mA Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 15 TPS62175, TPS62177 SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 16 www.ti.com STARTUP TO VOUT=3.3V STARTUP CURRENT LIMIT Figure 41. PWM Mode, VIN=12V, Iout=250mA Figure 42. Startup Current Limit, VIN=12V, Rload=6.6Ω STARTUP TO VOUT=3.3V OUTPUT VOLTAGE DISCHARGE Figure 43. Sleep Mode, VIN=12V, Iout=10mA Figure 44. Output Discharge Function (Vout=3.3V, no load) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 TPS62175, TPS62177 www.ti.com SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 PWM MODE OPERATION POWER SAVE MODE OPERATION Figure 45. Typical Operation in PWM Mode, VIN=12V, VOUT=3.3V, Iout=250mA Figure 46. Typical Operation in Power Save Mode, VIN=12V, VOUT=3.3V, Iout=75mA POWER SAVE MODE OPERATION SLEEP MODE OPERATION Figure 47. Typical Operation in Power Save Mode, VIN=12V, VOUT=3.3V, Iout=1mA Figure 48. Typical Operation in Sleep Mode, VIN=12V, VOUT=3.3V, Iout=1mA Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 17 TPS62175, TPS62177 SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 18 www.ti.com POWER SAVE MODE OPERATION SLEEP MODE OPERATION Figure 49. Typical Operation in Power Save Mode, VIN=12V, VOUT=3.3V, Iout=1mA (single pulse) Figure 50. Typical Operation in Sleep Mode, VIN=12V, VOUT=3.3V, Iout=1mA (single pulse) SHORT CIRCUIT OPERATION SHORT CIRCUIT OPERATION Figure 51. Short circuit while running, VIN=12V Figure 52. Short circuit from startup, VIN=12V Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 TPS62175, TPS62177 www.ti.com SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 TRIANGULAR LOAD SWEEP TRIANGULAR LOAD SWEEP Figure 53. Triangular Load Sweep with Mode Transitions (Power Save Mode - PWM Mode - Power Save Mode), VIN=12V, VOUT=3.3V Figure 54. Triangular Load Sweep with Mode Transitions (Power Save Mode - PWM Mode - Power Save Mode), VIN=24V, VOUT=3.3V Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 19 TPS62175, TPS62177 SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com DETAILED DESCRIPTION Device Operation The TPS62175/7 synchronous switch mode power converters are based on DCS-Control™ (Direct Control with Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the advantages of hysteretic, voltage mode and current mode control including an AC loop directly associated to the output voltage. This control loop takes information about output voltage changes and feeds it directly to a fast comparator stage. It sets the switching frequency, which is constant for steady state operating conditions, and provides immediate response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves fast and stable operation with small external components and low ESR capacitors. The DCS-ControlTM topology supports PWM (Pulse Width Modulation) mode for medium and heavy load conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in continuous conduction mode. This frequency is typically about 1MHz with a controlled frequency variation depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly with the load current. Since DCS-ControlTM supports both operation modes within one single building block, the transition from PWM to Power Save Mode is seamless without effects on the output voltage. Fixed output voltage versions provide smallest solution size and lowest current consumption, requiring only 3 external components. An internal current limit supports nominal output currents of up to 500mA. The TPS62175/7 offer both excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits. Pulse Width Modulation (PWM) Operation The TPS62175/7 operates with pulse width modulation in continuous conduction mode (CCM) with a nominal switching frequency of about 1MHz. The switching frequency in PWM is set by an internal timer circuit. The frequency variation is controlled and depends on VIN and VOUT. The device operates in PWM mode as long the output current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the device enters Power Save Mode at the boundary to discontinuous conduction mode (DCM). Power Save Mode Operation The TPS62175/7's built in Power Save Mode is entered seamlessly, if the load current decreases. This secures a high efficiency in light load operation by keeping the on-time and reducing the switching frequency. The device remains in Power Save Mode as long as the inductor current is discontinuous. The on-time, in steady-state operation, can be estimated as: spacing tON = VOUT × 1ms VIN (1) spacing While the peak inductor current in Power Save Mode can be approximated by: spacing I LPSM ( peak ) = (V IN - VOUT ) × t ON L (2) spacing The switching frequency is calculated as follows: spacing f PSM = 20 2 × I OUT VIN éVIN - VOUT ù 2 tON úû VOUT êë L (3) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 TPS62175, TPS62177 www.ti.com SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 Sleep Mode Operation In Sleep Mode operation, the typical quiescent current is reduced from 22µA to 4.8µA to significantly increase the efficiency at load currents of typically less than 1mA (see Figure 1). The output voltage is regulated with a fixed on-time, which is adjusted according to VIN. A new pulse is initiated once the output voltage falls below its regulation threshold. Sleep Mode is limited with its dynamic response and current capabilities. It is designed to be enabled and disabled by pulling the SLEEP pin High or Low. As a safety feature, the device returns to normal operation automatically, if too much current is drawn, avoiding a complete collapse of Vout. Once the load current decreases again, the device re-enters Sleep mode operation. However, this is not a recommended operation mode. Ultra low power micro controllers in deep sleep or hibernating mode might have floating output pins. Therefore, TPS62175/7 have a pull-down resistor internally connected to the Sleep pin, to keep a logic low level, when the Sleep input signal goes High Impedance. If the Sleep signal goes directly from logic High to High Impedance, the low level detection must be ensured considering the leakage of the micro controller's Sleep signal. An external pull-down resistor, shown in Figure 62, may be required. The device can deliver temporarily more than 15mA, to allow micro controllers to wake up and drive the Sleep signal High, exiting Sleep Mode. 100% Mode Operation The duty cycle of the buck converter is given by D=Vout/Vin and increases as the input voltage comes close to the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch 100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal setpoint. This allows the conversion of small input to output voltage differences, e.g. for longest operation time of battery-powered applications. The minimum input voltage to maintain output voltage regulation can be calculated as: spacing VIN (min) = VOUT (min) + I OUT (RDS ( on ) + RL ) (4) spacing where IOUT is the output current, RDS(on) is the RDS(on) of the high-side FET and RL is the DC resistance of the inductor used. spacing Enable/Shutdown (EN) The device can be switched on/off by pulling the EN pin to High (operation) or Low (shutdown). If EN is pulled to High, the device starts operation after a delay of about 1ms (typ.). This helps to ensure a monotonic startup sequence, which makes the device ideally suited to control the power on sequence of micro controllers. During Shutdown, the internal MOSFETs as well as the entire control circuitry are turned off and the current consumption is typically 1.5µA. The EN pin is connected via a 400kΩ pull-down resistor, keeping the logic level low, if the pin is floating. Output Discharge The output is actively discharged through a 175Ω (typ.) resistor on the VOS pin when the device is turned off by EN, UVLO or thermal shutdown. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 21 TPS62175, TPS62177 SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com Softstart The internal soft start circuitry controls the output voltage slope during startup. This avoids excessive inrush current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from highimpedance power sources or batteries. When EN is set to High and the device starts switching, VOUT rises with a slope of typically 10mV/µs. The internal current limit is reduced to typically 525mA during startup. Thereby the output current is less than 500mA during hat time (see Figure 42). The startup sequence ends, when device achieves regulation, then, the device runs with the full current limit of typically 1A, providing full output current. The TPS62175/7 can monotonically start into a pre-biased output. Current Limit And Short Circuit Protection The TPS62175/7 devices are protected against heavy load and short circuit events. If a current limit situation is detected, the device switches off. The off time is maintained longer as the output voltage becomes lower. At heavy overloads the low side MOSFET stays on until the inductor current returns to zero. Then the high side MOSFET turns on again (see Figure 51 and Figure 52). Power Good (PG) The TPS62175/7 has a built in power good (PG) function to indicate that the output reached regulation. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an open-drain output that requires a pull-up resistor (to any voltage below 7V). It can sink 2mA of current and maintain its specified logic Low level of 0.3V. It is held Low when the device is turned off by EN, UVLO or thermal shutdown. If the PG pin is not used, it may be left floating or connected to AGND. Under Voltage Lockout (UVLO) If the input voltage drops, the under voltage lockout function prevents misoperation by turning the device off. The under voltage lockout threshold is set to 4.6V (typically) for rising VIN. To cover for possible input voltage drops, when using high impedance sources or batteries, the falling threshold is set to typically 2.9V, allowing monotonic startup sequence under such conditions. For input voltages below the minimum VIN of 4.75V and above the falling UVLO threshold of 2.9V, the device still functions with a current limit and regulation capability but the electrical characteristics are no longer specified. Thermal Shutdown The junction temperature (Tj) of the device is monitored by an internal temperature sensor. If Tj exceeds 150°C (typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG goes Low. When Tj decreases below the hysteresis amount, the converter resumes normal operation, beginning with Soft Start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented on the thermal shutdown temperature. 22 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 TPS62175, TPS62177 www.ti.com SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 APPLICATION INFORMATION Programming The Output Voltage While the output voltage of the TPS62175 is adjustable, the TPS62177 is programmed to a fixed output voltage of 3.3V. For the fixed output voltage version, the FB pin is pulled low internally by a 400kΩ resistor. It is recommended to connect the FB pin to AGND to improve thermal resistance. The adjustable version can be programmed for output voltages from 1V to 6V by using a resistive divider. The voltage at the FB pin is regulated to 800mV. The value of the output voltage is set by the selection of the resistive divider from Equation 5. It is recommended to choose resistor values which allow a current of at least 5uA. Lower resistor values are recommended to increase noise immunity. For applications requiring lowest current consumption, the use of the fixed output voltage version is recommended. spacing æV ö R1 = R 2 çç OUT - 1÷÷ è V REF ø (5) spacing As a safety feature, the device clamps the output voltage at the VOS pin to typically 7.4V, if the FB pin gets opened. External Component Selection The external components have to fulfill the needs of the application, but also the stability criteria of the devices control loop. The TPS62175/7 is optimized to work within a wide range of external components. The LC output filter's inductance and capacitance have to be considered together, while creating a double pole that is responsible for the corner frequency of the converter. Table 1 shows the recommended output filter components. Table 1. Recommended LC Output Filter Combinations (1) 10µF 22µF 47µF 100µF 200µF √ (2) √ √ √ √ √ 400µF 6.8µH 10µH 22µH 33µH (1) (2) The values in the table are nominal values. Variations of typically ±20% due to tolerance, saturation and DC bias are assumed. This LC combination is the standard value and recommended for most applications. For output voltages of ≤2V, an output capacitance of at least 2x22uF is recommended. Output Filter And Loop Stability The TPS62175/7 devices are internally compensated and are stable with LC output filter combinations recommended in Table 1. Further information on other values and loop stability can be found in SLVA543. Inductor Selection The inductor selection is determined by several effects like inductor ripple current, output ripple voltage, PWM-toPower Save Mode transition point and efficiency. In addition, the inductor selected has to be rated for appropriate saturation current and DC resistance (DCR). Equation 6 and Equation 7 calculate the maximum inductor current under static load conditions. spacing I L(max) = I OUT (max) + DI L(max) 2 (6) spacingspacing Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 23 TPS62175, TPS62177 SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 DI L (max) VOUT æ ç1VIN (max) ×h V = OUT × ç h ç L(min) × f SW ç è www.ti.com ö ÷ ÷ ÷ ÷ ø (7) where ΔIL is the Peak to Peak Inductor Ripple Current, η is the converter efficiency (see efficiency figures), L(min) is the minimum inductor value and fSW is the actual PWM Switching Frequency. Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation current of the inductor needed. A margin of about 20% is recommended to cover possible load transient overshoot. A larger inductor value is also useful to get lower ripple current, but increases the transient response time and solution size as well. The following inductors have been tested with the TPS62175/7: Table 2. List of Inductors Type Inductance [µH] Current [A] (1) DCR [mΩ] Dimensions [L x B x H] mm MANUFACTUR ER LPS4012-103MLC 10µH, ±20% 1.1A 350 (max) 4.0 x 4.0 x 1.2 Coilcraft LPS4018-103MLC 10µH, ±20% 1.3A 200 (max) 4.0 x 4.0 x 1.8 Coilcraft TDK VLS4012ET-100M 10µH, ±20% 0.99A 190 (typ) 4.0 x 4.0 x 1.2 VLCF4020T-100MR85 10µH, ±20% 0.85A 168 (typ) 4.0 x 4.0 x 2.0 TDK 74437324100 10µH, ±20% 1.5 A 215 (typ) 4.5 x 4.1 x 1.8 Wuerth IFSC-1515AH-01 10µH, ±20% 1.3A 135 (typ) 3.8 x 3.8 x 1.8 Vishay ELL-4LG100MA 10µH, ±20% 0.8A 200 (typ) 3.8 x 3.8 x 1.8 Panasonic (1) IRMS at 40°C rise or ISAT at 30% drop. Output Capacitor The recommended value for the output capacitor is 22uF. To maintain low output voltage ripple during large load transients, for output voltages below 2V, 2x 22µF is recommended. The architecture of the TPS62175/7 allows the use of ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple and are recommended with an X7R or X5R dielectric. Larger capacitance values have the advantage of smaller output voltage ripple and a tighter DC output accuracy in Power Save Mode. Note: In Power Save Mode, the output voltage ripple and accuracy depends on the output capacitance and the inductor value. The larger the capacitance the lower the output voltage ripple and the better the output voltage accuracy. The same relation applies to the inductor value. Input Capacitor Typically, 2.2µF is sufficient and is recommended, though a larger value reduces input current ripple further. The input capacitor buffers the input voltage during transient events and also decouples the converter from the supply. A low ESR, multilayer, X5R or X7R dielectric, ceramic capacitor is recommended for best filtering and should be placed between VIN and PGND as close as possible to those pins. spacing NOTE DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which has a strong influence on the final effective capacitance. Therefore the right capacitor value has to be chosen carefully. Package size and voltage rating in combination with dielectric material are responsible for differences between the rated capacitor value and the effective capacitance. 24 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 TPS62175, TPS62177 www.ti.com SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 Layout Considerations The input capacitor needs to be placed as close as possible to the IC pins (VIN, PGND). The inductor should be placed close to the SW pin and connect directly to the output capacitor - minimizing the loop area between the SW pin, inductor, output capacitor and PGND pin. Also, sensitive nodes like FB and VOS should be connected with short wires, not nearby high dv/dt signals (e.g. SW). The feedback resistors, R1 and R2, should be placed close to the IC and connect directly to the AGND and FB pins. A proper layout is critical for the operation of a switch mode power supply, even more at high switching frequencies. Therefore the PCB layout of the TPS62175/7 demands careful attention to ensure operation and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability and accuracy weaknesses, increased EMI radiation and noise sensitivity. See Figure 55 for the recommended layout of the TPS62175, which is implemented on the EVM. Information can be found in the EVM Users Guide, SLVU743. Alternatively, the EVM Gerber data are available for download here, SLVC453. VOUT COUT CIN COUT L PGND VIN AGND R2 R1 Figure 55. Layout Example spacingspacing The Exposed Thermal Pad must be soldered to AGND and on the circuit board for mechanical reliability and to achieve appropriate power dissipation. THERMAL INFORMATION The TPS62175/7 is designed for a maximum operating junction temperature (Tj) of 125°C. Therefore the maximum output power is limited by the power losses. Since the thermal resistance of the package is given, the size of the surrounding copper area and a proper thermal connection of the IC can reduce the thermal resistance. To get an improved thermal behavior, it's recommended to use top layer metal to connect the device with wide and thick metal lines (see Figure 55 above). Internal ground layers can connect to vias directly under the IC for improved thermal performance. For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics Application Note (SZZA017), and (SPRA953). Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 25 TPS62175, TPS62177 SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com Typical Applications spacingspacing spacingspacing 10uH 5 to 28V VIN TPS62175 EN 2.2uF 5V/0.5A SW 100k VOS SLEEP 22uF PG 787k AGND FB PGND NC 150k Figure 56. 5V/0.5A Power Supply spacingspacing 10uH 4.75 to 28V VIN TPS62177 EN 2.2uF 3.3V/0.5A SW VOS SLEEP PG AGND FB PGND NC 100k 22uF Figure 57. 3.3V/0.5A Power Supply spacingspacing 10uH 4.75 to 28V VIN TPS62175 EN 2.2uF 2.5V/0.5A SW SLEEP VOS 100k 22uF PG 390k AGND FB PGND NC 110k Figure 58. 2.5V/0.5A Power Supply spacingspacing spacingspacing spacingspacing 26 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 TPS62175, TPS62177 www.ti.com SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 spacingspacing spacingspacing 10uH 4.75 to 28V VIN TPS62175 EN 2.2uF 1.8V/0.5A SW SLEEP 100k VOS 22uF PG 200k AGND FB PGND NC 160k Figure 59. 1.8V/0.5A Power Supply spacingspacing 10uH 4.75 to 28V VIN TPS62175 EN 2.2uF 1.2V/0.5A SW SLEEP 100k VOS 22uF PG 110k AGND FB PGND NC 130k Figure 60. 1.2V/0.5A Power Supply spacingspacing 10uH 4.75 to 28V VIN TPS62175 EN 2.2uF 1V/0.5A SW SLEEP VOS 100k 22uF PG 30k AGND FB PGND NC 120k Figure 61. 1V/0.5A Power Supply Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 27 TPS62175, TPS62177 SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com Application Examples spacingspacing Micro Controller Power Supply The TPS6215/7 can be used advantageously as the power supply rail for micro-controllers with low current power save modes. Figure 62 shows the connection of TPS62177 to the Stellaris Cortex M4 micro-controller (LM4F), using its Hibernate Mode signal to control Sleep Mode operation. spacing decoupling VDD 10uH 4.75 to 28 V VIN EN 2x1uF SW TPS62177 NC 2.2uF 3.3V VOS 100k 4x0.1uF 2x0.01uF VDDA 22uF 1uF PG 0.1uF optional AGND VBAT SLEEP PGND ETP FB HighZ detection HIB Stellaris LM4F Figure 62. Micro-Controller Power Supply with Sleep Mode spacingspacing Inverting Power Supply The TPS62175/7 can be used as inverting power supply by rearranging external circuitry as shown in Figure 63. As the former GND node now represents a voltage level below system ground, the voltage difference between VIN and VOUT has to be limited to the maximum operating voltage of 28V. spacingspacing 2.2uF 10µH VIN VIN SW TPS62175 EN VOS 2.2uF SLEEP PG NC FB 100k R1 22uF R2 AGND -VOUT PGND Figure 63. Inverting Buck-Boost Converter spacingspacing More information about using TPS62175 as inverting buck-boost converter can be found in the Application Note SLVA542. 28 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 TPS62175, TPS62177 www.ti.com SLVSB35A – OCTOBER 2012 – REVISED NOVEMBER 2012 REVISION HISTORY Changes from Original (October 2012) to Revision A Page • Added Startup Mode to High-Side MOSFET Current Limit in ELECTRICAL CHARACTERISTICS .................................... 3 • Changed Table 1 ................................................................................................................................................................ 23 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62175 TPS62177 29 PACKAGE OPTION ADDENDUM www.ti.com 12-Nov-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Samples (3) (Requires Login) TPS62175DQCR ACTIVE WSON DQC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS62175DQCT ACTIVE WSON DQC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS62177DQCR ACTIVE WSON DQC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS62177DQCT ACTIVE WSON DQC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS62175DQCR WSON DQC 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 2.3 3.3 0.85 4.0 12.0 Q1 TPS62175DQCT WSON DQC 10 250 180.0 12.4 2.3 3.3 0.85 4.0 12.0 Q1 TPS62177DQCR WSON DQC 10 3000 330.0 12.4 2.3 3.3 0.85 4.0 12.0 Q1 TPS62177DQCT WSON DQC 10 250 180.0 12.4 2.3 3.3 0.85 4.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS62175DQCR WSON DQC 10 3000 367.0 367.0 35.0 TPS62175DQCT WSON DQC 10 250 210.0 185.0 35.0 TPS62177DQCR WSON DQC 10 3000 367.0 367.0 35.0 TPS62177DQCT WSON DQC 10 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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