CYPRESS CY8C28243_12

CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
PSoC® Programmable System-on-Chip™
PSoC® Programmable System-on-Chip™
Features
■
■
■
■
■
■
Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
❐ Analog input on all GPIOs
❐ 30 mA analog outputs on GPIOs
❐ Configurable interrupt on all GPIOs
❐
Varied resource options within one PSoC® device group
Powerful Harvard-architecture processor
❐ M8C processor speeds up to 24 MHz
❐ 8 × 8 Multiply, 32-bit accumulate
❐ Low power at high speed
❐ Operating voltage: 3.0 V to 5.25 V
❐ Operating voltages down to 1.5 V Using on-chip switched
mode pump (SMP)
❐ Industrial temperature range: –40 °C to +85 °C
Advanced reconfigurable peripherals (PSoC Blocks)
❐ Up to 12 rail-to-rail analog PSoC blocks provide:
• Up to 14-bit ADCs
• Up to 9-bit DACs
• Programmable gain amplifiers
• Programmable filters and comparators
• Multiple ADC configurations
• Dedicated SAR ADC, up to 142 ksps with sample and hold
• Up to 4 synchronized or independent delta-sigma ADCs for
advanced applications
❐ Up to 4 limited type E analog blocks provide:
• Dual channel capacitive sensing capability
• Comparators with programmable DAC reference
• Up to 10-bit single-slope ADCs
❐ Up to 12 digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• Shift register, CRC, and PRS modules
• Up to 3 full-duplex UARTs
• Up to 6 half-duplex UARTs
• Multiple variable data length SPI masters or slaves
• Connectable to all GPIOs
❐ Complex peripherals by combining blocks
■
Additional system resources
2
❐ Up to two hardware I C resources
• Each resource implements slave, master, or multi-master
modes
• Operation between 0 and 400 kHz
❐ Watchdog and Sleep timers
❐ User-configurable low voltage detection
❐ Flexible internal voltage references
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
■
Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full featured in-circuit emulator, and programmer
❐ Full speed emulation
❐ Flexible and functional breakpoint structure
❐ 128 KB trace memory
Logic Block Diagram
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
PSoC
CORE
System Bus
Global Digital Interconnect
SRAM
1K
Global Analog Interconnect
Flash 16K
CPU Core (M8C)
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Clocks
2
MACs
ANALOG SYSTEM
Analog
Block
Array
Digital
Block
Array
Programmable Pin configurations
❐ 25 mA sink, 10 mA drive on all GPIOs
Cypress Semiconductor Corporation
Document Number: 001-48111 Rev. *K
SROM
Interrupt
Controller
Precision, programmable clocking
❐ Internal ±2.5% 24/48 MHz main oscillator
❐ Optional 32.768 kHz crystal for precise on-chip clocks
❐ Optional external oscillator, up to 24 MHz
❐ Internal low speed, low power oscillator for watchdog and
sleep functionality
Flexible on-chip memory
❐ 16 KB flash program storage 50,000 erase/write cycles
❐ 1-KB SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
Analog
Drivers
4 Type 2
2 I2C
Decimators Blocks
POR and LVD
System Resets
Analog
Ref.
Analog
Input
Muxing
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 1, 2012
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Contents
PSoC Functional Overview .............................................. 3
The PSoC Core ........................................................... 3
The Digital System ...................................................... 3
The Analog System ..................................................... 4
System Resources ...................................................... 7
PSoC Device Characteristics ...................................... 7
Getting Started .................................................................. 8
Application Notes ........................................................ 8
Development Kits ........................................................ 8
Training ....................................................................... 8
CYPros Consultants .................................................... 8
Solutions Library .......................................................... 8
Technical Support ....................................................... 8
Development Tools .......................................................... 9
PSoC Designer Software Subsystems ........................ 9
Designing with PSoC Designer ..................................... 10
Select User Modules ................................................. 10
Configure User Modules ............................................ 10
Organize and Connect .............................................. 10
Generate, Verify, and Debug ..................................... 10
Pinouts ............................................................................ 11
20-Pin Part Pinout .................................................... 11
28-Pin Part Pinout ..................................................... 12
44-Pin Part Pinout .................................................... 13
48-Pin Part Pinout ..................................................... 14
56-Pin Part Pinout ..................................................... 15
Register Reference ......................................................... 17
Register Conventions ................................................ 17
Register Mapping Tables .......................................... 17
Document Number: 001-48111 Rev. *K
Electrical Specifications ................................................ 32
Absolute Maximum Ratings ....................................... 33
Operating Temperature ............................................. 33
DC Electrical Characteristics ..................................... 34
AC Electrical Characteristics ..................................... 52
Packaging Information ................................................... 62
Packaging Dimensions .............................................. 62
Thermal Impedances ................................................ 66
Capacitance on Crystal Pins .................................... 66
Solder Reflow Specifications ..................................... 66
Development Tool Selection ......................................... 67
Software .................................................................... 67
Development Kits ...................................................... 67
Evaluation Tools ........................................................ 67
Device Programmers ................................................. 68
Accessories (Emulation and Programming) .............. 68
Ordering Information ...................................................... 69
Ordering Code Definitions ......................................... 70
Acronyms ........................................................................ 71
Acronyms Used ......................................................... 71
Reference Documents .................................................... 71
Document Conventions ................................................. 72
Units of Measure ....................................................... 72
Numeric Conventions ................................................ 72
Glossary .......................................................................... 72
Document History Page ................................................. 77
Sales, Solutions, and Legal Information ...................... 78
Worldwide Sales and Design Support ....................... 78
Products .................................................................... 78
PSoC Solutions ......................................................... 78
Page 2 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
PSoC Functional Overview
The PSoC family consists of many devices with On-Chip
Controllers. These devices are designed to replace multiple
traditional MCU based system components with one low cost
single chip programmable component. A PSoC device includes
configurable analog blocks, digital blocks, and interconnections.
This architecture enables the user to create customized
peripheral configurations to match the requirements of each
individual application. In addition, a fast CPU, Flash program
memory, SRAM data memory, and configurable I/O are included
in a range of convenient pinouts and packages.
32-bit peripherals, which are called user modules. The digital
blocks can be connected to any GPIO through a series of global
buses that can route any signal to any pin.
Figure 1. Digital System Block Diagram[1]
Port 5
Port 1
Port 3
Port 4
Port 0
Port 2
Digital Clocks
From Core
To Analog
System
To System Bus
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
Row 0
DBC00
DBC01
DCC02
4
DCC03
4
Row Output
Configuration
The CY8C28xxx group of PSoC devices described in this
datasheet have multiple resource configuration options
available. Therefore, not every resource mentioned in this
datasheet is available for each CY8C28xxx subgroup. The
CY8C28x45 subgroup has a full feature set of all resources
described. There are six more segmented subgroups that allow
designers to use a device with only the resources and functionality necessary for a specific application. See Table 2 on page 8
to determine the resources available for each CY8C28xxx
subgroup. The same information is also presented in more detail
in the Ordering Information section.
8
8
Row Input
Configuration
DBC10
DBC11
DCC12
4
DCC13
4
Row 2
DBC20
DBC21
DCC22
4
DCC23
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
8
Row Output
Configuration
The architecture for this specific PSoC device family, as shown
in the Logic Block Diagram on page 1, consists of four main
areas: PSoC Core, Digital System, Analog System, and System
Resources. The configurable global bus system allows all the
device resources to be combined into a complete custom
system. PSoC CY8C28xxx family devices have up to six I/O
ports that connect to the global digital and analog interconnects,
providing access to up to 12 digital blocks and up to 16 analog
blocks.
Row 1
Row Output
Configuration
Row Input
Configuration
8
GOE[7:0]
GOO[7:0]
The PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
general Purpose I/O (GPIO). The M8C CPU core is a powerful
processor with speeds up to 24 MHz, providing a four MIPS 8-bit
Harvard architecture microcontroller.
Memory encompasses 16K bytes of Flash for program storage,
1K bytes of SRAM for data storage. The PSoC device incorporates flexible internal clock generators, including a 24 MHz
internal main oscillator (IMO) accurate to 2.5% over temperature
and voltage. A low power 32 kHz internal low speed oscillator
(ILO) is provided for the sleep timer and watch dog timer (WDT).
The 32.768 kHz external crystal oscillator (ECO) is available for
use as a real time clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL.
PSoC GPIOs provide connections to the CPU, and digital and
analog resources. Each pin’s drive mode may be selected from
8 options, which allows great flexibility in external interfacing.
Every pin also has the capability to generate a system interrupt
on high level, low level, and change from last read.
The Digital System
The Digital System is composed of up to 12 configurable digital
PSoC blocks. Each block is an 8-bit resource that can be used
alone or combined with other blocks to create 8, 16, 24, and
Digital peripheral configurations include:
■
PWMs (8- and 16-bit, One-shot and Multi-shot capability)
■
PWMs with Dead band/Kill (8- and 16-bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
Full-duplex 8-bit UARTs (up to 3) with selectable parity
■
Half-duplex 8-bit UARTs (up to 6) with selectable parity
■
Variable length SPI slave and master
❐ Up to 6 total slaves and masters (8-bit)
❐ Supports 8 to 16 bit operation
■
I2C slave, master, or multi-master (up to 2 available as System
Resources)
■
IrDA (up to 3)
■
Pseudo Random Sequence Generators (8 to 32 bit)
■
Cyclical Redundancy Checker/Generator (16 bit)
■
Shift Register (2 to 32 bit)
Note
1. CY8C28x52 devices do not have digital block row 2. They have two digital rows with eight total digital blocks.
Document Number: 001-48111 Rev. *K
Page 3 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Some of the more common PSoC analog functions (most
available as user modules) are:
■
Analog-to-digital converters (6 to 14-bit resolution, up to 4,
selectable as Incremental or Delta Sigma)
All GPIO
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
The Analog System is composed of up to 16 configurable analog
blocks, each containing an opamp circuit that allows the creation
of complex analog signal flows. Some devices in this PSoC
family have an analog multiplex bus that can connect to every
GPIO pin. This bus can also connect to the analog system for
analysis with comparators and analog-to-digital converters. It
can be split into two sections for simultaneous dual-channel
processing.
Figure 2. Analog System Block Diagram for CY8C28x45 and
CY8C28x52 Devices
P2[3]
Analog Mux
Bus
The Analog System
P2[1]
P2[6]
P2[4]
P2[2]
■
Dedicated 10-bit SAR ADC with sample rates up to 142 ksps
■
Synchronized, simultaneous Delta Sigma ADCs (up to 4)
■
Filters (2 to 8 pole band-pass, low pass, and notch)
■
Amplifiers (up to 4, with selectable gain to 48x)
■
Instrumentation amplifiers (up to 2, with selectable gain to 93x)
■
Comparators (up to 6, with 16 selectable thresholds)
■
DACs (up to 4, with 6 to 9-bit resolution)
■
Multiplying DACs (up to 4, with 6 to 9-bit resolution)
ACC00
ACC01
ACC02
ACC03
■
High current output drivers (up to 4 with 30 mA drive)
ASC10
ASD11
ASC12
ASD13
■
1.3 V reference (as a System Resource)
ASD20
ASC21
ASD22
ASC23
■
DTMF Dialer
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
ACI4[1:0]
ACI5[1:0]
Block Array
ACE00
ACE01
ASE10
ASE11
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-48111 Rev. *K
Page 4 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Figure 3. Analog System Block Diagram for CY8C28x43
Devices
Figure 4. Analog System Block Diagram for CY8C28x33
Devices
All GPIO
All GPIO
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
P0[7]
P0[5]
P2[1]
P0[4]
P0[1]
P0[2]
P2[3]
P2[1]
P2[4]
P0[0]
AGNDIn RefIn
Analog Mux
Bus
P2[3]
P2[6]
P0[3]
Analog Mux
Bus
AGNDIn RefIn
P0[6]
P2[2]
P2[0]
P2[6]
P2[4]
Array Input Configuration
Array Input Configuration
ACI0[1:0]
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI1[1:0]
ACI4[1:0]
ACI5[1:0]
ACI3[1:0]
Block Array
ACC00
ACC01
Block Array
ACC00
ACC01
ACC02
ACC03
ASC10
ASD11
ASC10
ASD11
ASC12
ASD13
ASD20
ASC21
ASD20
ASC21
ASD22
ASC23
ACE00
ACE01
ASE10
ASE11
Analog Reference
Interface to
Digital System
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-48111 Rev. *K
Page 5 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Figure 5. Analog System Block Diagram for CY8C28x23
Devices
Figure 6. Analog System Block Diagram for CY8C28x13
Devices
P0[7]
All GPIO
P0[5]
P0[6]
P0[4]
P0[1]
P0[6]
Analog Mux
Bus
P0[7]
P0[3]
P0[5]
P0[4]
P0[2]
P2[3]
P0[0]
AGNDIn RefIn
P2[1]
P0[3]
P0[2]
P0[1]
P0[0]
P2[6]
Array Input
Configuration
P2[4]
ACI0[1:0]
ACI1[1:0]
Array Input
Configuration
ACI0[1:0]
Block Array
ACI1[1:0]
Block Array
ACC00
ACC01
ASC10
ASD11
ASD20
ASC21
RefHi
RefLo
AGND
Reference
Generators
ACE01
ASE10
ASE11
Analog Reference
Interface to
Digital System
Analog Reference
Interface to
Digital System
ACE00
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-48111 Rev. *K
Page 6 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
System Resources
■
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a multiplier, multiple
decimators, switch mode pump, low voltage detection, and
power on reset. Statements describing the merits of each system
resource follow:
■
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
Multiply accumulate (MAC) provides fast 8-bit multiplier with
32-bit accumulate, to assist in general math and digital filters.
Up to four decimators provide custom hardware filters for digital
signal processing applications such as Delta-Sigma ADCs and
CapSense capacitive sensor measurement.
Up to two I2C resources provide 0 to 400 kHz communication
over two wires. Slave, master, and multi-master modes are all
supported. I2C resources have hardware address detection
capability.
■
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.3 V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.5 V battery cell, providing a
low cost boost converter.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or 4
analog blocks. Table 1 on page 7 lists the resources available for specific PSoC device groups. The PSoC device covered by this
datasheet is highlighted in this table.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
CY8C29x66
up to 64
4
16
up to 12
4
4
12
2K
32 K
CY8C28xxx
up to 44
up to 3
up to 12
up to 44
up to 4
up to 6
up to
12 + 4[2]
1K
16 K
CY8C27x43
up to 44
2
8
up to 12
4
4
12
256
16 K
CY8C24x94
up to 56
1
4
up to 48
2
2
6
1K
16 K
CY8C24x23A
up to 24
1
4
up to 12
2
2
6
256
4K
CY8C23x33
up to 26
1
4
up to 12
2
2
4
256
8K
CY8C22x45
up to 38
2
8
up to 38
0
4
6[2]
1K
16 K
CY8C21x45
up to 24
1
4
up to 24
0
4
6[2]
512
8K
CY8C21x34
up to 28
1
4
up to 28
0
2
4[2]
512
8K
[2]
256
4K
512
8K
up to 2 K
up to 32 K
CY8C21x23
up to 16
1
4
up to 8
0
2
CY8C20x34
up to 28
0
0
up to 28
0
0
3[2,3]
0
[2,3]
CY8C20xx6
up to 36
0
0
up to 36
0
4
3
Notes
2. Limited analog functionality.
3. Two analog blocks and one CapSense®.
Document Number: 001-48111 Rev. *K
Page 7 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
The devices covered by this datasheet all have the same architecture, specifications, and ratings. However, the amount of some
hardware resources varies from device to device within the group. The following table lists resources available for the specific device
subgroups covered by this datasheet.
Table 2. CY8C28xxx Device Characteristics
CapSense
Digital
Blocks
Regular
Analog
Blocks
Limited
Analog
Blocks
HW I2C
Decimators
Digital
I/O
CY8C28x03
N
12
0
0
2
0
up to 24
up to 8
0
CY8C28x13
Y
12
0
4
1
2
up to 40
up to 40
0
CY8C28x23
N
12
6
0
2
2
up to 44
up to 10
2
CY8C28x33
Y
12
6
4
1
4
up to 40
up to 40
2
CY8C28x43
N
12
12
0
2
4
up to 44
up to 44
4
CY8C28x45
Y
12
12
4
2
4
up to 44
up to 44
4
CY8C28x52
Y
8
12
4
1
4
up to 24
up to 24
4
PSoC Part
Number
Getting Started
For in depth information, along with detailed programming
details, see the PSoC® Technical Reference Manual.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web.
Application Notes
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
Analog
Inputs
Analog
Outputs
covers a wide variety of topics and skill levels to assist you in
your designs.
CYPros Consultants
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the CYPros Consultants web site.
Solutions Library
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Notes
4. Has 12 regular analog blocks and four limited Type-E analog blocks.
5. Limited analog functionality.
6. Two analog blocks and one CapSense.
Document Number: 001-48111 Rev. *K
Page 8 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
■
Integrated source-code editor (C and assembly)
■
Free C compiler with no size restrictions or time limits
■
Built-in debugger
■
In-circuit emulation
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full-speed USB 2.0
❐ Up to four full-duplex universal asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
■
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this lets you to use more than 100 percent of
PSoC's resources for an application.
Document Number: 001-48111 Rev. *K
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also lets you to create a trace buffer of registers and memory
locations of interest.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an Online Support
Forum to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
Page 9 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed-function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and lowering inventory costs. These
configurable resources, called PSoC blocks, have the ability to
implement a wide variety of user-selectable functions. The PSoC
development process is:
1. Select user modules.
2. Configure user modules.
3. Organize and connect.
4. Generate, verify, and debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a PWM
User Module configures one or more digital PSoC blocks, one
for each eight bits of resolution. Using these parameters, you can
establish the pulse width and duty cycle. Configure the
parameters and properties to correspond to your chosen
application. Enter values directly or by selecting values from
drop-down menus. All of the user modules are documented in
datasheets that may be viewed directly in PSoC Designer or on
the Cypress website. These user module datasheets explain the
internal operation of the user module and provide performance
specifications. Each datasheet describes the use of each user
module parameter, and other information that you may need to
successfully implement your design.
Document Number: 001-48111 Rev. *K
Organize and Connect
Build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. Perform the selection,
configuration, and routing so that you have complete control over
all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides APIs with high-level functions to control
and respond to hardware events at run time, and interrupt
service routines that you can adapt as needed.
A complete code development environment lets you to develop
and customize your applications in C, assembly language, or
both.
The last step in the development process takes place inside
PSoC Designer's Debugger (accessed by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full-speed. PSoC Designer debugging
capabilities rival those of systems costing many times more. In
addition to traditional single-step, run-to-breakpoint, and
watch-variable features, the debug interface provides a large
trace buffer. It lets you to define complex breakpoint events that
include monitoring address and data bus values, memory
locations, and external signals.
Page 10 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Pinouts
This section describes, lists, and illustrates the CY8C28xxx PSoC device pins and pinout configurations.
The CY8C28xxx PSoC devices are available in a variety of packages which are listed and illustrated in the following tables. Every
port pin (labeled with a “P”) is capable of Digital I/O. However, VSS, VDD, SMP, and XRES are not capable of Digital I/O.
20-Pin Part Pinout
Table 3. 20-Pin Part Pinout (SSOP)
Type
Pin
No.
Digital
Analog
Pin
Name
1
I/O
I, M, S
P0[7]
2
I/O
I/O, M, S
P0[5]
3
I/O
I/O, M, S
P0[3]
4
I/O
I, M, S
P0[1]
5
Output
SMP
Description
Analog column mux and SAR ADC
input.[8]
S, AI, M, P0[7]
S, AIO, M, P0[5]
Analog column mux and SAR ADC input.
S, AIO, M, P0[3]
Analog column output.[8, 9]
S, AI, M, P0[1]
Analog column mux and SAR ADC input.
SMP
[8,
9]
Analog column output.
I2C0 SCL, M, P1[7]
Analog column mux and SAR ADC
I2C0 SDA, M, P1[5]
input.[8]
M, P1[3]
Switch Mode Pump (SMP) connection to I2C0 SCL, XTALin, M, P1[1]
external components.
Vss
6
I/O
M
P1[7]
I2C0 Serial Clock (SCL).
7
I/O
M
P1[5]
I2C0 Serial Data (SDA).
8
I/O
M
P1[3]
9
I/O
M
P1[1]
10
Power
VSS
M
P1[0]
Crystal Output (XTALout), I2C0 Serial
Data (SDA), ISSP-SDATA[7].
12
I/O
M
P1[2]
I2C1 Serial Data (SDA).[10]
13
I/O
M
P1[4]
Optional External Clock Input (EXTCLK).
14
I/O
M
P1[6]
I2C1 Serial Clock (SCL).[10]
I/O
I, M, S
P0[0]
Analog column mux and SAR ADC
input.[8]
17
I/O
I/O, M, S
P0[2]
Analog column mux and SAR ADC input.
Analog column output.[8, 11]
18
I/O
I/O, M, S
P0[4]
Analog column mux and SAR ADC input.
Analog column output.[8, 11]
19
I/O
I, M, S
P0[6]
Analog column mux and SAR ADC
input.[8]
VDD
Supply voltage.
Power
Vdd
P0[6], M, AI, S
P0[4], M, AIO, S
P0[2], M, AIO, S
P0[0], M, AI, S
XRES
P1[6], M, I2C1 SCL
P1[4], M, EXTCLK
P1[2], M, I2C1 SDA
P1[0], M, XTALout, I2C0 SDA
XRES Active high external reset with internal
pull-down.
16
20
SSOP
20
19
18
17
16
15
14
13
12
11
Ground connection.
I/O
Input
1
2
3
4
5
6
7
8
9
10
Crystal Input (XTALin), I2C0 Serial Clock
(SCL), ISSP-SCLK[7].
11
15
CY8C28243 20-Pin PSoC Device
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input.
Notes
7. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Technical Reference Manual for CY8C28xxx PSoC devices for details.
8. CY8C28x52 and CY8C28x23 devices do not have a SAR ADC. Therefore, this pin does not function as a SAR ADC input for these devices.
9. CY8C28x13 and CY8C28x03 devices do not have any analog output buffers. Therefore, this pin does not function as an analog column output for these devices.
10. CY8C28x52, CY8C28x13, and CY8C28x33 devices only have one I2C block. Therefore, this GPIO does not function as an I2C pin for these devices.
11. CY8C28x33, CY8C28x23, CY8C28x13, and CY8C28x03 devices do not have an analog output buffer for this pin. Therefore, this pin does not function as an analog
column output for these devices.
Document Number: 001-48111 Rev. *K
Page 11 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
28-Pin Part Pinout
Table 4. 28-Pin Part Pinout (SSOP)
Type
Description
Pin
No.
Digital
Analog
Pin
Name
1
I/O
I, M, S
P0[7]
Analog column mux and SAR ADC
input.[8]
2
I/O
I/O, M, S
P0[5]
Analog column mux and SAR ADC input.
Analog column output.[8, 9]
3
I/O
I/O, M, S
P0[3]
Analog column mux and SAR ADC input.
Analog column output.[8, 9]
4
I/O
I, M, S
P0[1]
Analog column mux and SAR ADC
input.[8]
5
I/O
M
P2[7]
6
I/O
M
P2[5]
7
I/O
I, M
P2[3]
Direct switched capacitor block input.[12]
8
I/O
I, M
P2[1]
Direct switched capacitor block input.[12]
SMP
Switch Mode Pump (SMP) connection to
external components.
9
Output
10
I/O
M
P1[7]
I2C0 Serial Clock (SCL).
11
I/O
M
P1[5]
I2C0 Serial Data (SDA).
12
I/O
M
P1[3]
13
I/O
M
P1[1]
14
Power
VSS
M
P1[0]
Crystal Output (XTALout), I2C0 Serial
Data (SDA), ISSP-SDATA[7].
16
I/O
M
P1[2]
I2C1 Serial Data (SDA).[10]
17
I/O
M
P1[4]
Optional External Clock Input (EXTCLK).
18
I/O
M
P1[6]
I2C1 Serial Clock (SCL).[10]
I/O
I, M
P2[0]
Direct switched capacitor block input.[13]
21
I/O
I, M
P2[2]
Direct switched capacitor block input.[13]
22
I/O
M
P2[4]
External Analog Ground (AGND).
23
I/O
M
P2[6]
External Voltage Reference (VRef).
24
I/O
I, M, S
P0[0]
Analog column mux and SAR ADC
input.[8]
25
I/O
I/O, M, S
P0[2]
Analog column mux and SAR ADC input.
Analog column output.[8, 11]
26
I/O
I/O, M, S
P0[4]
Analog column mux and SAR ADC input.
Analog column output.[8, 11]
27
I/O
I, M, S
P0[6]
Analog column mux and SAR ADC
input.[8]
VDD
Supply voltage.
Power
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], M, AI, S
P0[4], M, AIO, S
P0[2], M, AIO, S
P0[0], M, AI, S
P2[6], M, External VRef
P2[4], M, External AGND
P2[2], M, AI
P2[0], M, AI
XRES
P1[6], M, I2C1 SCL
P1[4], M, EXTCLK
P1[2], M, I2C1 SDA
P1[0], M, XTALout, I2C0 SDA
XRES Active high external reset with internal
pull-down.
20
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Ground connection.
I/O
Input
S, AI, M, P0[7]
S, AIO, M, P0[5]
S, AIO, M, P0[3]
S, AI, M, P0[1]
M, P2[7]
M, P2[5]
AI, M, P2[3]
AI, M, P2[1]
SMP
I2C0 SCL, M, P1[7]
I2C0 SDA, M, P1[5]
M, P1[3]
I2C0 SCL, XTALin, M, P1[1]
Vss
Crystal Input (XTALin), I2C0 Serial Clock
(SCL), ISSP-SCLK[7].
15
19
CY8C28403, CY8C28413, CY8C28433, CY8C28445, and
CY8C28452 28-Pin PSoC Devices
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input
Notes
12. This pin is not a direct switched capacitor block analog input for CY8C28x03 and CY8C28x13 devices.
13. This pin is not a direct switched capacitor block analog input for CY8C28x03, CY8C28x13, CY8C28x23, and CY8C28x33 devices.
Document Number: 001-48111 Rev. *K
Page 12 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
44-Pin Part Pinout
Table 5. 44-Pin Part Pinout (TQFP)
9
10
11
12
13
14
15
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
17
18
M
M
M
M
M
M
M
M
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
P1[3]
P1[1]
I/O
M
VSS
P1[0]
19
20
21
22
23
24
25
26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
M
27
28
29
30
31
32
33
34
35
36
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
I, M
I, M
M
M
I, M, S
I/O, M S
P4[0]
P4[2]
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
37
I/O
I/O, M, S
P0[4]
38
39
40
41
I/O
I, M, S
Power
I/O
I, M, S
I/O
I/O, M, S
P0[6]
VDD
P0[7]
P0[5]
42
I/O
P0[3]
Power
Input
I/O, M, S
P1[2]
P1[4]
P1[6]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
P2[7], M
P0[1], M, AI, S
P0[3], M, AIO, S
P0[5], M, AIO, S
P0[7], M, AI, S
Vdd
P0[6], M, AI, S
P0[4], M, AIO, S
P0[2], M, AIO, S
P0[0], M, AI, S
P2[6], M, External VRef
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
CY8C28513, CY8C28533, and CY8C28545
44-Pin PSoC Devices
Description
Direct switched capacitor block input.[12]
Direct switched capacitor block input.[12]
Switch Mode Pump (SMP) connection to
external components.
I2C0 Serial Clock (SCL).
I2C0 Serial Data (SDA).
Crystal Input (XTALin), I2C0 Serial Clock
(SCL), ISSP-SCLK[7].
Ground connection.
Crystal Output (XTALout), I2C0 Serial Data
(SDA), ISSP-SDATA[7].
I2C1 Serial Data (SDA).[10]
Optional External Clock Input (EXTCLK).
I2C1 Serial Clock (SCL).[10]
I2C1 Serial Data (SDA).[10]
I2C1 Serial Clock (SCL).[10]
M, P2[5]
AI, M, P2[3]
AI, M, P2[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
SMP
M, P3[7]
M, P3[5]
M, P3[3]
44
43
42
41
40
39
38
37
36
35
34
Pin
Name
1
2
3
4
5
6
7
8
9
10
11
TQFP
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
Type
Digital Analog
I/O
M
I/O
I, M
I/O
I, M
I/O
M
I/O
M
I/O
M
I/O
M
Output
P2[4], M, External AGND
P2[2], M, AI
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
P3[6], M
P3[4], M
P3[2], M, I2C1 SCL
M, P3[1]
I2C0 SCL, M, P1[7]
I2C0 SDA, M, P1[5]
M, P1[3]
I2C0 SCL, XTALin, M, P1[1]
Vss
I2C0 SDA, XTALout, M, P1[0]
I2C1 SDA, M, P1[2]
EXTCLK, M, P1[4]
I2C1 SCL, M, P1[6]
I2C1 SDA, M, P3[0]
Pin
No.
Active high external reset with internal
pull-down.
Direct switched capacitor block input.[13]
Direct switched capacitor block input.[13]
External Analog Ground (AGND).
External Voltage Reference (VRef).
Analog column mux and SAR ADC input.[8]
Analog column mux and SAR ADC input.
Analog column output.[8, 11]
Analog column mux and SAR ADC input.
Analog column output.[8, 11]
Analog column mux and SAR ADC input.[8]
Supply voltage.
Analog column mux and SAR ADC input.[8]
Analog column mux and SAR ADC input.
Analog column output.[8, 9]
Analog column mux and SAR ADC input.
Analog column output.[8, 9]
Analog column mux and SAR ADC input.[8]
43
I/O
I, M, S
P0[1]
44
I/O
P2[7]
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input.
Document Number: 001-48111 Rev. *K
Page 13 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
48-Pin Part Pinout
Table 6. 48-Pin Part Pinout (QFN[14])
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
18
19
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
Direct switched capacitor block input.[12]
Direct switched capacitor block input.[12]
Switch Mode Pump (SMP) connection to
external components.
CY8C28623, CY8C28643, and CY8C28645
48-Pin PSoC Devices
P2[5], M
P2[7], M
P0[1], M, AI, S
P0[3], M, AIO, S
P0[5], M, AIO, S
P0[7], M, AI, S
Vdd
P0[6], M, AI, S
P0[4], M, AIO, S
P0[2], M, AIO, S
P0[0], M, AI, S
P2[6], M, External VRef
Description
AI, M, P2[3]
AI, M, P2[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
SMP
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[3]
M
M
M
M
M
M
M
M
M
M
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
I/O
M
VSS
P1[0]
20
21
I/O
I/O
M
M
P1[2]
P1[4]
22
23
24
25
26
27
28
29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
M
30
31
32
I/O
I/O
I/O
M
M
M
P1[6]
P5[0]
P5[2]
P3[0] I2C1 Serial Data (SDA).[10]
P3[2] I2C1 Serial Clock (SCL).[10]
P3[4]
P3[6]
XRES Active high external reset with internal
pull-down.
P4[0]
P4[2]
P4[4]
Pin
No.
33
I/O
M
P4[6]
41
34
35
I/O
I/O
I, M
I, M
P2[0]
P2[2]
Direct switched capacitor block input.[13]
Direct switched capacitor block input.[13]
42
43
36
I/O
M
P2[4]
External Analog Ground (AGND).
44
37
I/O
M
P2[6]
External Voltage Reference (VRef).
45
38
I/O
I, M, S
P0[0]
Power
Input
I2C0 Serial Clock (SCL).
I2C0 Serial Data (SDA).
Crystal Input (XTALin), I2C0 Serial Clock
(SCL), ISSP-SCLK[7].
Ground connection.
Crystal Output (XTALout), I2C0 Serial
Data (SDA), ISSP-SDATA[7].
I2C1 Serial Data (SDA).[10]
Optional External Clock Input
(EXTCLK).
I2C1 Serial Clock (SCL).[10]
1
2
3
4
5
6
7
8
9
10
11
12
QFN
(Top View)
36
35
34
33
32
31
30
29
28
27
26
25
P2[4], M, External AGND
P2[2], M, AI
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
P3[6], M
P3[4], M
P3[2], M, I2C1 SCL
P3[0], M, I2C1 SDA
M, P5[1]
I2C0 SCL, M, P1[7]
I2C0 SDA, M, P1[5]
M, P1[3]
I2C0 SCL, XTALin, M, P1[1]
Vss
I2C0 SDA, XTALout, M, P1[0]
I2C1 SDA, M, P1[2]
EXTCLK, M, P1[4]
I2C1 SCL, M, P1[6]
M, P5[0]
M, P5[2]
8
9
10
11
12
13
14
15
16
17
Pin
Name
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
Type
Digital Analog
I/O
I, M
I/O
I, M
I/O
M
I/O
M
I/O
M
I/O
M
Output
13
14
15
16
17
18
19
20
21
22
23
24
Pin
No.
Type
Pin
Nam
Description
e
I/O
I, M, S P0[6] Analog column mux and SAR ADC
input.[8]
Power
VDD Supply voltage.
I/O
I, M, S P0[7] Analog column mux and SAR ADC
input.[8]
I/O
I/O, M, S P0[5] Analog column mux and SAR ADC
input. Analog column output.[8, 9]
I/O
I/O, M, S P0[3] Analog column mux and SAR ADC
input. Analog column output.[8, 9]
I/O
I, M, S P0[1] Analog column mux and SAR ADC
input.[8]
I/O
M
P2[7]
Digital
Analog
Analog column mux and SAR ADC
46
input.[8]
39
I/O
I/O, M, S P0[2] Analog column mux and SAR ADC input.
47
Analog column output.[8, 11]
40
I/O
I/O, M, S P0[4] Analog column mux and SAR ADC input.
48
I/O
M
Analog column output.[8, 11]
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input.
P2[5]
Note
14. The QFN package has a center pad that must be connected to ground (VSS)
Document Number: 001-48111 Rev. *K
Page 14 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
56-Pin Part Pinout
The 56-pin SSOP part is for the CY8C28000 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Table 7. 56-Pin Part Pinout (SSOP)
Pin
No.
Type
Digital
Analog
Pin
Name
2
I/O
I, M, S
P0[7]
Analog column mux and SAR ADC input.
3
I/O
I/O, M, S
P0[5]
Analog column mux and SAR ADC input.
Analog column output.
4
I/O
I/O, M, S
P0[3]
Analog column mux and SAR ADC input.
Analog column output.
5
I/O
I, M, S
P0[1]
Analog column mux and SAR ADC input.
6
I/O
M
P2[7]
7
I/O
M
P2[5]
8
I/O
I
P2[3]
Direct switched capacitor block input.
Direct switched capacitor block input.
1
NC
9
I/O
I
P2[1]
10
I/O
M
P4[7]
Description
No connection.
11
I/O
M
P4[5]
12
I/O
I, M
P4[3]
13
I/O
I, M
14
OCD
M
OCDE OCD even data I/O.
15
OCD
M
OCDO OCD odd data output.
16
Output
P4[1]
SMP
Switch Mode Pump (SMP) connection to
required external components.
17
I/O
M
P3[7]
18
I/O
M
P3[5]
19
I/O
M
P3[3]
20
I/O
M
P3[1]
21
I/O
M
P5[3]
22
I/O
M
P5[1]
23
I/O
M
P1[7]
I2C0 Serial Clock (SCL).
24
I/O
M
P1[5]
I2C0 Serial Data (SDA).
25
NC
I/O
M
P1[3]
27
I/O
M
P1[1]
Crystal Input (XTALin), I2C0 Serial Clock
(SCL), ISSP-SCLK[7].
VSS
Ground connection.
Power
NC
S, AI, M, P0[7]
S, AIO, M, P0[5]
S, AIO, M, P0[3]
S, AI, M, P0[1]
M, P2[7]
M, P2[5]
AI, M, P2[3]
AI, M, P2[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
OCDE
OCDO
SMP
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[3]
M, P5[1]
I2C0 SCL, M, P1[7]
I2C0 SDA, M, P1[5]
NC
M, P1[3]
SCLK, I2C0 SCL, XTALIn, M, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SSOP
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Vdd
P0[6], M, AI, S
P0[4], M, AIO, S
P0[2], M, AIO, S
P0[0], M, AI, S
P2[6], M, External VRef
P2[4], M, External AGND
P2[2], M, AI
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
CCLK
HCLK
XRES
P3[6], M
P3[4], M
P3[2], M, I2C1 SCL
P3[0], M, I2C1 SDA
P5[2], M
P5[0], M
P1[6], M, I2C1 SCL
P1[4], M, EXTCLK
P1[2], M, I2C1 SDA
P1[0], M, XTALOut, I2C0 SDA, SDATA
NC
NC
Not for Production
No connection.
26
28
CY8C28000 56-Pin PSoC Device
29
NC
No connection.
30
NC
No connection.
31
I/O
M
P1[0]
Crystal Output (XTALout), I2C0 Serial
Data (SDA), ISSP-SDATA[7].
32
I/O
M
P1[2]
I2C1 Serial Data (SDA).
33
I/O
M
P1[4]
Optional External Clock Input (EXTCLK).
34
I/O
M
P1[6]
I2C1 Serial Clock (SCL).
35
I/O
M
P5[0]
36
I/O
M
P5[2]
37
I/O
M
P3[0]
I2C1 Serial Data (SDA).
38
I/O
M
P3[2]
I2C1 Serial Clock (SCL).
39
I/O
M
P3[4]
40
I/O
M
P3[6]
Document Number: 001-48111 Rev. *K
Page 15 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 7. 56-Pin Part Pinout (SSOP) (continued)
Pin
No.
Type
Digital
41
Analog
Input
Pin
Name
Description
XRES Active high external reset with internal
pull-down.
42
OCD
M
HCLK OCD high speed clock output.
43
OCD
M
CCLK OCD CPU clock output.
44
I/O
M
P4[0]
45
I/O
M
P4[2]
46
I/O
M
P4[4]
47
I/O
M
P4[6]
48
I/O
I, M
P2[0]
Direct switched capacitor block input.
49
I/O
I, M
P2[2]
Direct switched capacitor block input.
50
I/O
M
P2[4]
External Analog Ground (AGND).
51
I/O
M
P2[6]
External Voltage Reference (VRef).
52
I/O
I, M, S
P0[0]
Analog column mux and SAR ADC input.
53
I/O
I/O, M, S
P0[2]
Analog column mux and SAR ADC input.
Analog column output.
54
I/O
I/O, M, S
P0[4]
Analog column mux and SAR ADC input.
Analog column output.
55
I/O
I, M, S
P0[6]
Analog column mux and SAR ADC input.
VDD
Supply voltage.
56
Power
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, M = Analog Mux Bus Input, and OCD = On-Chip Debug.
Document Number: 001-48111 Rev. *K
Page 16 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Register Reference
This section lists the registers of the CY8C28xxx PSoC devices. For detailed register information, reference the
PSoC Technical Reference Manual for CY8C28xxx PSoC devices.
Register Conventions
Register Mapping Tables
The register conventions specific to this section are listed in the
following table.
CY8C28xxx PSoC devices have a total register address space
of 512 bytes. The register space is referred to as I/O space and
is divided into two banks. The XIO bit in the Flag register
(CPU_F) determines which bank of registers CPU instructions
access. When the XIO bit is set the registers in Bank 1 are
accessed by CPU instructions. When the XIO bit is cleared the
registers in Bank 0 are accessed by CPU instructions.
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 001-48111 Rev. *K
Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
Page 17 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 8. CY8C28x03 Register Map Bank 0 Table: User Space
Name
PRT0DR
Addr (0,Hex)
00
Access
RW
Name
DBC20DR0
Addr (0,Hex)
40
Access
#
Name
Addr (0,Hex)
80
PRT0IE
01
RW
DBC20DR1
41
W
81
PRT0GS
02
RW
DBC20DR2
42
RW
82
PRT0DM2
03
RW
DBC20CR0
43
#
PRT1DR
04
RW
DBC21DR0
44
PRT1IE
05
RW
DBC21DR1
PRT1GS
06
RW
PRT1DM2
07
PRT2DR
Access
Name
RDI2RI
Addr (0,Hex)
C0
Access
RW
RDI2SYN
C1
RW
RDI2IS
C2
RW
83
RDI2LT0
C3
RW
#
84
RDI2LT1
C4
RW
45
W
85
RDI2RO0
C5
RW
DBC21DR2
46
RW
86
RDI2RO1
C6
RW
RW
DBC21CR0
47
#
87
RDI2DSM
C7
RW
08
RW
DCC22DR0
48
#
88
PRT2IE
09
RW
DCC22DR1
49
W
89
C9
PRT2GS
0A
RW
DCC22DR2
4A
RW
8A
CA
C8
PRT2DM2
0B
RW
DCC22CR0
4B
#
8B
CB
PRT3DR
0C
RW
DCC23DR0
4C
#
8C
CC
PRT3IE
0D
RW
DCC23DR1
4D
W
8D
CD
PRT3GS
0E
RW
DCC23DR2
4E
RW
8E
CE
PRT3DM2
0F
RW
DCC23CR0
4F
#
8F
PRT4DR
10
RW
50
90
CUR_PP
D0
RW
PRT4IE
11
RW
51
91
STK_PP
D1
RW
PRT4GS
12
RW
52
92
PRT4DM2
13
RW
53
93
IDX_PP
D3
RW
PRT5DR
14
RW
54
94
MVR_PP
D4
RW
PRT5IE
15
RW
55
95
MVW_PP
D5
RW
PRT5GS
16
RW
56
96
I2C0_CFG
D6
RW
PRT5DM2
17
RW
57
97
I2C0_SCR
D7
#
58
98
I2C0_DR
D8
RW
18
CF
D2
19
59
99
I2C0_MSCR
D9
#
1A
5A
9A
INT_CLR0
DA
RW
1B
5B
9B
INT_CLR1
DB
RW
1C
5C
9C
INT_CLR2
DC
RW
1D
5D
9D
INT_CLR3
DD
RW
1E
5E
9E
INT_MSK3
DE
RW
1F
5F
9F
INT_MSK2
DF
RW
#
60
A0
INT_MSK0
E0
RW
DBC00DR0
20
DBC00DR1
21
W
61
A1
INT_MSK1
E1
RW
DBC00DR2
22
RW
62
A2
INT_VC
E2
RC
DBC00CR0
23
#
63
A3
RES_WDT
E3
W
DBC01DR0
24
#
64
A4
I2C1_SCR
E4
#
DBC01DR1
25
W
65
A5
I2C1_MSCR
E5
#
DBC01DR2
26
RW
66
A6
DBC01CR0
27
#
DCC02DR0
28
#
68
MUL1_X
A8
W
MUL0_X
E8
W
DCC02DR1
29
W
69
MUL1_Y
A9
W
MUL0_Y
E9
W
DCC02DR2
2A
RW
SADC_DH
6A
RW
MUL1_DH
AA
R
MUL0_DH
EA
R
DCC02CR0
2B
#
SADC_DL
6B
RW
MUL1_DL
AB
R
MUL0_DL
EB
R
DCC03DR0
2C
#
TMP_DR0
6C
RW
ACC1_DR1
AC
RW
ACC0_DR1
EC
RW
DCC03DR1
2D
W
TMP_DR1
6D
RW
ACC1_DR0
AD
RW
ACC0_DR0
ED
RW
DCC03DR2
2E
RW
TMP_DR2
6E
RW
ACC1_DR3
AE
RW
ACC0_DR3
EE
RW
DCC03CR0
2F
#
TMP_DR3
6F
RW
ACC1_DR2
AF
RW
ACC0_DR2
EF
RW
DBC10DR0
30
#
70
RDI0RI
B0
RW
F0
DBC10DR1
31
W
71
RDI0SYN
B1
RW
F1
DBC10DR2
32
RW
72
RDI0IS
B2
RW
F2
DBC10CR0
33
#
73
RDI0LT0
B3
RW
F3
DBC11DR0
34
#
74
RDI0LT1
B4
RW
F4
DBC11DR1
35
W
75
RDI0RO0
B5
RW
F5
DBC11DR2
36
RW
76
RDI0RO1
B6
RW
DBC11CR0
37
#
77
RDI0DSM
B7
RW
DCC12DR0
38
#
78
RDI1RI
B8
RW
I2C1_DR
67
RW
E6
A7
E7
F6
CPU_F
F7
DCC12DR1
39
W
79
RDI1SYN
B9
RW
F9
DCC12DR2
3A
RW
7A
RDI1IS
BA
RW
FA
DCC12CR0
3B
#
7B
RDI1LT0
BB
RW
FB
DCC13DR0
3C
#
7C
RDI1LT1
BC
RW
FC
DCC13DR1
3D
W
7D
RDI1RO0
BD
RW
DCC13DR2
3E
RW
7E
RDI1RO1
BE
RW
DCC13CR0
3F
#
Blank fields are Reserved and should not be accessed.
Document Number: 001-48111 Rev. *K
7F
# Access is bit specific.
RL
F8
FD
CPU_SCR1
RDI1DSM
BF
RW
CPU_SCR0
*Address has a dual purpose, see “Mapping Exceptions” on page 251
FE
#
FF
#
Page 18 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 9. CY8C28x03 Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
Addr (1,Hex)
00
Access
RW
PRT0DM1
01
RW
PRT0IC0
02
RW
PRT0IC1
03
PRT1DM0
Name
DBC20FN
Addr (1,Hex)
40
Access
RW
DBC20IN
41
RW
DBC20OU
42
RW
RW
DBC20CR1
43
RW
04
RW
DBC21FN
44
PRT1DM1
05
RW
DBC21IN
PRT1IC0
06
RW
PRT1IC1
07
PRT2DM0
Name
Addr (1,Hex)
80
Access
SADC_TSCMPL
81
RW
SADC_TSCMPH
82
RW
Name
RDI2RI
Addr (1,Hex)
C0
Access
RW
RDI2SYN
C1
RW
RDI2IS
C2
RW
83
RDI2LT0
C3
RW
RW
84
RDI2LT1
C4
RW
45
RW
85
RDI2RO0
C5
RW
DBC21OU
46
RW
86
RDI2RO1
C6
RW
RW
DBC21CR1
47
RW
87
RDI2DSM
C7
RW
08
RW
DCC22FN
48
RW
88
PRT2DM1
09
RW
DCC22IN
49
RW
89
C9
PRT2IC0
0A
RW
DCC22OU
4A
RW
8A
CA
C8
PRT2IC1
0B
RW
DCC22CR1
4B
RW
8B
CB
PRT3DM0
0C
RW
DCC23FN
4C
RW
8C
CC
PRT3DM1
0D
RW
DCC23IN
4D
RW
8D
CD
PRT3IC0
0E
RW
DCC23OU
4E
RW
8E
CE
PRT3IC1
0F
RW
DCC23CR1
4F
RW
8F
PRT4DM0
10
RW
50
90
GDI_O_IN
D0
RW
PRT4DM1
11
RW
51
91
GDI_E_IN
D1
RW
PRT4IC0
12
RW
52
92
GDI_O_OU
D2
RW
PRT4IC1
13
RW
53
93
GDI_E_OU
D3
RW
PRT5DM0
14
RW
54
94
D4
CF
PRT5DM1
15
RW
55
95
D5
PRT5IC0
16
RW
56
96
D6
PRT5IC1
17
RW
57
97
D7
18
58
98
D8
19
59
99
D9
1A
5A
9A
DA
1B
5B
9B
DB
1C
5C
9C
DC
1D
5D
9D
OSC_GO_EN
DD
RW
1E
5E
9E
OSC_CR4
DE
RW
1F
5F
9F
OSC_CR3
DF
RW
DBC00FN
20
RW
60
GDI_O_IN_CR
A0
RW
OSC_CR0
E0
RW
DBC00IN
21
RW
61
GDI_E_IN_CR
A1
RW
OSC_CR1
E1
RW
DBC00OU
22
RW
62
GDI_O_OU_CR
A2
RW
OSC_CR2
E2
RW
DBC00CR1
23
RW
63
GDI_E_OU_CR
A3
RW
VLT_CR
E3
RW
DBC01FN
24
RW
64
RTC_H
A4
RW
VLT_CMP
E4
RW
DBC01IN
25
RW
65
RTC_M
A5
RW
E5
DBC01OU
26
RW
66
RTC_S
A6
RW
E6
DBC01CR1
27
RW
67
RTC_CR
A7
RW
DCC02FN
28
RW
68
SADC_CR0
A8
RW
IMO_TR
E8
RW
DCC02IN
29
RW
69
SADC_CR1
A9
RW
ILO_TR
E9
RW
DCC02OU
2A
RW
SADC_CR2
AA
RW
BDG_TR
EA
RW
DCC02CR1
2B
RW
I2C1_CFG
6B
RW
SADC_CR3
AB
RW
ECO_TR
EB
RW
DCC03FN
2C
RW
TMP_DR0
6C
RW
SADC_CR4
AC
RW
EC
DCC03IN
2D
RW
TMP_DR1
6D
RW
I2C0_ADDR
AD
RW
ED
DCC03OU
2E
RW
TMP_DR2
6E
RW
I2C1_ADDR
AE
RW
EE
DCC03CR1
2F
RW
TMP_DR3
6F
RW
AMUX_CLK
AF
RW
EF
DBC10FN
30
RW
RDI0RI
B0
RW
F0
DBC10IN
31
RW
SADC_TSCR0
71
RW
RDI0SYN
B1
RW
F1
DBC10OU
32
RW
SADC_TSCR1
72
RW
RDI0IS
B2
RW
F2
DBC10CR1
33
RW
73
RDI0LT0
B3
RW
F3
DBC11FN
34
RW
74
RDI0LT1
B4
RW
F4
DBC11IN
35
RW
75
RDI0RO0
B5
RW
F5
DBC11OU
36
RW
76
RDI0RO1
B6
RW
DBC11CR1
37
RW
77
RDIODSM
B7
RW
DCC12FN
38
RW
78
RDI1RI
B8
RW
DCC12IN
39
RW
79
RDI1SYN
B9
RW
DCC12OU
3A
RW
7A
RDI1IS
BA
RW
DCC12CR1
3B
RW
7B
RDI1LT0
BB
RW
FB
DCC13FN
3C
RW
7C
RDI1LT1
BC
RW
FC
DCC13IN
3D
RW
7D
RDI1RO0
BD
RW
DCC13OU
3E
RW
7E
RDI1RO1
BE
RW
CPU_SCR1
FE
#
DCC13CR1
3F
RW
7F
RDI1DSM
BF
RW
CPU_SCR0
FF
#
6A
70
Blank fields are Reserved and should not be accessed.
Document Number: 001-48111 Rev. *K
# Access is bit specific.
E7
F6
CPU_F
F7
RL
F8
F9
FLS_PR1
FA
RW
FD
*Address has a dual purpose, see “Mapping Exceptions” on page 251
Page 19 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 10. CY8C28x13 Register Map Bank 0 Table: User Space
Name
PRT0DR
Addr (0,Hex)
00
Access
RW
Name
DBC20DR0
Addr (0,Hex)
40
Access
#
Name
Addr (0,Hex)
80
PRT0IE
01
RW
DBC20DR1
41
W
81
PRT0GS
02
RW
DBC20DR2
42
RW
82
PRT0DM2
03
RW
DBC20CR0
43
#
PRT1DR
04
RW
DBC21DR0
44
PRT1IE
05
RW
DBC21DR1
PRT1GS
06
RW
PRT1DM2
07
PRT2DR
Access
Name
RDI2RI
Addr (0,Hex)
C0
Access
RW
RDI2SYN
C1
RW
RDI2IS
C2
RW
83
RDI2LT0
C3
RW
#
84
RDI2LT1
C4
RW
45
W
85
RDI2RO0
C5
RW
DBC21DR2
46
RW
86
RDI2RO1
C6
RW
RW
DBC21CR0
47
#
87
RDI2DSM
C7
RW
08
RW
DCC22DR0
48
#
88
PRT2IE
09
RW
DCC22DR1
49
W
89
C9
PRT2GS
0A
RW
DCC22DR2
4A
RW
8A
CA
C8
PRT2DM2
0B
RW
DCC22CR0
4B
#
8B
CB
PRT3DR
0C
RW
DCC23DR0
4C
#
8C
CC
PRT3IE
0D
RW
DCC23DR1
4D
W
8D
CD
PRT3GS
0E
RW
DCC23DR2
4E
RW
8E
CE
PRT3DM2
0F
RW
DCC23CR0
4F
#
8F
PRT4DR
10
RW
50
90
CUR_PP
D0
RW
PRT4IE
11
RW
51
91
STK_PP
D1
RW
PRT4GS
12
RW
52
92
PRT4DM2
13
RW
53
93
IDX_PP
D3
RW
PRT5DR
14
RW
54
94
MVR_PP
D4
RW
PRT5IE
15
RW
55
95
MVW_PP
D5
RW
PRT5GS
16
RW
56
96
I2C0_CFG
D6
RW
PRT5DM2
17
RW
57
97
I2C0_SCR
D7
#
58
98
I2C0_DR
D8
RW
18
CF
D2
19
59
99
I2C0_MSCR
D9
#
1A
5A
9A
INT_CLR0
DA
RW
1B
5B
9B
INT_CLR1
DB
RW
1C
5C
9C
INT_CLR2
DC
RW
1D
5D
9D
INT_CLR3
DD
RW
1E
5E
9E
INT_MSK3
DE
RW
1F
5F
9F
INT_MSK2
DF
RW
DBC00DR0
20
#
60
DBC00DR1
21
W
DBC00DR2
22
RW
62
DBC00CR0
23
#
63
DBC01DR0
24
#
64
A4
DBC01DR1
25
W
65
A5
DBC01DR2
26
RW
66
A6
DEC_CR0*
E6
RW
DBC01CR0
27
#
67
A7
DEC_CR1*
E7
RW
DCC02DR0
28
#
68
MUL1_X
A8
W
MUL0_X
E8
W
DCC02DR1
29
W
69
MUL1_Y
A9
W
MUL0_Y
E9
W
DCC02DR2
2A
RW
SADC_DH
6A
RW
MUL1_DH
AA
R
MUL0_DH
EA
R
DCC02CR0
2B
#
SADC_DL
6B
RW
MUL1_DL
AB
R
MUL0_DL
EB
R
DCC03DR0
2C
#
TMP_DR0
6C
RW
ACC1_DR1
AC
RW
ACC0_DR1
EC
RW
DCC03DR1
2D
W
TMP_DR1
6D
RW
ACC1_DR0
AD
RW
ACC0_DR0
ED
RW
DCC03DR2
2E
RW
TMP_DR2
6E
RW
ACC1_DR3
AE
RW
ACC0_DR3
EE
RW
DCC03CR0
2F
#
TMP_DR3
6F
RW
ACC1_DR2
AF
RW
ACC0_DR2
EF
RW
DBC10DR0
30
#
70
RDI0RI
B0
RW
F0
DBC10DR1
31
W
71
RDI0SYN
B1
RW
F1
DBC10DR2
32
RW
72
RDI0IS
B2
RW
F2
DBC10CR0
33
#
73
RDI0LT0
B3
RW
F3
DBC11DR0
34
#
74
RDI0LT1
B4
RW
F4
DBC11DR1
35
W
75
RDI0RO0
B5
RW
F5
DBC11DR2
36
RW
76
RDI0RO1
B6
RW
DBC11CR0
37
#
77
RDI0DSM
B7
RW
DCC12DR0
38
#
78
RDI1RI
B8
RW
AMUX_CFG
61
RW
DEC0_DH
A0
RC
INT_MSK0
E0
RW
DEC0_DL
A1
RC
INT_MSK1
E1
RW
DEC1_DH
A2
RC
INT_VC
E2
RC
DEC1_DL
A3
RC
RES_WDT
E3
W
E4
E5
F6
CPU_F
F7
RL
F8
DCC12DR1
39
W
79
RDI1SYN
B9
RW
F9
DCC12DR2
3A
RW
7A
RDI1IS
BA
RW
FA
DCC12CR0
3B
#
7B
RDI1LT0
BB
RW
DCC13DR0
3C
#
7C
RDI1LT1
BC
RW
DAC1_D
FC
RW
DCC13DR1
3D
W
7D
RDI1RO0
BD
RW
DAC0_D
FD
RW
DCC13DR2
3E
RW
7E
RDI1RO1
BE
RW
CPU_SCR1
FE
#
FF
#
DCC13CR0
3F
#
Blank fields are Reserved and should not be accessed.
Document Number: 001-48111 Rev. *K
7F
# Access is bit specific.
FB
RDI1DSM
BF
RW
CPU_SCR0
*Address has a dual purpose, see “Mapping Exceptions” on page 251
Page 20 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 11. CY8C28x13 Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
Addr (1,Hex)
00
Access
RW
PRT0DM1
01
RW
PRT0IC0
02
RW
PRT0IC1
03
PRT1DM0
Name
DBC20FN
Addr (1,Hex)
40
Access
RW
Name
Addr (1,Hex)
80
Access
SADC_TSCMPL
81
RW
SADC_TSCMPH
82
RW
ACE_AMD_CR1
83
RW
Addr (1,Hex)
C0
Access
RW
DBC20IN
41
RW
DBC20OU
42
RW
RDI2SYN
C1
RW
RDI2IS
C2
RW
DBC20CR1
43
RW
RW
RDI2LT0
C3
04
RW
DBC21FN
44
RW
RW
RDI2LT1
C4
PRT1DM1
05
RW
DBC21IN
45
RW
ACE_PWM_CR
85
RW
RW
RDI2RO0
C5
PRT1IC0
06
RW
DBC21OU
46
RW
ACE_ADC0_CR
RW
86
RW
RDI2RO1
C6
PRT1IC1
07
RW
DBC21CR1
47
RW
ACE_ADC1_CR
RW
87
RW
RDI2DSM
C7
PRT2DM0
08
RW
DCC22FN
48
RW
RW
PRT2DM1
09
RW
DCC22IN
49
RW
ACE_CLK_CR0
89
RW
C9
PRT2IC0
0A
RW
DCC22OU
4A
RW
ACE_CLK_CR1
8A
RW
CA
ACE_CLK_CR3
8B
RW
CB
8C
RW
CC
84
Name
RDI2RI
88
C8
PRT2IC1
0B
RW
DCC22CR1
4B
RW
PRT3DM0
0C
RW
DCC23FN
4C
RW
PRT3DM1
0D
RW
DCC23IN
4D
RW
ACE01CR1
8D
RW
CD
PRT3IC0
0E
RW
DCC23OU
4E
RW
ACE01CR2
8E
RW
CE
PRT3IC1
0F
RW
DCC23CR1
4F
RW
ASE11CR0
8F
RW
PRT4DM0
10
RW
50
PRT4DM1
11
RW
51
DEC0_CR0
91
PRT4IC0
12
RW
52
DEC_CR3
92
PRT4IC1
13
RW
53
PRT5DM0
14
RW
54
PRT5DM1
15
RW
55
PRT5IC0
16
RW
56
96
PRT5IC1
17
RW
90
DEC1_CR0
CF
GDI_O_IN
D0
RW
RW
GDI_E_IN
D1
RW
RW
GDI_O_OU
D2
RW
93
GDI_E_OU
D3
RW
94
DEC0_CR
D4
RW
DEC1_CR
D5
RW
95
RW
D6
57
97
18
58
98
MUX_CR0
D8
RW
19
59
99
MUX_CR1
D9
RW
1A
5A
MUX_CR2
DA
RW
1B
5B
9B
MUX_CR3
DB
RW
1C
5C
9C
IDAC_CR1
DC
RW
1D
5D
9D
OSC_GO_EN
DD
RW
1E
5E
9E
OSC_CR4
DE
RW
1F
5F
9F
OSC_CR3
DF
RW
DEC_CR5
9A
D7
RW
DBC00FN
20
RW
60
GDI_O_IN_CR
A0
RW
OSC_CR0
E0
RW
DBC00IN
21
RW
61
GDI_E_IN_CR
A1
RW
OSC_CR1
E1
RW
DBC00OU
22
RW
62
GDI_O_OU_CR
A2
RW
OSC_CR2
E2
RW
DBC00CR1
23
RW
63
GDI_E_OU_CR
A3
RW
VLT_CR
E3
RW
DBC01FN
24
RW
64
RTC_H
A4
RW
VLT_CMP
E4
RW
DBC01IN
25
RW
65
RTC_M
A5
RW
ADC0_TR
E5
RW
DBC01OU
26
RW
66
RTC_S
A6
RW
ADC1_TR
E6
RW
DBC01CR1
27
RW
67
RTC_CR
A7
RW
IDAC_CR2
E7
RW
DCC02FN
28
RW
68
SADC_CR0
A8
RW
IMO_TR
E8
RW
DCC02IN
29
RW
SADC_CR1
A9
RW
ILO_TR
E9
RW
DCC02OU
2A
RW
SADC_CR2
AA
RW
BDG_TR
EA
RW
DCC02CR1
2B
RW
SADC_CR3
AB
RW
ECO_TR
EB
RW
DCC03FN
2C
RW
TMP_DR0
6C
RW
SADC_CR4
AC
RW
MUX_CR4
EC
RW
DCC03IN
2D
RW
TMP_DR1
6D
RW
I2C0_ADDR
AD
RW
MUX_CR5
ED
RW
DCC03OU
2E
RW
TMP_DR2
6E
RW
DCC03CR1
2F
RW
TMP_DR3
6F
RW
DBC10FN
30
RW
DBC10IN
31
RW
SADC_TSCR0
71
DBC10OU
32
RW
SADC_TSCR1
DBC10CR1
33
RW
ACE_AMD_CR0
DBC11FN
34
RW
DBC11IN
35
RW
DBC11OU
36
DBC11CR1
DCC12FN
69
AMUX_CFG1
6A
RW
6B
AE
EE
AMUX_CLK
AF
RW
EF
RDI0RI
B0
RW
F0
RW
RDI0SYN
B1
RW
F1
72
RW
RDI0IS
B2
RW
F2
73
RW
RDI0LT0
B3
RW
F3
74
RW
RDI0LT1
B4
RW
F4
ACE_AMX_IN
75
RW
RDI0RO0
B5
RW
F5
RW
ACE_CMP_CR0
76
RW
RDI0RO1
B6
RW
37
RW
ACE_CMP_CR1
77
RW
RDIODSM
B7
RW
38
RW
RDI1RI
B8
RW
DCC12IN
39
RW
ACE_CMP_GI_EN
79
RW
RDI1SYN
B9
RW
DCC12OU
3A
RW
ACE_ALT_CR0
7A
RW
RDI1IS
BA
RW
DCC12CR1
3B
RW
ACE_ABF_CR0
7B
RW
RDI1LT0
BB
RW
DCC13FN
3C
RW
RDI1LT1
BC
RW
DCC13IN
3D
RW
ACE0_CR1
7D
RW
RDI1RO0
BD
RW
IDAC_CR0
FD
RW
DCC13OU
3E
RW
ACE0_CR2
7E
RW
RDI1RO1
BE
RW
CPU_SCR1
FE
#
DCC13CR1
3F
RW
ACE0_CR3
7F
RW
RDI1DSM
BF
RW
CPU_SCR0
FF
#
70
78
7C
Blank fields are Reserved and should not be accessed.
Document Number: 001-48111 Rev. *K
# Access is bit specific.
F6
CPU_F
F7
RL
F8
F9
FLS_PR1
FA
RW
FB
FC
*Address has a dual purpose, see “Mapping Exceptions” on page 251
Page 21 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 12. CY8C28x23 Register Map Bank 0 Table: User Space
Name
PRT0DR
Addr (0,Hex)
00
Access
RW
Name
DBC20DR0
Addr (0,Hex)
40
Access
#
Name
ASC10CR0
Addr (0,Hex)
80
Access
RW
PRT0IE
01
RW
DBC20DR1
PRT0GS
02
RW
DBC20DR2
PRT0DM2
03
RW
PRT1DR
04
PRT1IE
Name
RDI2RI
Addr (0,Hex)
C0
Access
RW
41
W
ASC10CR1
81
RW
42
RW
ASC10CR2
82
RW
RDI2SYN
C1
RW
RDI2IS
C2
DBC20CR0
43
#
ASC10CR3
83
RW
RW
RDI2LT0
C3
RW
DBC21DR0
44
#
ASD11CR0
RW
84
RW
RDI2LT1
C4
05
RW
DBC21DR1
45
W
RW
ASD11CR1
85
RW
RDI2RO0
C5
PRT1GS
06
RW
DBC21DR2
46
RW
RW
ASD11CR2
86
RW
RDI2RO1
C6
PRT1DM2
07
RW
DBC21CR0
RW
47
#
ASD11CR3
87
RW
RDI2DSM
C7
PRT2DR
08
RW
DCC22DR0
RW
48
#
PRT2IE
09
RW
DCC22DR1
49
W
89
C9
PRT2GS
0A
RW
DCC22DR2
4A
RW
8A
CA
88
C8
PRT2DM2
0B
RW
DCC22CR0
4B
#
8B
CB
PRT3DR
0C
RW
DCC23DR0
4C
#
8C
CC
PRT3IE
0D
RW
DCC23DR1
4D
W
8D
CD
PRT3GS
0E
RW
DCC23DR2
4E
RW
8E
CE
PRT3DM2
0F
RW
DCC23CR0
4F
#
8F
PRT4DR
10
RW
50
ASD20CR0
90
RW
CUR_PP
D0
RW
PRT4IE
11
RW
51
ASD20CR1
91
RW
STK_PP
D1
RW
PRT4GS
12
RW
52
ASD20CR2
92
RW
PRT4DM2
13
RW
53
ASD20CR3
93
RW
IDX_PP
D3
RW
PRT5DR
14
RW
54
ASC21CR0
94
RW
MVR_PP
D4
RW
PRT5IE
15
RW
55
ASC21CR1
95
RW
MVW_PP
D5
RW
PRT5GS
16
RW
56
ASC21CR2
96
RW
I2C0_CFG
D6
RW
PRT5DM2
17
RW
57
ASC21CR3
97
RW
I2C0_SCR
D7
#
98
I2C0_DR
D8
RW
18
58
CF
D2
19
59
99
I2C0_MSCR
D9
#
1A
5A
9A
INT_CLR0
DA
RW
1B
5B
9B
INT_CLR1
DB
RW
1C
5C
9C
INT_CLR2
DC
RW
1D
5D
9D
INT_CLR3
DD
RW
1E
5E
9E
INT_MSK3
DE
RW
1F
5F
9F
INT_MSK2
DF
RW
DBC00DR0
20
#
AMX_IN
60
RW
DEC0_DH
A0
RC
INT_MSK0
E0
RW
DBC00DR1
DBC00DR2
21
W
AMUX_CFG
61
RW
DEC0_DL
A1
RC
INT_MSK1
E1
RW
22
RW
CLK_CR3
62
RW
DEC1_DH
A2
RC
INT_VC
E2
RC
DBC00CR0
23
#
ARF_CR
63
RW
DEC1_DL
A3
RC
RES_WDT
E3
W
DBC01DR0
24
#
CMP_CR0
64
#
A4
I2C1_SCR
E4
#
DBC01DR1
25
W
ASY_CR
65
#
A5
I2C1_MSCR
E5
#
DBC01DR2
26
RW
CMP_CR1
66
RW
A6
DEC_CR0*
E6
RW
DBC01CR0
27
#
I2C1_DR
67
RW
DEC_CR1*
E7
RW
DCC02DR0
28
#
68
MUL1_X
A8
W
MUL0_X
E8
W
DCC02DR1
29
W
69
MUL1_Y
A9
W
MUL0_Y
E9
W
DCC02DR2
2A
RW
6A
MUL1_DH
AA
R
MUL0_DH
EA
R
DCC02CR0
2B
#
6B
MUL1_DL
AB
R
MUL0_DL
EB
R
DCC03DR0
2C
#
TMP_DR0
6C
RW
ACC1_DR1
AC
RW
ACC0_DR1
EC
RW
DCC03DR1
2D
W
TMP_DR1
6D
RW
ACC1_DR0
AD
RW
ACC0_DR0
ED
RW
DCC03DR2
2E
RW
TMP_DR2
6E
RW
ACC1_DR3
AE
RW
ACC0_DR3
EE
RW
DCC03CR0
2F
#
TMP_DR3
6F
RW
ACC1_DR2
AF
RW
ACC0_DR2
EF
RW
DBC10DR0
30
#
ACB00CR3
70
RW
RDI0RI
B0
RW
F0
DBC10DR1
31
W
ACB00CR0
71
RW
RDI0SYN
B1
RW
F1
DBC10DR2
32
RW
ACB00CR1
72
RW
RDI0IS
B2
RW
F2
DBC10CR0
33
#
ACB00CR2
73
RW
RDI0LT0
B3
RW
F3
DBC11DR0
34
#
ACB01CR3
74
RW
RDI0LT1
B4
RW
F4
DBC11DR1
35
W
ACB01CR0
75
RW
RDI0RO0
B5
RW
F5
DBC11DR2
36
RW
ACB01CR1
76
RW
RDI0RO1
B6
RW
DBC11CR0
37
#
ACB01CR2
77
RW
RDI0DSM
B7
RW
DCC12DR0
38
#
78
RDI1RI
B8
RW
A7
F6
CPU_F
F7
DCC12DR1
39
W
79
RDI1SYN
B9
RW
F9
DCC12DR2
3A
RW
7A
RDI1IS
BA
RW
FA
DCC12CR0
3B
#
7B
RDI1LT0
BB
RW
FB
DCC13DR0
3C
#
7C
RDI1LT1
BC
RW
FC
DCC13DR1
3D
W
7D
RDI1RO0
BD
RW
DCC13DR2
3E
RW
7E
RDI1RO1
BE
RW
DCC13CR0
3F
#
Blank fields are Reserved and should not be accessed.
Document Number: 001-48111 Rev. *K
7F
# Access is bit specific.
RL
F8
FD
CPU_SCR1
RDI1DSM
BF
RW
CPU_SCR0
*Address has a dual purpose, see “Mapping Exceptions” on page 251
FE
#
FF
#
Page 22 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 13. CY8C28x23 Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
Addr (1,Hex)
00
Access
RW
PRT0DM1
01
RW
PRT0IC0
02
RW
PRT0IC1
03
PRT1DM0
Name
DBC20FN
Addr (1,Hex)
40
Access
RW
Name
Addr (1,Hex)
80
DBC20IN
41
RW
81
DBC20OU
42
RW
82
RW
DBC20CR1
43
RW
04
RW
DBC21FN
44
PRT1DM1
05
RW
DBC21IN
PRT1IC0
06
RW
PRT1IC1
07
PRT2DM0
Access
Name
RDI2RI
Addr (1,Hex)
C0
Access
RW
RDI2SYN
C1
RW
RDI2IS
C2
RW
83
RDI2LT0
C3
RW
RW
84
RDI2LT1
C4
RW
45
RW
85
RDI2RO0
C5
RW
DBC21OU
46
RW
86
RDI2RO1
C6
RW
RW
DBC21CR1
47
RW
87
RDI2DSM
C7
RW
08
RW
DCC22FN
48
RW
88
PRT2DM1
09
RW
DCC22IN
49
RW
89
C9
PRT2IC0
0A
RW
DCC22OU
4A
RW
8A
CA
C8
PRT2IC1
0B
RW
DCC22CR1
4B
RW
8B
CB
PRT3DM0
0C
RW
DCC23FN
4C
RW
8C
CC
PRT3DM1
0D
RW
DCC23IN
4D
RW
8D
CD
PRT3IC0
0E
RW
DCC23OU
4E
RW
8E
CE
PRT3IC1
0F
RW
DCC23CR1
4F
RW
8F
PRT4DM0
10
RW
50
PRT4DM1
11
RW
51
DEC0_CR0
91
PRT4IC0
12
RW
52
DEC_CR3
PRT4IC1
13
RW
PRT5DM0
14
PRT5DM1
CF
90
GDI_O_IN
D0
RW
RW
GDI_E_IN
D1
RW
92
RW
GDI_O_OU
D2
RW
53
93
RW
GDI_E_OU
D3
RW
RW
54
94
RW
DEC0_CR
D4
RW
15
RW
55
95
RW
DEC1_CR
D5
RW
PRT5IC0
16
RW
56
96
D6
PRT5IC1
17
RW
DEC1_CR0
57
97
D7
18
58
98
D8
19
59
99
1A
5A
DEC_CR5
9A
D9
RW
DA
1B
5B
9B
DB
1C
5C
9C
DC
1D
5D
9D
OSC_GO_EN
DD
RW
1E
5E
9E
OSC_CR4
DE
RW
1F
5F
9F
OSC_CR3
DF
RW
DBC00FN
20
RW
CLK_CR0
60
RW
GDI_O_IN_CR
A0
RW
OSC_CR0
E0
RW
DBC00IN
21
RW
CLK_CR1
61
RW
GDI_E_IN_CR
A1
RW
OSC_CR1
E1
RW
DBC00OU
22
RW
ABF_CR0
62
RW
GDI_O_OU_CR
A2
RW
OSC_CR2
E2
RW
DBC00CR1
23
RW
AMD_CR0
63
RW
GDI_E_OU_CR
A3
RW
VLT_CR
E3
RW
DBC01FN
24
RW
CMP_GO_EN
64
RW
RTC_H
A4
RW
VLT_CMP
E4
RW
DBC01IN
25
RW
RTC_M
A5
RW
E5
DBC01OU
26
RW
AMD_CR1
66
RW
RTC_S
A6
RW
E6
DBC01CR1
27
RW
ALT_CR0
67
RW
RTC_CR
A7
RW
DCC02FN
28
RW
DCC02IN
29
RW
DCC02OU
2A
RW
DCC02CR1
2B
RW
I2C1_CFG
6B
RW
DCC03FN
2C
RW
TMP_DR0
6C
RW
AC
DCC03IN
2D
RW
TMP_DR1
6D
RW
I2C0_ADDR
AD
RW
ED
DCC03OU
2E
RW
TMP_DR2
6E
RW
I2C1_ADDR
AE
RW
EE
DCC03CR1
2F
RW
TMP_DR3
6F
RW
AMUX_CLK
AF
RW
EF
DBC10FN
30
RW
70
RDI0RI
B0
RW
F0
DBC10IN
31
RW
71
RDI0SYN
B1
RW
F1
DBC10OU
32
RW
72
RDI0IS
B2
RW
F2
DBC10CR1
33
RW
73
RDI0LT0
B3
RW
F3
DBC11FN
34
RW
74
RDI0LT1
B4
RW
F4
DBC11IN
35
RW
75
RDI0RO0
B5
RW
F5
DBC11OU
36
RW
76
RDI0RO1
B6
RW
DBC11CR1
37
RW
77
RDIODSM
B7
RW
DCC12FN
38
RW
78
RDI1RI
B8
RW
DCC12IN
39
RW
79
RDI1SYN
B9
RW
DCC12OU
3A
RW
7A
RDI1IS
BA
RW
DCC12CR1
3B
RW
7B
RDI1LT0
BB
RW
FB
DCC13FN
3C
RW
7C
RDI1LT1
BC
RW
FC
DCC13IN
3D
RW
7D
RDI1RO0
BD
RW
DCC13OU
3E
RW
7E
RDI1RO1
BE
RW
CPU_SCR1
FE
#
DCC13CR1
3F
RW
7F
RDI1DSM
BF
RW
CPU_SCR0
FF
#
65
68
CLK_CR2
69
RW
6A
Blank fields are Reserved and should not be accessed.
Document Number: 001-48111 Rev. *K
# Access is bit specific.
E7
A8
IMO_TR
E8
RW
A9
ILO_TR
E9
RW
AA
BDG_TR
EA
RW
AB
ECO_TR
EB
RW
EC
F6
CPU_F
F7
RL
F8
F9
FLS_PR1
FA
RW
FD
*Address has a dual purpose, see “Mapping Exceptions” on page 251
Page 23 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 14. CY8C28x33 Register Map Bank 0 Table: User Space
Name
PRT0DR
Addr (0,Hex)
00
Access
RW
Name
DBC20DR0
Addr (0,Hex)
40
Access
#
Name
ASC10CR0
Addr (0,Hex)
80
Access
RW
PRT0IE
01
RW
DBC20DR1
PRT0GS
02
RW
DBC20DR2
PRT0DM2
03
RW
PRT1DR
04
PRT1IE
Name
RDI2RI
Addr (0,Hex)
C0
Access
RW
41
W
ASC10CR1
81
RW
42
RW
ASC10CR2
82
RW
RDI2SYN
C1
RW
RDI2IS
C2
DBC20CR0
43
#
ASC10CR3
83
RW
RW
RDI2LT0
C3
RW
DBC21DR0
44
#
ASD11CR0
RW
84
RW
RDI2LT1
C4
05
RW
DBC21DR1
45
W
RW
ASD11CR1
85
RW
RDI2RO0
C5
PRT1GS
06
RW
DBC21DR2
46
RW
RW
ASD11CR2
86
RW
RDI2RO1
C6
PRT1DM2
07
RW
DBC21CR0
RW
47
#
ASD11CR3
87
RW
RDI2DSM
C7
PRT2DR
08
RW
DCC22DR0
RW
48
#
PRT2IE
09
RW
DCC22DR1
49
W
89
C9
PRT2GS
0A
RW
DCC22DR2
4A
RW
8A
CA
88
C8
PRT2DM2
0B
RW
DCC22CR0
4B
#
8B
CB
PRT3DR
0C
RW
DCC23DR0
4C
#
8C
CC
PRT3IE
0D
RW
DCC23DR1
4D
W
8D
CD
PRT3GS
0E
RW
DCC23DR2
4E
RW
8E
CE
PRT3DM2
0F
RW
DCC23CR0
4F
#
8F
PRT4DR
10
RW
50
ASD20CR0
90
RW
CUR_PP
D0
RW
PRT4IE
11
RW
51
ASD20CR1
91
RW
STK_PP
D1
RW
PRT4GS
12
RW
52
ASD20CR2
92
RW
PRT4DM2
13
RW
53
ASD20CR3
93
RW
IDX_PP
D3
RW
PRT5DR
14
RW
54
ASC21CR0
94
RW
MVR_PP
D4
RW
PRT5IE
15
RW
55
ASC21CR1
95
RW
MVW_PP
D5
RW
PRT5GS
16
RW
56
ASC21CR2
96
RW
I2C0_CFG
D6
RW
PRT5DM2
17
RW
57
ASC21CR3
97
RW
I2C0_SCR
D7
#
98
I2C0_DR
D8
RW
18
58
CF
D2
19
59
99
I2C0_MSCR
D9
#
1A
5A
9A
INT_CLR0
DA
RW
1B
5B
9B
INT_CLR1
DB
RW
1C
5C
9C
INT_CLR2
DC
RW
1D
5D
9D
INT_CLR3
DD
RW
1E
5E
9E
INT_MSK3
DE
RW
1F
5F
9F
INT_MSK2
DF
RW
DBC00DR0
20
#
AMX_IN
60
RW
DEC0_DH
A0
RC
INT_MSK0
E0
RW
DBC00DR1
DBC00DR2
21
W
AMUX_CFG
61
RW
DEC0_DL
A1
RC
INT_MSK1
E1
RW
22
RW
CLK_CR3
62
RW
DEC1_DH
A2
RC
INT_VC
E2
RC
DBC00CR0
23
#
ARF_CR
63
RW
DEC1_DL
A3
RC
RES_WDT
E3
W
DBC01DR0
24
#
CMP_CR0
64
#
DEC2_DH
A4
RC
DBC01DR1
25
W
ASY_CR
65
#
DEC2_DL
A5
RC
DBC01DR2
26
RW
CMP_CR1
66
RW
DEC3_DH
A6
RC
DEC_CR0*
E6
RW
DBC01CR0
27
#
67
DEC3_DL
A7
RC
DEC_CR1*
E7
RW
DCC02DR0
28
#
68
MUL1_X
A8
W
MUL0_X
E8
W
DCC02DR1
29
W
69
MUL1_Y
A9
W
MUL0_Y
E9
W
DCC02DR2
2A
RW
SADC_DH
6A
RW
MUL1_DH
AA
R
MUL0_DH
EA
R
DCC02CR0
2B
#
SADC_DL
6B
RW
MUL1_DL
AB
R
MUL0_DL
EB
R
DCC03DR0
2C
#
TMP_DR0
6C
RW
ACC1_DR1
AC
RW
ACC0_DR1
EC
RW
DCC03DR1
2D
W
TMP_DR1
6D
RW
ACC1_DR0
AD
RW
ACC0_DR0
ED
RW
DCC03DR2
2E
RW
TMP_DR2
6E
RW
ACC1_DR3
AE
RW
ACC0_DR3
EE
RW
DCC03CR0
2F
#
TMP_DR3
6F
RW
ACC1_DR2
AF
RW
ACC0_DR2
EF
RW
DBC10DR0
30
#
ACB00CR3
70
RW
RDI0RI
B0
RW
F0
DBC10DR1
31
W
ACB00CR0
71
RW
RDI0SYN
B1
RW
F1
DBC10DR2
32
RW
ACB00CR1
72
RW
RDI0IS
B2
RW
F2
DBC10CR0
33
#
ACB00CR2
73
RW
RDI0LT0
B3
RW
F3
DBC11DR0
34
#
ACB01CR3
74
RW
RDI0LT1
B4
RW
F4
DBC11DR1
35
W
ACB01CR0
75
RW
RDI0RO0
B5
RW
F5
DBC11DR2
36
RW
ACB01CR1
76
RW
RDI0RO1
B6
RW
DBC11CR0
37
#
ACB01CR2
77
RW
RDI0DSM
B7
RW
DCC12DR0
38
#
78
RDI1RI
B8
RW
E4
E5
F6
CPU_F
F7
RL
F8
DCC12DR1
39
W
79
RDI1SYN
B9
RW
F9
DCC12DR2
3A
RW
7A
RDI1IS
BA
RW
FA
DCC12CR0
3B
#
7B
RDI1LT0
BB
RW
DCC13DR0
3C
#
7C
RDI1LT1
BC
RW
DAC1_D
FC
RW
DCC13DR1
3D
W
7D
RDI1RO0
BD
RW
DAC0_D
FD
RW
DCC13DR2
3E
RW
7E
RDI1RO1
BE
RW
CPU_SCR1
FE
#
FF
#
DCC13CR0
3F
#
Blank fields are Reserved and should not be accessed.
Document Number: 001-48111 Rev. *K
7F
# Access is bit specific.
FB
RDI1DSM
BF
RW
CPU_SCR0
*Address has a dual purpose, see “Mapping Exceptions” on page 251
Page 24 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 15. CY8C28x33 Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
Addr (1,Hex)
00
Access
RW
PRT0DM1
01
RW
PRT0IC0
02
RW
PRT0IC1
03
PRT1DM0
Name
DBC20FN
Addr (1,Hex)
40
Access
RW
Name
Addr (1,Hex)
80
Access
DBC20IN
41
RW
DBC20OU
42
RW
SADC_TSCMPL
81
RW
SADC_TSCMPH
82
RW
RW
DBC20CR1
43
RW
ACE_AMD_CR1
83
RW
04
RW
DBC21FN
44
RW
Addr (1,Hex)
C0
Access
RW
RDI2SYN
C1
RW
RDI2IS
C2
RW
RDI2LT0
C3
RW
RDI2LT1
C4
PRT1DM1
05
RW
DBC21IN
45
RW
ACE_PWM_CR
85
RW
RW
RDI2RO0
C5
PRT1IC0
06
RW
DBC21OU
46
RW
ACE_ADC0_CR
RW
86
RW
RDI2RO1
C6
PRT1IC1
07
RW
DBC21CR1
47
RW
ACE_ADC1_CR
RW
87
RW
RDI2DSM
C7
PRT2DM0
08
RW
DCC22FN
48
RW
RW
88
RW
PRT2DM1
09
RW
DCC22IN
49
RW
PRT2IC0
0A
RW
DCC22OU
4A
RW
ACE_CLK_CR0
89
RW
C9
ACE_CLK_CR1
8A
RW
CA
ACE_CLK_CR3
8B
RW
84
Name
RDI2RI
C8
PRT2IC1
0B
RW
DCC22CR1
4B
RW
PRT3DM0
0C
RW
DCC23FN
4C
RW
CB
PRT3DM1
0D
RW
DCC23IN
4D
RW
ACE01CR1
8D
RW
CD
PRT3IC0
0E
RW
DCC23OU
4E
RW
ACE01CR2
8E
RW
CE
PRT3IC1
0F
RW
DCC23CR1
4F
RW
ASE11CR0
8F
RW
PRT4DM0
10
RW
50
PRT4DM1
11
RW
51
DEC0_CR0
91
PRT4IC0
12
RW
52
DEC_CR3
92
PRT4IC1
13
RW
53
PRT5DM0
14
RW
54
PRT5DM1
15
RW
55
DEC1_CR0
95
PRT5IC0
16
RW
56
DEC_CR4
96
PRT5IC1
17
RW
57
18
58
19
59
DEC2_CR0
99
1A
5A
DEC_CR5
9A
1B
5B
1C
5C
1D
5D
1E
5E
9E
1F
5F
9F
8C
CC
90
DEC3_CR0
CF
GDI_O_IN
D0
RW
RW
GDI_E_IN
D1
RW
RW
GDI_O_OU
D2
RW
93
GDI_E_OU
D3
RW
94
DEC0_CR
D4
RW
RW
DEC1_CR
D5
RW
RW
DEC2_CR
D6
RW
97
DEC3_CR
D7
RW
98
MUX_CR0
D8
RW
RW
MUX_CR1
D9
RW
RW
MUX_CR2
DA
RW
9B
MUX_CR3
DB
RW
9C
IDAC_CR1
DC
RW
OSC_GO_EN
DD
RW
OSC_CR4
DE
RW
OSC_CR3
DF
RW
9D
RW
DBC00FN
20
RW
CLK_CR0
60
RW
GDI_O_IN_CR
A0
RW
OSC_CR0
E0
RW
DBC00IN
21
RW
CLK_CR1
61
RW
GDI_E_IN_CR
A1
RW
OSC_CR1
E1
RW
DBC00OU
22
RW
ABF_CR0
62
RW
GDI_O_OU_CR
A2
RW
OSC_CR2
E2
RW
DBC00CR1
23
RW
AMD_CR0
63
RW
GDI_E_OU_CR
A3
RW
VLT_CR
E3
RW
DBC01FN
24
RW
CMP_GO_EN
64
RW
RTC_H
A4
RW
VLT_CMP
E4
RW
DBC01IN
25
RW
RTC_M
A5
RW
ADC0_TR
E5
RW
DBC01OU
26
RW
AMD_CR1
66
RW
RTC_S
A6
RW
ADC1_TR
E6
RW
DBC01CR1
27
RW
ALT_CR0
67
RW
RTC_CR
A7
RW
IDAC_CR2
E7
RW
DCC02FN
28
RW
SADC_CR0
A8
RW
IMO_TR
E8
RW
DCC02IN
29
RW
CLK_CR2
69
RW
SADC_CR1
A9
RW
ILO_TR
E9
RW
DCC02OU
2A
RW
AMUX_CFG1
6A
RW
SADC_CR2
AA
RW
BDG_TR
EA
RW
DCC02CR1
2B
RW
SADC_CR3
AB
RW
ECO_TR
EB
RW
DCC03FN
2C
RW
TMP_DR0
6C
RW
SADC_CR4
AC
RW
MUX_CR4
EC
RW
DCC03IN
2D
RW
TMP_DR1
6D
RW
I2C0_ADDR
AD
RW
MUX_CR5
ED
RW
DCC03OU
2E
RW
TMP_DR2
6E
RW
DCC03CR1
2F
RW
TMP_DR3
6F
RW
DBC10FN
30
RW
DBC10IN
31
RW
SADC_TSCR0
71
DBC10OU
32
RW
SADC_TSCR1
DBC10CR1
33
RW
ACE_AMD_CR0
DBC11FN
34
RW
DBC11IN
35
RW
ACE_AMX_IN
75
DBC11OU
36
RW
ACE_CMP_CR0
DBC11CR1
37
RW
ACE_CMP_CR1
DCC12FN
38
RW
DCC12IN
39
RW
ACE_CMP_GI_EN
79
RW
DCC12OU
3A
RW
ACE_ALT_CR0
7A
RW
DCC12CR1
3B
RW
ACE_ABF_CR0
7B
RW
DCC13FN
3C
RW
DCC13IN
3D
RW
ACE0_CR1
7D
RW
DCC13OU
3E
RW
ACE0_CR2
7E
DCC13CR1
3F
RW
ACE0_CR3
7F
65
68
6B
AF
RW
EF
RDI0RI
B0
RW
F0
RW
RDI0SYN
B1
RW
F1
72
RW
RDI0IS
B2
RW
F2
73
RW
RDI0LT0
B3
RW
F3
RDI0LT1
B4
RW
F4
RW
RDI0RO0
B5
RW
F5
76
RW
RDI0RO1
B6
RW
77
RW
RDIODSM
B7
RW
RDI1RI
B8
RW
RDI1SYN
B9
RW
RDI1IS
BA
RW
RDI1LT0
BB
RW
RDI1LT1
BC
RW
RDI1RO0
BD
RW
IDAC_CR0
FD
RW
RW
RDI1RO1
BE
RW
CPU_SCR1
FE
#
RW
RDI1DSM
BF
RW
CPU_SCR0
FF
#
74
78
7C
Document Number: 001-48111 Rev. *K
EE
AMUX_CLK
70
Blank fields are Reserved and should not be accessed.
AE
# Access is bit specific.
F6
CPU_F
F7
RL
F8
F9
FLS_PR1
FA
RW
FB
FC
*Address has a dual purpose, see “Mapping Exceptions” on page 251
Page 25 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 16. CY8C28x43 Register Map Bank 0 Table: User Space
Name
PRT0DR
Addr (0,Hex)
00
Access
RW
Name
DBC20DR0
Addr (0,Hex)
40
Access
#
Name
ASC10CR0
Addr (0,Hex)
80
Access
RW
PRT0IE
01
RW
DBC20DR1
PRT0GS
02
RW
DBC20DR2
41
W
ASC10CR1
81
RW
42
RW
ASC10CR2
82
RW
PRT0DM2
03
RW
DBC20CR0
43
#
ASC10CR3
83
PRT1DR
04
RW
DBC21DR0
44
#
ASD11CR0
PRT1IE
05
RW
DBC21DR1
45
W
PRT1GS
06
RW
DBC21DR2
46
PRT1DM2
07
RW
DBC21CR0
PRT2DR
08
RW
DCC22DR0
PRT2IE
09
RW
DCC22DR1
PRT2GS
0A
RW
DCC22DR2
Name
RDI2RI
Addr (0,Hex)
C0
Access
RW
RDI2SYN
C1
RW
RDI2IS
C2
RW
RW
RDI2LT0
C3
RW
84
RW
RDI2LT1
C4
RW
ASD11CR1
85
RW
RDI2RO0
C5
RW
RW
ASD11CR2
86
RW
RDI2RO1
C6
RW
47
#
ASD11CR3
87
RW
RDI2DSM
C7
RW
48
#
ASC12CR0
88
RW
49
W
ASC12CR1
89
RW
C9
4A
RW
ASC12CR2
8A
RW
CA
C8
PRT2DM2
0B
RW
DCC22CR0
4B
#
ASC12CR3
8B
RW
CB
PRT3DR
0C
RW
DCC23DR0
4C
#
ASD13CR0
8C
RW
CC
PRT3IE
0D
RW
DCC23DR1
4D
W
ASD13CR1
8D
RW
CD
PRT3GS
0E
RW
DCC23DR2
4E
RW
ASD13CR2
8E
RW
CE
PRT3DM2
0F
RW
DCC23CR0
4F
#
ASD13CR3
8F
RW
PRT4DR
10
RW
50
ASD20CR0
90
RW
CUR_PP
D0
RW
PRT4IE
11
RW
51
ASD20CR1
91
RW
STK_PP
D1
RW
PRT4GS
12
RW
52
ASD20CR2
92
RW
PRT4DM2
13
RW
53
ASD20CR3
93
RW
IDX_PP
D3
RW
PRT5DR
14
RW
54
ASC21CR0
94
RW
MVR_PP
D4
RW
PRT5IE
15
RW
55
ASC21CR1
95
RW
MVW_PP
D5
RW
PRT5GS
16
RW
56
ASC21CR2
96
RW
I2C0_CFG
D6
RW
PRT5DM2
17
RW
57
ASC21CR3
97
RW
I2C0_SCR
D7
#
58
ASD22CR0
98
RW
I2C0_DR
D8
RW
19
59
ASD22CR1
99
RW
I2C0_MSCR
D9
#
1A
5A
ASD22CR2
9A
RW
INT_CLR0
DA
RW
18
CF
D2
1B
5B
ASD22CR3
9B
RW
INT_CLR1
DB
RW
1C
5C
ASC23CR0
9C
RW
INT_CLR2
DC
RW
1D
5D
ASC23CR1
9D
RW
INT_CLR3
DD
RW
1E
5E
ASC23CR2
9E
RW
INT_MSK3
DE
RW
1F
5F
ASC23CR3
9F
RW
INT_MSK2
DF
RW
DBC00DR0
20
#
AMX_IN
60
RW
DEC0_DH
A0
RC
INT_MSK0
E0
RW
DBC00DR1
DBC00DR2
21
W
AMUX_CFG
61
RW
DEC0_DL
A1
RC
INT_MSK1
E1
RW
22
RW
CLK_CR3
62
RW
DEC1_DH
A2
RC
INT_VC
E2
RC
DBC00CR0
23
#
ARF_CR
63
RW
DEC1_DL
A3
RC
RES_WDT
E3
W
DBC01DR0
24
#
CMP_CR0
64
#
DEC2_DH
A4
RC
I2C1_SCR
E4
#
DBC01DR1
25
W
ASY_CR
65
#
DEC2_DL
A5
RC
I2C1_MSCR
E5
#
DBC01DR2
26
RW
CMP_CR1
66
RW
DEC3_DH
A6
RC
DEC_CR0*
E6
RW
DBC01CR0
27
#
I2C1_DR
67
RW
DEC3_DL
A7
RC
DEC_CR1*
E7
RW
DCC02DR0
28
#
68
MUL1_X
A8
W
MUL0_X
E8
W
DCC02DR1
29
W
69
MUL1_Y
A9
W
MUL0_Y
E9
W
DCC02DR2
2A
RW
SADC_DH
6A
RW
MUL1_DH
AA
R
MUL0_DH
EA
R
DCC02CR0
2B
#
SADC_DL
6B
RW
MUL1_DL
AB
R
MUL0_DL
EB
R
DCC03DR0
2C
#
TMP_DR0
6C
RW
ACC1_DR1
AC
RW
ACC0_DR1
EC
RW
DCC03DR1
2D
W
TMP_DR1
6D
RW
ACC1_DR0
AD
RW
ACC0_DR0
ED
RW
DCC03DR2
2E
RW
TMP_DR2
6E
RW
ACC1_DR3
AE
RW
ACC0_DR3
EE
RW
DCC03CR0
2F
#
TMP_DR3
6F
RW
ACC1_DR2
AF
RW
ACC0_DR2
EF
RW
DBC10DR0
30
#
ACB00CR3
70
RW
RDI0RI
B0
RW
F0
DBC10DR1
31
W
ACB00CR0
71
RW
RDI0SYN
B1
RW
F1
DBC10DR2
32
RW
ACB00CR1
72
RW
RDI0IS
B2
RW
F2
DBC10CR0
33
#
ACB00CR2
73
RW
RDI0LT0
B3
RW
F3
DBC11DR0
34
#
ACB01CR3
74
RW
RDI0LT1
B4
RW
F4
DBC11DR1
35
W
ACB01CR0
75
RW
RDI0RO0
B5
RW
F5
DBC11DR2
36
RW
ACB01CR1
76
RW
RDI0RO1
B6
RW
DBC11CR0
37
#
ACB01CR2
77
RW
RDI0DSM
B7
RW
DCC12DR0
38
#
ACB02CR3
78
RW
RDI1RI
B8
RW
F6
CPU_F
F7
DCC12DR1
39
W
ACB02CR0
79
RW
RDI1SYN
B9
RW
F9
DCC12DR2
3A
RW
ACB02CR1
7A
RW
RDI1IS
BA
RW
FA
DCC12CR0
3B
#
ACB02CR2
7B
RW
RDI1LT0
BB
RW
FB
DCC13DR0
3C
#
ACB03CR3
7C
RW
RDI1LT1
BC
RW
FC
DCC13DR1
3D
W
ACB03CR0
7D
RW
RDI1RO0
BD
RW
DCC13DR2
3E
RW
ACB03CR1
7E
RW
RDI1RO1
BE
RW
DCC13CR0
3F
#
ACB03CR2
Blank fields are Reserved and should not be accessed.
Document Number: 001-48111 Rev. *K
7F
RW
# Access is bit specific.
RL
F8
FD
CPU_SCR1
RDI1DSM
BF
RW
CPU_SCR0
*Address has a dual purpose, see “Mapping Exceptions” on page 251
FE
#
FF
#
Page 26 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 17. CY8C28x43 Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
Addr (1,Hex)
00
Access
RW
PRT0DM1
01
RW
PRT0IC0
02
RW
PRT0IC1
03
PRT1DM0
Name
DBC20FN
Addr (1,Hex)
40
Access
RW
DBC20IN
41
RW
DBC20OU
42
RW
RW
DBC20CR1
43
RW
04
RW
DBC21FN
44
PRT1DM1
05
RW
DBC21IN
PRT1IC0
06
RW
PRT1IC1
07
PRT2DM0
Name
Addr (1,Hex)
80
Access
SADC_TSCMPL
81
RW
SADC_TSCMPH
82
RW
Name
RDI2RI
Addr (1,Hex)
C0
Access
RW
RDI2SYN
C1
RW
RDI2IS
C2
RW
83
RDI2LT0
C3
RW
RW
84
RDI2LT1
C4
RW
45
RW
85
RDI2RO0
C5
RW
DBC21OU
46
RW
86
RDI2RO1
C6
RW
RW
DBC21CR1
47
RW
87
RDI2DSM
C7
RW
08
RW
DCC22FN
48
RW
88
PRT2DM1
09
RW
DCC22IN
49
RW
89
C9
PRT2IC0
0A
RW
DCC22OU
4A
RW
8A
CA
C8
PRT2IC1
0B
RW
DCC22CR1
4B
RW
8B
CB
PRT3DM0
0C
RW
DCC23FN
4C
RW
8C
CC
PRT3DM1
0D
RW
DCC23IN
4D
RW
8D
CD
PRT3IC0
0E
RW
DCC23OU
4E
RW
8E
CE
PRT3IC1
0F
RW
DCC23CR1
4F
RW
8F
PRT4DM0
10
RW
50
PRT4DM1
11
RW
51
DEC0_CR0
91
PRT4IC0
12
RW
52
DEC_CR3
92
PRT4IC1
13
RW
53
PRT5DM0
14
RW
54
PRT5DM1
15
RW
55
DEC1_CR0
95
PRT5IC0
16
RW
56
DEC_CR4
96
PRT5IC1
17
RW
57
18
58
19
59
DEC2_CR0
99
1A
5A
DEC_CR5
9A
1B
5B
9B
1C
5C
9C
1D
5D
OSC_GO_EN
DD
RW
1E
5E
9E
OSC_CR4
DE
RW
1F
5F
9F
OSC_CR3
DF
RW
CF
90
DEC3_CR0
GDI_O_IN
D0
RW
RW
GDI_E_IN
D1
RW
RW
GDI_O_OU
D2
RW
93
GDI_E_OU
D3
RW
94
DEC0_CR
D4
RW
RW
DEC1_CR
D5
RW
RW
DEC2_CR
D6
RW
97
DEC3_CR
D7
RW
98
MUX_CR0
D8
RW
RW
MUX_CR1
D9
RW
RW
MUX_CR2
DA
RW
MUX_CR3
DB
RW
9D
DC
RW
DBC00FN
20
RW
CLK_CR0
60
RW
GDI_O_IN_CR
A0
RW
OSC_CR0
E0
RW
DBC00IN
21
RW
CLK_CR1
61
RW
GDI_E_IN_CR
A1
RW
OSC_CR1
E1
RW
DBC00OU
22
RW
ABF_CR0
62
RW
GDI_O_OU_CR
A2
RW
OSC_CR2
E2
RW
DBC00CR1
23
RW
AMD_CR0
63
RW
GDI_E_OU_CR
A3
RW
VLT_CR
E3
RW
DBC01FN
24
RW
CMP_GO_EN
64
RW
RTC_H
A4
RW
VLT_CMP
E4
RW
DBC01IN
25
RW
CMP_GO_EN1
65
RW
RTC_M
A5
RW
E5
DBC01OU
26
RW
AMD_CR1
66
RW
RTC_S
A6
RW
E6
DBC01CR1
27
RW
ALT_CR0
67
RW
RTC_CR
A7
RW
DCC02FN
28
RW
ALT_CR1
68
RW
SADC_CR0
A8
RW
IMO_TR
E8
RW
DCC02IN
29
RW
CLK_CR2
69
RW
SADC_CR1
A9
RW
ILO_TR
E9
RW
DCC02OU
2A
RW
AMUX_CFG1
6A
RW
SADC_CR2
AA
RW
BDG_TR
EA
RW
DCC02CR1
2B
RW
I2C1_CFG
6B
RW
SADC_CR3
AB
RW
ECO_TR
EB
RW
DCC03FN
2C
RW
TMP_DR0
6C
RW
SADC_CR4
AC
RW
MUX_CR4
EC
RW
DCC03IN
2D
RW
TMP_DR1
6D
RW
I2C0_ADDR
AD
RW
MUX_CR5
ED
RW
DCC03OU
2E
RW
TMP_DR2
6E
RW
I2C1_ADDR
AE
RW
EE
DCC03CR1
2F
RW
TMP_DR3
6F
RW
AMUX_CLK
AF
RW
EF
DBC10FN
30
RW
RDI0RI
B0
RW
F0
DBC10IN
31
RW
SADC_TSCR0
71
RW
RDI0SYN
B1
RW
F1
DBC10OU
32
RW
SADC_TSCR1
72
RW
RDI0IS
B2
RW
F2
DBC10CR1
33
RW
73
RDI0LT0
B3
RW
F3
DBC11FN
34
RW
74
RDI0LT1
B4
RW
F4
DBC11IN
35
RW
75
RDI0RO0
B5
RW
F5
DBC11OU
36
RW
76
RDI0RO1
B6
RW
DBC11CR1
37
RW
77
RDIODSM
B7
RW
DCC12FN
38
RW
78
RDI1RI
B8
RW
DCC12IN
39
RW
79
RDI1SYN
B9
RW
DCC12OU
3A
RW
7A
RDI1IS
BA
RW
DCC12CR1
3B
RW
7B
RDI1LT0
BB
RW
FB
DCC13FN
3C
RW
7C
RDI1LT1
BC
RW
FC
DCC13IN
3D
RW
7D
RDI1RO0
BD
RW
DCC13OU
3E
RW
7E
RDI1RO1
BE
RW
CPU_SCR1
FE
#
DCC13CR1
3F
RW
7F
RDI1DSM
BF
RW
CPU_SCR0
FF
#
70
Blank fields are Reserved and should not be accessed.
Document Number: 001-48111 Rev. *K
# Access is bit specific.
E7
F6
CPU_F
F7
RL
F8
F9
FLS_PR1
FA
RW
FD
*Address has a dual purpose, see “Mapping Exceptions” on page 251
Page 27 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 18. CY8C28x45 Register Map Bank 0 Table: User Space
Name
PRT0DR
Addr (0,Hex)
00
Access
RW
Name
DBC20DR0
Addr (0,Hex)
40
Access
#
Name
ASC10CR0
Addr (0,Hex)
80
Access
RW
PRT0IE
01
RW
DBC20DR1
PRT0GS
02
RW
DBC20DR2
41
W
ASC10CR1
81
RW
42
RW
ASC10CR2
82
RW
PRT0DM2
03
RW
DBC20CR0
43
#
ASC10CR3
83
PRT1DR
04
RW
DBC21DR0
44
#
ASD11CR0
PRT1IE
05
RW
DBC21DR1
45
W
PRT1GS
06
RW
DBC21DR2
46
PRT1DM2
07
RW
DBC21CR0
PRT2DR
08
RW
DCC22DR0
PRT2IE
09
RW
DCC22DR1
PRT2GS
0A
RW
DCC22DR2
Name
RDI2RI
Addr (0,Hex)
C0
Access
RW
RDI2SYN
C1
RW
RDI2IS
C2
RW
RW
RDI2LT0
C3
RW
84
RW
RDI2LT1
C4
RW
ASD11CR1
85
RW
RDI2RO0
C5
RW
RW
ASD11CR2
86
RW
RDI2RO1
C6
RW
47
#
ASD11CR3
87
RW
RDI2DSM
C7
RW
48
#
ASC12CR0
88
RW
49
W
ASC12CR1
89
RW
C9
4A
RW
ASC12CR2
8A
RW
CA
C8
PRT2DM2
0B
RW
DCC22CR0
4B
#
ASC12CR3
8B
RW
CB
PRT3DR
0C
RW
DCC23DR0
4C
#
ASD13CR0
8C
RW
CC
PRT3IE
0D
RW
DCC23DR1
4D
W
ASD13CR1
8D
RW
CD
PRT3GS
0E
RW
DCC23DR2
4E
RW
ASD13CR2
8E
RW
CE
PRT3DM2
0F
RW
DCC23CR0
4F
#
ASD13CR3
8F
RW
PRT4DR
10
RW
50
ASD20CR0
90
RW
CUR_PP
D0
RW
PRT4IE
11
RW
51
ASD20CR1
91
RW
STK_PP
D1
RW
PRT4GS
12
RW
52
ASD20CR2
92
RW
PRT4DM2
13
RW
53
ASD20CR3
93
RW
IDX_PP
D3
RW
PRT5DR
14
RW
54
ASC21CR0
94
RW
MVR_PP
D4
RW
PRT5IE
15
RW
55
ASC21CR1
95
RW
MVW_PP
D5
RW
PRT5GS
16
RW
56
ASC21CR2
96
RW
I2C0_CFG
D6
RW
PRT5DM2
17
RW
57
ASC21CR3
97
RW
I2C0_SCR
D7
#
58
ASD22CR0
98
RW
I2C0_DR
D8
RW
19
59
ASD22CR1
99
RW
I2C0_MSCR
D9
#
1A
5A
ASD22CR2
9A
RW
INT_CLR0
DA
RW
18
CF
D2
1B
5B
ASD22CR3
9B
RW
INT_CLR1
DB
RW
1C
5C
ASC23CR0
9C
RW
INT_CLR2
DC
RW
1D
5D
ASC23CR1
9D
RW
INT_CLR3
DD
RW
1E
5E
ASC23CR2
9E
RW
INT_MSK3
DE
RW
1F
5F
ASC23CR3
9F
RW
INT_MSK2
DF
RW
DBC00DR0
20
#
AMX_IN
60
RW
DEC0_DH
A0
RC
INT_MSK0
E0
RW
DBC00DR1
DBC00DR2
21
W
AMUX_CFG
61
RW
DEC0_DL
A1
RC
INT_MSK1
E1
RW
22
RW
CLK_CR3
62
RW
DEC1_DH
A2
RC
INT_VC
E2
RC
DBC00CR0
23
#
ARF_CR
63
RW
DEC1_DL
A3
RC
RES_WDT
E3
W
DBC01DR0
24
#
CMP_CR0
64
#
DEC2_DH
A4
RC
I2C1_SCR
E4
#
DBC01DR1
25
W
ASY_CR
65
#
DEC2_DL
A5
RC
I2C1_MSCR
E5
#
DBC01DR2
26
RW
CMP_CR1
66
RW
DEC3_DH
A6
RC
DEC_CR0*
E6
RW
DBC01CR0
27
#
I2C1_DR
67
RW
DEC3_DL
A7
RC
DEC_CR1*
E7
RW
DCC02DR0
28
#
68
MUL1_X
A8
W
MUL0_X
E8
W
DCC02DR1
29
W
69
MUL1_Y
A9
W
MUL0_Y
E9
W
DCC02DR2
2A
RW
SADC_DH
6A
RW
MUL1_DH
AA
R
MUL0_DH
EA
R
DCC02CR0
2B
#
SADC_DL
6B
RW
MUL1_DL
AB
R
MUL0_DL
EB
R
DCC03DR0
2C
#
TMP_DR0
6C
RW
ACC1_DR1
AC
RW
ACC0_DR1
EC
RW
DCC03DR1
2D
W
TMP_DR1
6D
RW
ACC1_DR0
AD
RW
ACC0_DR0
ED
RW
DCC03DR2
2E
RW
TMP_DR2
6E
RW
ACC1_DR3
AE
RW
ACC0_DR3
EE
RW
DCC03CR0
2F
#
TMP_DR3
6F
RW
ACC1_DR2
AF
RW
ACC0_DR2
EF
RW
DBC10DR0
30
#
ACB00CR3
70
RW
RDI0RI
B0
RW
F0
DBC10DR1
31
W
ACB00CR0
71
RW
RDI0SYN
B1
RW
F1
DBC10DR2
32
RW
ACB00CR1
72
RW
RDI0IS
B2
RW
F2
DBC10CR0
33
#
ACB00CR2
73
RW
RDI0LT0
B3
RW
F3
DBC11DR0
34
#
ACB01CR3
74
RW
RDI0LT1
B4
RW
F4
DBC11DR1
35
W
ACB01CR0
75
RW
RDI0RO0
B5
RW
F5
DBC11DR2
36
RW
ACB01CR1
76
RW
RDI0RO1
B6
RW
DBC11CR0
37
#
ACB01CR2
77
RW
RDI0DSM
B7
RW
DCC12DR0
38
#
ACB02CR3
78
RW
RDI1RI
B8
RW
F6
CPU_F
F7
RL
F8
DCC12DR1
39
W
ACB02CR0
79
RW
RDI1SYN
B9
RW
F9
DCC12DR2
3A
RW
ACB02CR1
7A
RW
RDI1IS
BA
RW
FA
DCC12CR0
3B
#
ACB02CR2
7B
RW
RDI1LT0
BB
RW
DCC13DR0
3C
#
ACB03CR3
7C
RW
RDI1LT1
BC
RW
DAC1_D
FC
RW
DCC13DR1
3D
W
ACB03CR0
7D
RW
RDI1RO0
BD
RW
DAC0_D
FD
RW
DCC13DR2
3E
RW
ACB03CR1
7E
RW
RDI1RO1
BE
RW
CPU_SCR1
FE
#
FF
#
DCC13CR0
3F
#
ACB03CR2
Blank fields are Reserved and should not be accessed.
Document Number: 001-48111 Rev. *K
7F
RW
# Access is bit specific.
FB
RDI1DSM
BF
RW
CPU_SCR0
*Address has a dual purpose, see “Mapping Exceptions” on page 251
Page 28 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 19. CY8C28x45 Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
Addr (1,Hex)
00
Access
RW
PRT0DM1
01
RW
PRT0IC0
02
RW
PRT0IC1
03
PRT1DM0
Name
DBC20FN
Addr (1,Hex)
40
Access
RW
DBC20IN
41
RW
DBC20OU
42
RW
RW
DBC20CR1
43
RW
04
RW
DBC21FN
44
RW
PRT1DM1
05
RW
DBC21IN
45
RW
PRT1IC0
06
RW
DBC21OU
46
PRT1IC1
07
RW
DBC21CR1
PRT2DM0
08
RW
DCC22FN
PRT2DM1
09
RW
PRT2IC0
0A
RW
Name
Addr (1,Hex)
80
Access
RW
SADC_TSCMPL
81
RW
SADC_TSCMPH
82
RW
ACE_AMD_CR1
83
Name
RDI2RI
Addr (1,Hex)
C0
Access
RW
RDI2SYN
C1
RW
RDI2IS
C2
RW
RW
RDI2LT0
C3
RW
84
RW
RDI2LT1
C4
RW
ACE_PWM_CR
85
RW
RDI2RO0
C5
RW
RW
ACE_ADC0_CR
86
RW
RDI2RO1
C6
RW
47
RW
ACE_ADC1_CR
87
RW
RDI2DSM
C7
RW
48
RW
88
RW
DCC22IN
49
RW
ACE_CLK_CR0
89
RW
C9
DCC22OU
4A
RW
ACE_CLK_CR1
8A
RW
CA
ACE_CLK_CR3
8B
RW
CB
8C
RW
CC
C8
PRT2IC1
0B
RW
DCC22CR1
4B
RW
PRT3DM0
0C
RW
DCC23FN
4C
RW
PRT3DM1
0D
RW
DCC23IN
4D
RW
ACE01CR1
8D
RW
CD
PRT3IC0
0E
RW
DCC23OU
4E
RW
ACE01CR2
8E
RW
CE
PRT3IC1
0F
RW
DCC23CR1
4F
RW
ASE11CR0
8F
RW
PRT4DM0
10
RW
50
PRT4DM1
11
RW
51
DEC0_CR0
91
PRT4IC0
12
RW
52
DEC_CR3
92
PRT4IC1
13
RW
53
PRT5DM0
14
RW
54
PRT5DM1
15
RW
55
DEC1_CR0
95
PRT5IC0
16
RW
56
DEC_CR4
96
PRT5IC1
17
RW
57
18
58
19
59
DEC2_CR0
99
1A
5A
DEC_CR5
9A
1B
5B
1C
5C
1D
5D
1E
5E
9E
1F
5F
9F
90
DEC3_CR0
CF
GDI_O_IN
D0
RW
RW
GDI_E_IN
D1
RW
RW
GDI_O_OU
D2
RW
93
GDI_E_OU
D3
RW
94
DEC0_CR
D4
RW
RW
DEC1_CR
D5
RW
RW
DEC2_CR
D6
RW
97
DEC3_CR
D7
RW
98
MUX_CR0
D8
RW
RW
MUX_CR1
D9
RW
RW
MUX_CR2
DA
RW
9B
MUX_CR3
DB
RW
9C
IDAC_CR1
DC
RW
OSC_GO_EN
DD
RW
OSC_CR4
DE
RW
OSC_CR3
DF
RW
9D
RW
DBC00FN
20
RW
CLK_CR0
60
RW
GDI_O_IN_CR
A0
RW
OSC_CR0
E0
RW
DBC00IN
21
RW
CLK_CR1
61
RW
GDI_E_IN_CR
A1
RW
OSC_CR1
E1
RW
DBC00OU
22
RW
ABF_CR0
62
RW
GDI_O_OU_CR
A2
RW
OSC_CR2
E2
RW
DBC00CR1
23
RW
AMD_CR0
63
RW
GDI_E_OU_CR
A3
RW
VLT_CR
E3
RW
DBC01FN
24
RW
CMP_GO_EN
64
RW
RTC_H
A4
RW
VLT_CMP
E4
RW
DBC01IN
25
RW
CMP_GO_EN1
65
RW
RTC_M
A5
RW
ADC0_TR
E5
RW
DBC01OU
26
RW
AMD_CR1
66
RW
RTC_S
A6
RW
ADC1_TR
E6
RW
DBC01CR1
27
RW
ALT_CR0
67
RW
RTC_CR
A7
RW
IDAC_CR2
E7
RW
DCC02FN
28
RW
ALT_CR1
68
RW
SADC_CR0
A8
RW
IMO_TR
E8
RW
DCC02IN
29
RW
CLK_CR2
69
RW
SADC_CR1
A9
RW
ILO_TR
E9
RW
DCC02OU
2A
RW
AMUX_CFG1
6A
RW
SADC_CR2
AA
RW
BDG_TR
EA
RW
DCC02CR1
2B
RW
I2C1_CFG
6B
RW
SADC_CR3
AB
RW
ECO_TR
EB
RW
DCC03FN
2C
RW
TMP_DR0
6C
RW
SADC_CR4
AC
RW
MUX_CR4
EC
RW
DCC03IN
2D
RW
TMP_DR1
6D
RW
I2C0_ADDR
AD
RW
MUX_CR5
ED
RW
DCC03OU
2E
RW
TMP_DR2
6E
RW
I2C1_ADDR
AE
RW
EE
DCC03CR1
2F
RW
TMP_DR3
6F
RW
AMUX_CLK
AF
RW
EF
DBC10FN
30
RW
RDI0RI
B0
RW
F0
DBC10IN
31
RW
SADC_TSCR0
71
RW
RDI0SYN
B1
RW
F1
DBC10OU
32
RW
SADC_TSCR1
72
RW
RDI0IS
B2
RW
F2
DBC10CR1
33
RW
ACE_AMD_CR0
73
RW
RDI0LT0
B3
RW
F3
DBC11FN
34
RW
RDI0LT1
B4
RW
F4
DBC11IN
35
RW
ACE_AMX_IN
75
RW
RDI0RO0
B5
RW
F5
DBC11OU
36
RW
ACE_CMP_CR0
76
RW
RDI0RO1
B6
RW
DBC11CR1
37
RW
ACE_CMP_CR1
77
RW
RDIODSM
B7
RW
DCC12FN
38
RW
RDI1RI
B8
RW
DCC12IN
39
RW
ACE_CMP_GI_EN
79
RW
RDI1SYN
B9
RW
DCC12OU
3A
RW
ACE_ALT_CR0
7A
RW
RDI1IS
BA
RW
DCC12CR1
3B
RW
ACE_ABF_CR0
7B
RW
RDI1LT0
BB
RW
DCC13FN
3C
RW
RDI1LT1
BC
RW
DCC13IN
3D
RW
ACE0_CR1
7D
RW
RDI1RO0
BD
RW
IDAC_CR0
FD
RW
DCC13OU
3E
RW
ACE0_CR2
7E
RW
RDI1RO1
BE
RW
CPU_SCR1
FE
#
DCC13CR1
3F
RW
ACE0_CR3
7F
RW
RDI1DSM
BF
RW
CPU_SCR0
FF
#
70
74
78
7C
Blank fields are Reserved and should not be accessed.
Document Number: 001-48111 Rev. *K
# Access is bit specific.
F6
CPU_F
F7
RL
F8
F9
FLS_PR1
FA
RW
FB
FC
*Address has a dual purpose, see “Mapping Exceptions” on page 251
Page 29 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 20. CY8C28x52 Register Map Bank 0 Table: User Space
Name
PRT0DR
Addr (0,Hex)
00
Access
RW
PRT0IE
01
RW
PRT0GS
02
RW
PRT0DM2
03
PRT1DR
Name
Addr (0,Hex)
40
Access
Name
ASC10CR0
Addr (0,Hex)
80
Access
RW
Name
Addr (0,Hex)
C0
41
ASC10CR1
81
RW
C1
42
ASC10CR2
82
RW
C2
RW
43
ASC10CR3
83
RW
C3
04
RW
44
ASD11CR0
84
RW
C4
PRT1IE
05
RW
45
ASD11CR1
85
RW
C5
PRT1GS
06
RW
46
ASD11CR2
86
RW
C6
PRT1DM2
07
RW
47
ASD11CR3
87
RW
C7
PRT2DR
08
RW
48
ASC12CR0
88
RW
C8
PRT2IE
09
RW
49
ASC12CR1
89
RW
C9
PRT2GS
0A
RW
4A
ASC12CR2
8A
RW
CA
Access
PRT2DM2
0B
RW
4B
ASC12CR3
8B
RW
CB
PRT3DR
0C
RW
4C
ASD13CR0
8C
RW
CC
PRT3IE
0D
RW
4D
ASD13CR1
8D
RW
CD
PRT3GS
0E
RW
4E
ASD13CR2
8E
RW
CE
PRT3DM2
0F
RW
4F
ASD13CR3
8F
RW
PRT4DR
10
RW
50
ASD20CR0
90
RW
CUR_PP
D0
RW
PRT4IE
11
RW
51
ASD20CR1
91
RW
STK_PP
D1
RW
PRT4GS
12
RW
52
ASD20CR2
92
RW
PRT4DM2
13
RW
53
ASD20CR3
93
RW
IDX_PP
D3
RW
PRT5DR
14
RW
54
ASC21CR0
94
RW
MVR_PP
D4
RW
PRT5IE
15
RW
55
ASC21CR1
95
RW
MVW_PP
D5
RW
PRT5GS
16
RW
56
ASC21CR2
96
RW
I2C0_CFG
D6
RW
PRT5DM2
17
RW
57
ASC21CR3
97
RW
I2C0_SCR
D7
#
58
ASD22CR0
98
RW
I2C0_DR
D8
RW
19
59
ASD22CR1
99
RW
I2C0_MSCR
D9
#
1A
5A
ASD22CR2
9A
RW
INT_CLR0
DA
RW
18
CF
D2
1B
5B
ASD22CR3
9B
RW
INT_CLR1
DB
RW
1C
5C
ASC23CR0
9C
RW
INT_CLR2
DC
RW
1D
5D
ASC23CR1
9D
RW
INT_CLR3
DD
RW
1E
5E
ASC23CR2
9E
RW
INT_MSK3
DE
RW
1F
5F
ASC23CR3
9F
RW
INT_MSK2
DF
RW
DBC00DR0
20
#
AMX_IN
60
RW
DEC0_DH
A0
RC
INT_MSK0
E0
RW
DBC00DR1
DBC00DR2
21
W
AMUX_CFG
61
RW
DEC0_DL
A1
RC
INT_MSK1
E1
RW
22
RW
CLK_CR3
62
RW
DEC1_DH
A2
RC
INT_VC
E2
RC
DBC00CR0
23
#
ARF_CR
63
RW
DEC1_DL
A3
RC
RES_WDT
E3
W
DBC01DR0
24
#
CMP_CR0
64
#
DEC2_DH
A4
RC
DBC01DR1
25
W
ASY_CR
65
#
DEC2_DL
A5
RC
DBC01DR2
26
RW
CMP_CR1
66
RW
DEC3_DH
A6
RC
DEC_CR0*
E6
RW
DBC01CR0
27
#
67
DEC3_DL
A7
RC
DEC_CR1*
E7
RW
DCC02DR0
28
#
68
MUL1_X
A8
W
MUL0_X
E8
W
DCC02DR1
29
W
69
MUL1_Y
A9
W
MUL0_Y
E9
W
DCC02DR2
2A
RW
6A
MUL1_DH
AA
R
MUL0_DH
EA
R
DCC02CR0
2B
#
6B
MUL1_DL
AB
R
MUL0_DL
EB
R
DCC03DR0
2C
#
TMP_DR0
6C
RW
ACC1_DR1
AC
RW
ACC0_DR1
EC
RW
DCC03DR1
2D
W
TMP_DR1
6D
RW
ACC1_DR0
AD
RW
ACC0_DR0
ED
RW
DCC03DR2
2E
RW
TMP_DR2
6E
RW
ACC1_DR3
AE
RW
ACC0_DR3
EE
RW
DCC03CR0
2F
#
TMP_DR3
6F
RW
ACC1_DR2
AF
RW
ACC0_DR2
EF
RW
DBC10DR0
30
#
ACB00CR3
70
RW
RDI0RI
B0
RW
F0
DBC10DR1
31
W
ACB00CR0
71
RW
RDI0SYN
B1
RW
F1
DBC10DR2
32
RW
ACB00CR1
72
RW
RDI0IS
B2
RW
F2
DBC10CR0
33
#
ACB00CR2
73
RW
RDI0LT0
B3
RW
F3
DBC11DR0
34
#
ACB01CR3
74
RW
RDI0LT1
B4
RW
F4
DBC11DR1
35
W
ACB01CR0
75
RW
RDI0RO0
B5
RW
F5
DBC11DR2
36
RW
ACB01CR1
76
RW
RDI0RO1
B6
RW
DBC11CR0
37
#
ACB01CR2
77
RW
RDI0DSM
B7
RW
DCC12DR0
38
#
ACB02CR3
78
RW
RDI1RI
B8
RW
E4
E5
F6
CPU_F
F7
RL
F8
DCC12DR1
39
W
ACB02CR0
79
RW
RDI1SYN
B9
RW
F9
DCC12DR2
3A
RW
ACB02CR1
7A
RW
RDI1IS
BA
RW
FA
DCC12CR0
3B
#
ACB02CR2
7B
RW
RDI1LT0
BB
RW
DCC13DR0
3C
#
ACB03CR3
7C
RW
RDI1LT1
BC
RW
DAC1_D
FC
RW
DCC13DR1
3D
W
ACB03CR0
7D
RW
RDI1RO0
BD
RW
DAC0_D
FD
RW
DCC13DR2
3E
RW
ACB03CR1
7E
RW
RDI1RO1
BE
RW
CPU_SCR1
FE
#
FF
#
DCC13CR0
3F
#
ACB03CR2
Blank fields are Reserved and should not be accessed.
Document Number: 001-48111 Rev. *K
7F
RW
# Access is bit specific.
FB
RDI1DSM
BF
RW
CPU_SCR0
*Address has a dual purpose, see “Mapping Exceptions” on page 251
Page 30 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 21. CY8C28x52 Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
Addr (1,Hex)
00
Access
RW
Name
Addr (1,Hex)
40
Access
Name
PRT0DM1
01
RW
41
81
PRT0IC0
02
RW
42
82
PRT0IC1
03
RW
43
PRT1DM0
04
RW
44
PRT1DM1
05
RW
45
ACE_PWM_CR
85
RW
C5
PRT1IC0
06
RW
46
ACE_ADC0_CR
86
RW
C6
PRT1IC1
07
RW
47
ACE_ADC1_CR
87
RW
C7
PRT2DM0
08
RW
48
PRT2DM1
09
RW
49
ACE_CLK_CR0
89
RW
C9
PRT2IC0
0A
RW
4A
ACE_CLK_CR1
8A
RW
CA
ACE_CLK_CR3
8B
RW
ACE_AMD_CR1
Addr (1,Hex)
80
83
Access
Name
Addr (1,Hex)
C0
C1
C2
RW
C3
84
C4
88
C8
PRT2IC1
0B
RW
4B
PRT3DM0
0C
RW
4C
CB
PRT3DM1
0D
RW
4D
ACE01CR1
8D
RW
CD
PRT3IC0
0E
RW
4E
ACE01CR2
8E
RW
CE
PRT3IC1
0F
RW
4F
ASE11CR0
8F
RW
PRT4DM0
10
RW
50
PRT4DM1
11
RW
51
DEC0_CR0
91
PRT4IC0
12
RW
52
DEC_CR3
92
PRT4IC1
13
RW
53
PRT5DM0
14
RW
54
PRT5DM1
15
RW
55
DEC1_CR0
95
PRT5IC0
16
RW
56
DEC_CR4
96
PRT5IC1
17
RW
57
18
58
19
59
DEC2_CR0
99
1A
5A
DEC_CR5
9A
1B
5B
1C
5C
1D
5D
1E
5E
9E
1F
5F
9F
8C
CC
90
DEC3_CR0
Access
CF
GDI_O_IN
D0
RW
RW
GDI_E_IN
D1
RW
RW
GDI_O_OU
D2
RW
93
GDI_E_OU
D3
RW
94
DEC0_CR
D4
RW
RW
DEC1_CR
D5
RW
RW
DEC2_CR
D6
RW
97
DEC3_CR
D7
RW
98
MUX_CR0
D8
RW
RW
MUX_CR1
D9
RW
RW
MUX_CR2
DA
RW
9B
MUX_CR3
DB
RW
9C
IDAC_CR1
DC
RW
OSC_GO_EN
DD
RW
OSC_CR4
DE
RW
OSC_CR3
DF
RW
9D
RW
DBC00FN
20
RW
CLK_CR0
60
RW
GDI_O_IN_CR
A0
RW
OSC_CR0
E0
RW
DBC00IN
21
RW
CLK_CR1
61
RW
GDI_E_IN_CR
A1
RW
OSC_CR1
E1
RW
DBC00OU
22
RW
ABF_CR0
62
RW
GDI_O_OU_CR
A2
RW
OSC_CR2
E2
RW
DBC00CR1
23
RW
AMD_CR0
63
RW
GDI_E_OU_CR
A3
RW
VLT_CR
E3
RW
DBC01FN
24
RW
CMP_GO_EN
64
RW
RTC_H
A4
RW
VLT_CMP
E4
RW
DBC01IN
25
RW
CMP_GO_EN1
65
RW
RTC_M
A5
RW
ADC0_TR
E5
RW
DBC01OU
26
RW
AMD_CR1
66
RW
RTC_S
A6
RW
ADC1_TR
E6
RW
DBC01CR1
27
RW
ALT_CR0
67
RW
RTC_CR
A7
RW
IDAC_CR2
E7
RW
DCC02FN
28
RW
ALT_CR1
68
RW
A8
IMO_TR
E8
RW
DCC02IN
29
RW
CLK_CR2
69
RW
A9
ILO_TR
E9
RW
DCC02OU
2A
RW
AMUX_CFG1
6A
RW
AA
BDG_TR
EA
RW
DCC02CR1
2B
RW
AB
ECO_TR
EB
RW
DCC03FN
2C
RW
TMP_DR0
6C
RW
AC
MUX_CR4
EC
RW
DCC03IN
2D
RW
TMP_DR1
6D
RW
MUX_CR5
ED
RW
DCC03OU
2E
RW
TMP_DR2
6E
RW
DCC03CR1
2F
RW
TMP_DR3
6F
RW
AMUX_CLK
AF
RW
EF
DBC10FN
30
RW
70
RDI0RI
B0
RW
F0
DBC10IN
31
RW
71
RDI0SYN
B1
RW
F1
DBC10OU
32
RW
72
RDI0IS
B2
RW
F2
DBC10CR1
33
RW
RDI0LT0
B3
RW
F3
DBC11FN
34
RW
RDI0LT1
B4
RW
F4
DBC11IN
35
RW
ACE_AMX_IN
75
RW
RDI0RO0
B5
RW
F5
DBC11OU
36
RW
ACE_CMP_CR0
76
RW
RDI0RO1
B6
RW
DBC11CR1
37
RW
ACE_CMP_CR1
77
RW
RDIODSM
B7
RW
DCC12FN
38
RW
RDI1RI
B8
RW
DCC12IN
39
RW
ACE_CMP_GI_EN
79
RW
RDI1SYN
B9
RW
DCC12OU
3A
RW
ACE_ALT_CR0
7A
RW
RDI1IS
BA
RW
DCC12CR1
3B
RW
ACE_ABF_CR0
7B
RW
RDI1LT0
BB
RW
DCC13FN
3C
RW
RDI1LT1
BC
RW
DCC13IN
3D
RW
ACE0_CR1
7D
RW
RDI1RO0
BD
RW
IDAC_CR0
FD
RW
DCC13OU
3E
RW
ACE0_CR2
7E
RW
RDI1RO1
BE
RW
CPU_SCR1
FE
#
DCC13CR1
3F
RW
ACE0_CR3
7F
RW
RDI1DSM
BF
RW
CPU_SCR0
FF
#
6B
ACE_AMD_CR0
73
RW
74
78
7C
Blank fields are Reserved and should not be accessed.
Document Number: 001-48111 Rev. *K
# Access is bit specific.
I2C0_ADDR
AD
RW
AE
EE
F6
CPU_F
F7
RL
F8
F9
FLS_PR1
FA
RW
FB
FC
*Address has a dual purpose, see “Mapping Exceptions” on page 251
Page 31 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C28xxx PSoC devices. For the most up to date electrical
specifications, confirm that you have the most recent datasheet by going to the web at http//www.cypress.com.
Specifications are valid for -40oC  TA  85°C and TJ  100°C, except where noted. Specifications for devices running at greater than
12 MHz are valid for -40°C  TA  70°C and TJ  82°C.
Figure 7. Voltage versus CPU Frequency
5.25
Vdd Voltage
lid ing
Va rat on
pe i
O R eg
4.75
3.00
93 kHz
12 MHz
24 MHz
CPU Frequency
Document Number: 001-48111 Rev. *K
Page 32 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Absolute Maximum Ratings
Table 22. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage temperature
TBAKETEMP Bake temperature
tBAKETIME
Bake time
TA
VDD
VIO
VIOZ
IMIO
IMAIO
Ambient temperature with power applied
Supply voltage on VDD relative to VSS
DC input voltage
DC voltage applied to tri-state
Maximum current into any port pin
Maximum current into any port pin
configured as analog driver
Electro static discharge voltage
Latch up current
ESD
LU
Min
-55
Typ
25
Max
+100
Units
°C
-
125
See
package
label
-40
-0.5
VSS- 0.5
VSS – 0.5
-25
-50
-
See
Package
label
72
Hours
–
–
–
–
–
–
+85
+6.0
VDD + 0.5
VDD + 0.5
+50
+50
°C
V
V
V
mA
mA
2000
–
–
–
–
200
V
mA
Min
-40
-40
Typ
–
–
Max
+85
+100
Units
°C
°C
o
Notes
Higher storage temperatures
reduce data retention time.
Recommended storage temperature is +25°C ± 25°C. Extended
duration storage temperatures
above 65°C degrade reliability.
C
Human Body Model ESD.
Operating Temperature
Table 23. Operating Temperature
Symbol
TA
TJ
Description
Ambient temperature
Junction temperature
Document Number: 001-48111 Rev. *K
Notes
The temperature rise from
ambient to junction is package
specific. See Thermal Impedances on page 66. The user must
limit the power consumption to
comply with this requirement.
Page 33 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
DC Electrical Characteristics
DC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40°C  TA  85°C, or 3.0 V to 3.6 V and –40°C  TA  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and
are for design guidance only.
Table 24. DC Chip Level Specifications
Symbol
Description
VDD
Supply voltage
IDD
Supply current
Min
3.00
–
Typ
–
8
Max
5.25
14
Units
V
mA
IDD3
Supply current
–
5
9
mA
IDDP
Supply current when IMO = 6 MHz using
SLIMO mode=1
–
2
3
mA
ISB
Sleep (Mode) current with POR, LVD, sleep
timer, and WDT.[15]
–
3
10
A
ISBH
Sleep (Mode) current with POR, LVD, sleep
timer, and WDT at high temperature.[15]
–
4
25
A
ISBXTL
Sleep (Mode) Current with POR, LVD, sleep
timer, WDT, and external crystal.[15]
–
4
13
A
ISBXTLH
Sleep (Mode) current with POR, LVD, sleep
timer, WDT, and external crystal at high
temperature.[15]
Current consumed by RTC during sleep
–
5
26
A
–
0.5
1
µA
1.280
–
-
1.300
0.65
0.4
1.320
3
1.5
V
mA
mA
ISBRTC
VREF
ISXRES
Reference voltage (Bandgap)
Supply current with XRES asserted 5 V
Supply current with XRES asserted 3.3 V
Notes
Conditions are VDD = 5.0 V, TA = 25
°C, CPU = 3 MHz, SYSCLK doubler
disabled. VC1 = 1.5 MHz, VC2 = 93.75
kHz, VC3 = 93.75 kHz.
Conditions are VDD = 3.3 V, TA = 25
°C, CPU = 3 MHz, SYSCLK doubler
disabled. VC1 = 1.5 MHz, VC2 = 93.75
kHz, VC3 = 93.75 kHz.
Conditions are VDD = 3.3 V, TA = 25
°C, CPU = 0.75 MHz, SYSCLK
doubler disabled, VC1 = 0.375 MHz,
VC2 = 23.44 kHz, VC3 = 0.09 kHz.
Conditions are with internal slow
speed oscillator, VDD = 3.3 V, –40 °C
 TA  55 °C.
Conditions are with internal slow
speed oscillator, VDD = 3.3 V, 55 °C <
TA  85 °C.
Conditions are with properly loaded, 1
W max, 32.768 kHz crystal. VDD =
3.3 V, –40 °C  TA  55 °C.
Conditions are with properly loaded, 1
W max, 32.768 kHz crystal. VDD =
3.3 V, 55 °C < TA  85 °C.
Extra current consumed by the RTC
during sleep. This number is typical at
25 °C and 5 V.
Trimmed for appropriate VDD.
Max is peak current after XRES;
Typical value is the steady state
current value. TA = 25 °C.
Note
15. Standby (sleep) current includes all functions (POR, LVD, WDT, Sleep Timer) needed for reliable system operation. This should be compared with devices that have
similar functions enabled.
Document Number: 001-48111 Rev. *K
Page 34 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
DC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 25. DC GPIO Specifications
Symbol
RPU
RPD
VOH
Description
Pull-up resistor
Pull-down resistor
High output level
Min
4
4
VDD – 1.0
Typ
5.6
5.6
–
Max
8
8
–
VOL
Low output level
–
–
0.75
IOH
High level source current
10
–
–
IOL
Low level sink current
25
–
–
VIL
VIH
VH
IIL
CIN
Input low level
Input high level
Input hysteresis
Input leakage (absolute value)
Capacitive load on pins as input
–
2.1
–
–
–
–
–
60
1
3.5
0.8
–
–
–
10
COUT
Capacitive load on pins as output
–
3.5
10
Document Number: 001-48111 Rev. *K
Units
Notes
k
k
V
IOH = 10 mA, VDD = 4.75 to 5.25 V
(8 total loads, 4 on even port pins
(for example, P0[2], P1[4]), 4 on odd
port pins (for example, P0[3],
P1[5])). 80 mA maximum combined
IOH budget.
V
IOL = 25 mA, VDD = 4.75 to 5.25 V
(8 total loads, 4 on even port pins
(for example, P0[2], P1[4]), 4 on odd
port pins (for example, P0[3],
P1[5])). 150 mA maximum
combined IOL budget.
mA VOH = VDD – 1.0 V, see the limitations of the total current in the note
for VOH.
mA
VOL = 0.75 V, see the limitations of
the total current in the note for VOL.
V
VDD = 3.0 to 5.25.
V
VDD = 3.0 to 5.25.
mV
nA Gross tested to 1 A.
pF
Package and pin dependent. Temp
= 25 °C.
pF
Package and pin dependent. Temp
= 25 °C.
Page 35 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only. The Operational Amplifiers covered by these specifications are components of both the Analog
Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog
Continuous Time PSoC block.
Table 26. 5 V DC Operational Amplifier Specifications
Symbol
VOSOACT
Description
Input Offset Voltage CT Block (absolute value)
Power = Low, Opamp bias = High
Power = Medium, Opamp bias = High
Power = High, Opamp bias = High
VOSOA
Input Offset Voltage SC and AGND Opamps
(absolute value)
TCVOSOA Average Input Offset Voltage Drift
IEBOA
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
CINOA
Min
Typ
Max
Units
–
–
–
–
1.6
1.3
1.2
1
8
8
8
6
mV
mV
mV
mV
–
–
–
7.0
200
4.5
35.0
–
9.5
VCMOA
0.0
0.5
–
–
VDD
VDD –
0.5
60
60
60
–
–
–
–
–
–
dB
dB
dB
60
60
80
–
–
–
–
–
–
dB
dB
dB
VDD – 0.2
VDD – 0.2
VDD – 0.5
–
–
–
–
–
–
V
V
V
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
–
–
–
–
–
–
60
200
400
700
1400
2400
4600
–
300
600
1100
2000
3600
7700
–
A
A
A
A
A
A
dB
Common Mode Voltage Range
Common Mode Voltage Range (high power or
high Opamp bias)
CMRROA
Common Mode Rejection Ratio
Power = Low
Power = Medium
Power = High
GOLOA
Open Loop Gain
Power = Low
Power = Medium
Power = High
VOHIGHOA High Output Voltage Swing (internal signals)
Power = Low
Power = Medium
Power = High
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low
Power = Medium
Power = High
ISOA
PSRROA
Supply Current (including associated AGND
buffer)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = Medium, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
Supply Voltage Rejection Ratio
Document Number: 001-48111 Rev. *K
Notes
Applies to High and Low Opamp
bias.
V/°C
pA
Gross tested to 1 A.
pF
Package and pin dependent.
Temp = 25 °C.
V
The common-mode input
V
voltage range is measured
through an analog output buffer.
The specification includes the
limitations imposed by the
characteristics of the analog
output buffer.
VSS  VIN  (VDD – 2.25) or
(VDD – 1.25 V)  VIN  VDD.
Page 36 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 27. 3.3 V DC Operational Amplifier Specifications
Symbol
VOSOACT
Description
Input Offset Voltage CT Blocks (absolute value)
Power = Low, Opamp bias = High
Power = Medium, Opamp bias = High
Power = High, Opamp bias = High
VOSOA
Input Offset Voltage SC and AGND (absolute
value)
TCVOSOA Average Input Offset Voltage Drift
IEBOA
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
CINOA
Min
Typ
Max
Units
–
–
–
–
1.65
1.32
–
1
8
8
–
6
mV
mV
mV
mV
–
–
–
7.0
200
4.5
35.0
–
9.5
VCMOA
0.2
–
VDD –
0.2
50
50
50
–
–
–
–
–
–
dB
dB
dB
60
60
80
–
–
–
–
–
–
dB
dB
dB
VDD –
0.2
VDD –
0.2
VDD –
0.2
–
–
–
–
–
–
V
V
V
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
–
–
–
–
–
–
50
200
400
700
1400
2400
4600
80
300
600
1000
2000
3600
7500
–
A
A
A
A
A
A
dB
Common Mode Voltage Range
CMRROA Common Mode Rejection Ratio
Power = Low
Power = Medium
Power = High
GOLOA
Open Loop Gain
Power = Low
Power = Medium
Power = High
VOHIGHOA High Output Voltage Swing (internal signals)
Power = Low
Power = Medium
Power = High is 5 V only
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low
Power = Medium
Power = High
ISOA
Supply Current (including associated AGND
buffer)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = Medium, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
PSRROA Supply Voltage Rejection Ratio
Document Number: 001-48111 Rev. *K
Notes
Applies to High and Low Opamp
bias.
V/°C
pA
Gross tested to 1 A.
pF
Package and pin dependent.
Temp = 25 °C.
V
The common-mode input
voltage range is measured
through an analog output buffer.
The specification includes the
limitations imposed by the
characteristics of the analog
output buffer.
VSS  VIN  (VDD – 2.25 V) or
(VDD – 1.25 V)  VIN  VDD.
Page 37 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
DC Type-E Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only. The Operational Amplifiers covered by these specifications are components of the Limited Type E
Analog PSoC blocks.
Table 28. 5 V DC Type-E Operational Amplifier Specifications
Symbol
Description
Input offset voltage (absolute value)
VOSOA
Min
–
–
Typ
2.5
2.5
Max
15
20
Units
mV
mV
–
–
–
10
200
4.5
–
–
9.5
0.0
–
–
10
VDD
30
V/°C
nA
Gross tested to 1 A.
pF
Package and pin dependent. Temp
= 25 °C.
V
A
Min
–
–
Typ
2.5
2.5
Max
15
20
TCVOSOA Average input offset voltage drift
IEBOA[16] Input leakage current (Port 0 Analog Pins)
Input capacitance (Port 0 Analog Pins)
CINOA
–
–
–
10
200
4.5
–
–
9.5
VCMOA
ISOA
0
–
–
10
VDD
30
TCVOSOA Average input offset voltage drift
IEBOA[16] Input leakage current (Port 0 Analog Pins)
Input capacitance (Port 0 Analog Pins)
CINOA
VCMOA
ISOA
Common mode voltage range
Amplifier supply current
Notes
For 0.2 V < VIN < VDD – 1.2 V.
For VIN = 0 to 0.2 V and VIN > VDD
– 1.2 V.
Table 29. 3.3 V DC Type-E Operational Amplifier Specifications
Symbol
Description
Input offset voltage (absolute value)
VOSOA
Common mode voltage range
Amplifier supply current
Units
Notes
mV For 0.2 V < VIN < VDD – 1.2 V.
mV For VIN = 0 to 0.2 V and VIN > VDD –
1.2 V.
V/°C
nA
Gross tested to 1 A.
pF
Package and pin dependent. Temp =
25 °C.
V
A
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical
parameters apply to 5 V at 25 °C and are for design guidance only.
Table 30. DC Low Power Comparator Specifications
Symbol
VREFLPC
VOSLPC
ISLPC
Description
Low power comparator (LPC) reference
voltage range
LPC voltage offset
LPC supply current
Min
0.2
Typ
–
Max
VDD – 1
Units
V
–
–
2.5
10
30
40
mV
A
Notes
Note
16. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25 °C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.
Document Number: 001-48111 Rev. *K
Page 38 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 31. 5 V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
–
–
200
pF
This specification applies
to the external circuit that is
being driven by the analog
output buffer.
3
+6
–
12
20
VDD – 1.0
mV
V/°C
V
1
1
–
–


–
–
–
–
V
V
–
–
0.5 × VDD – 1.3
0.5 × VDD – 1.3
V
V
1.1
2.6
64
5.1
8.8
–
mA
mA
dB
CL
Load capacitance
VOSOB
TCVOSOB
VCMOB
ROUTOB
Input offset voltage (Absolute Value)
–
Average input offset voltage drift
–
Common-mode input voltage range
0.5
Output resistance
–
Power = Low
–
Power = High
High output voltage swing (Load = 32
 to VDD/2)
Power = Low
0.5 × VDD + 1.3
Power = High
0.5 × VDD + 1.3
Low output voltage swing (Load = 32
 to VDD/2)
Power = Low
–
Power = High
–
Supply current including bias cell
(No Load)
Power = Low
–
Power = High
–
Supply voltage rejection ratio
53
VOHIGHOB
VOLOWOB
ISOB
PSRROB
Document Number: 001-48111 Rev. *K
(0.5 × VDD – 1.0)  VOUT
 (0.5 × VDD + 0.9).
Page 39 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 32. 3.3 V DC Analog Output Buffer Specifications
Symbol
CL
Description
Load Capacitance
VOSOB
TCVOSOB
VCMOB
ROUTOB
Min
Typ
Max
Units
Notes
–
–
200
pF
This specification applies to
the external circuit that is
being driven by the analog
output buffer.
3
+6
–
12
20
VDD – 1.0
mV
V/°C
V
1
1
–
–


–
–
–
–
V
V
–
–
0.5 × VDD – 1.0
0.5 × VDD – 1.0
V
V
0.8
2.0
2.0
4.3
mA
mA
64
–
dB
Input Offset Voltage (Absolute Value)
–
Average Input Offset Voltage Drift
–
Common-Mode Input Voltage Range
0.5
Output Resistance
Power = Low
–
Power = High
–
VOHIGHOB High Output Voltage Swing (Load = 1
k to VDD/2)
Power = Low
0.5 × VDD + 1.0
Power = High
0.5 × VDD + 1.0
VOLOWOB Low Output Voltage Swing (Load = 1
k to VDD/2)
–
Power = Low
–
Power = High
ISOB
Supply current including bias cell (No
–
Load)
–
Power = Low
Power = High
PSRROB Supply voltage rejection ratio
47
Document Number: 001-48111 Rev. *K
(0.5 × VDD – 1.0)  VOUT 
(0.5 × VDD + 0.9).
Page 40 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
DC Switch Mode Pump Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 33. DC Switch Mode Pump (SMP) Specifications
Symbol
VPUMP 5 V
Description
5 V output voltage
Min
4.75
Typ
5.0
Max
5.25
Units
Notes
V
Configuration of footnote.[17] Average,
neglecting ripple. SMP trip voltage is set
to 5.0 V.
V
Configuration of footnote.[17] Average,
neglecting ripple. SMP trip voltage is set
to 3.25 V.
Configuration of footnote.[17]
SMP trip voltage is set to 3.25 V.
mA
SMP trip voltage is set to 5.0 V.
mA
V
Configuration of footnote.[17] SMP trip
voltage is set to 5.0 V.
V
Configuration of footnote.[17] SMP trip
voltage is set to 3.25 V.
V
Configuration of footnote.[17]
VPUMP 3 V
3 V output voltage
3.00
3.25
3.60
IPUMP
VBAT5 V
Available output current
VBAT = 1.5 V, VPUMP = 3.25 V
VBAT = 1.8 V, VPUMP = 5.0 V
Input voltage range from battery
8
5
1.8
–
–
–
–
–
5.0
VBAT3 V
Input voltage range from battery
1.5
–
3.3
VBATSTART
2.6
–
–
VPUMP_Line
Minimum input voltage from battery to
start pump
Line regulation (over VBAT range)
–
5
–
VPUMP_Load
Load regulation
–
5
–
VPUMP_Ripple
–
100
–
E3
Output voltage ripple (depends on
capacitor/load)
Efficiency
35
50
–
%
FPUMP
DCPUMP
Switching frequency
Switching duty cycle
–
–
1.3
50
–
–
MHz
%
%VO Configuration of footnote.[17] VO is the
“VDD Value for PUMP Trip” specified by
the VM[2:0] setting in the DC POR and
LVD Specification, Table 40 on page 50.
%VO Configuration of footnote.[17] VO is the
“VDD Value for PUMP Trip” specified by
the VM[2:0] setting in the DC POR and
LVD Specification, Table 40 on page 50.
mVpp Configuration of footnote.[17] Load is 5mA.
Configuration of footnote.[17] Load is
5 mA. SMP trip voltage is set to 3.25 V.
Figure 8. Basic Switch Mode Pump Circuit
D1
Vdd
L1
V BAT
+
V PUMP
C1
SMP
Battery
PSoC TM
Vss
Note
17. L1 = 2 uH inductor, C1 = 10 uF capacitor, D1 = Schottky diode. See Figure 8.
Document Number: 001-48111 Rev. *K
Page 41 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
The guaranteed specifications for RefHI and RefLo are measured through the Analog Continuous Time PSoC blocks. The power
levels for RefHi and RefLo refer to the Analog Reference Control register. AGND is measured at P2[4] in AGND bypass mode. Each
Analog Continuous Time PSoC block adds a maximum of 10mV additional offset error to guaranteed AGND specifications from the
local AGND buffer. Reference control power can be set to medium or high unless otherwise noted.
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling
of the digital signal may appear on the AGND.
Table 34. 5-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
0b000
Reference Power
Settings
Symbol
RefPower = High
VREFHI
Opamp bias = High
Reference
Description
Min
Typ
Max
Units
Ref high
VDD/2 + Bandgap
VDD/2 +
1.214
VDD/2 +
1.279
VDD/2 +
1.341
V
VAGND
AGND
VDD/2
VDD/2 –
0.018
VDD/2 –
0.004
VDD/2 + 0.01
V
VREFLO
Ref low
VDD/2 – Bandgap
VDD/2 –
1.328
VDD/2 –
1.301
VDD/2 –
1.273
V
Ref high
VDD/2 + Bandgap
VDD/2 +
0.228
VDD/2 +
1.284
VDD/2 +
1.344
V
VAGND
AGND
VDD/2
VDD/2 –
0.015
VDD/2 –
0.002
VDD/2 +
0.011
V
VREFLO
Ref low
VDD/2 – Bandgap
VDD/2 –
1.329
VDD/2 –
1.303
VDD/2 –
1.275
V
Ref high
VDD/2 + Bandgap
VDD/2 +
1.224
VDD/2 +
1.287
VDD/2 +
1.345
V
AGND
VDD/2
VDD/2 –
0.014
VDD/2 –
0.001
VDD/2 +
0.012
V
Ref low
VDD/2 – Bandgap
VDD/2 –
1.328
VDD/2 –
1.304
VDD/2 –
1.275
V
Ref high
VDD/2 + Bandgap
VDD/2 +
1.226
VDD/2 +
1.288
VDD/2 +
1.346
V
AGND
VDD/2
VDD/2 –
0.014
VDD/2 –
0.001
VDD/2 +
0.012
V
Ref low
VDD/2 – Bandgap
VDD/2 –
1.328
VDD/2 –
1.304
VDD/2 –
1.276
V
RefPower = High VREFHI
Opamp bias = Low
RefPower =
VREFHI
Medium
Opamp bias = High V
AGND
VREFLO
RefPower =
VREFHI
Medium
Opamp bias = Low V
AGND
VREFLO
Note
18. AGND tolerance includes the offsets of the local buffer in the PSoC block.
Document Number: 001-48111 Rev. *K
Page 42 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 34. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b001
Reference Power
Settings
Symbol
Description
Min
Typ
Max
Units
Ref high
P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] P2[4] + P2[6]
VDD/2, P2[6] = 1.3 V) – 0.055
– 0.019
+ 0.019
V
VAGND
AGND
P2[4]
–
VREFLO
Ref low
P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] P2[4] – P2[6]
+ 0.005
+ 0.035
VDD/2, P2[6] = 1.3 V) – 0.030
V
Ref high
P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] P2[4] + P2[6]
– 0.015
+ 0.021
VDD/2, P2[6] = 1.3 V) – 0.05
V
RefPower = High
VREFHI
Opamp bias = High
RefPower = High VREFHI
Opamp bias = Low
P2[4]
AGND
P2[4]
Ref low
P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] P2[4] – P2[6]
VDD/2, P2[6] = 1.3 V) – 0.033
+ 0.001
+ 0.031
V
Ref high
P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] P2[4] + P2[6]
VDD/2, P2[6] = 1.3 V) – 0.048
– 0.013
+ 0.022
V
AGND
P2[4]
–
Ref low
P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] P2[4] – P2[6]
VDD/2, P2[6] = 1.3 V) – 0.034
– 0.001
+ 0.031
V
Ref high
P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] P2[4] + P2[6]
VDD/2, P2[6] = 1.3 V) – 0.047
– 0.012
+ 0.023
V
VREFHI
RefPower =
Medium
Opamp bias = Low V
AGND
VREFLO
RefPower = High
VREFHI
Opamp bias = High V
AGND
VREFLO
RefPower = High VREFHI
Opamp bias = Low V
AGND
VREFLO
RefPower =
VREFHI
Medium
V
Opamp bias = High AGND
VREFLO
RefPower =
VREFHI
Medium
V
Opamp bias = Low AGND
VREFLO
Document Number: 001-48111 Rev. *K
P2[4]
P2[4]
P2[4]
P2[4]
VAGND
VREFLO
P2[4]
P2[4]
VREFLO
RefPower =
VREFHI
Medium
Opamp bias = High V
AGND
0b010
Reference
P2[4]
P2[4]
P2[4]
–
P2[4]
AGND
P2[4]
Ref low
P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] P2[4] – P2[6]
– 0.002
+ 0.030
VDD/2, P2[6] = 1.3 V) – 0.036
V
Ref high
VDD
VDD
V
AGND
VDD/2
VDD – 0.028 VDD – 0.010
VDD/2 –
VDD/2 –
0.014
0.002
VDD/2 +
0.012
V
Ref low
VSS
VSS
Ref high
VDD
AGND
VDD/2
VDD – 0.021 VDD – 0.007
VDD/2 –
VDD/2 –
0.014
0.001
Ref low
VSS
VSS
Ref high
VDD
AGND
VDD/2
VDD – 0.019 VDD – 0.006
VDD/2 –
VDD/2 –
0.014
0.001
Ref low
VSS
VSS
VSS + 0.004
V
Ref high
VDD
VDD
V
AGND
VDD/2
VDD – 0.017 VDD – 0.005
VDD/2 –
VDD/2 –
0.014
0.001
VDD/2 +
0.013
V
Ref low
VSS
VSS
VSS + 0.003
V
VSS + 0.004
VSS + 0.002
VSS + 0.002
VSS + 0.001
P2[4]
–
VSS + 0.008
V
VDD
V
VDD/2 +
0.012
V
VSS + 0.005
V
VDD
V
VDD/2 +
0.012
V
Page 43 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 34. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b011
Reference Power
Settings
Symbol
RefPower = High VREFHI
Opamp bias = High V
AGND
VREFLO
RefPower = High VREFHI
Opamp bias = Low V
AGND
VREFLO
0b100
Reference
Description
Min
Typ
Max
Units
Ref high
3 × Bandgap
3.736
3.887
4.030
V
AGND
2 × Bandgap
2.525
2.598
2.667
V
Ref low
Bandgap
1.265
1.302
1.335
V
Ref high
3 × Bandgap
3.747
3.894
4.034
V
AGND
2 × Bandgap
2.528
2.601
2.668
V
Ref low
Bandgap
1.264
1.302
1.335
V
VREFHI
RefPower =
Medium
V
Opamp bias = High AGND
VREFLO
Ref high
3 × Bandgap
3.749
3.897
4.035
V
AGND
2 × Bandgap
2.529
2.602
2.668
V
Ref low
Bandgap
1.264
1.302
1.335
V
VREFHI
RefPower =
Medium
V
Opamp bias = Low AGND
VREFLO
Ref high
3 × Bandgap
3.751
3.899
4.037
V
AGND
2 × Bandgap
2.530
2.603
2.669
V
Ref low
Bandgap
1.264
1.302
1.335
RefPower = High
VREFHI
Opamp bias = High
Ref high
2 × Bandgap + P2[6] 2.483 – P2[6] 2.578 – P2[6] 2.669 – P2[6]
(P2[6] = 1.3 V)
V
VAGND
AGND
2 × Bandgap
V
VREFLO
Ref low
2 × Bandgap – P2[6] 2.512 – P2[6] 2.602 – P2[6] 2.684 – P2[6]
(P2[6] = 1.3 V)
V
Ref high
2 × Bandgap + P2[6] 2.495 – P2[6] 2.586 – P2[6] 2.673 – P2[6]
(P2[6] = 1.3 V)
V
VAGND
AGND
2 × Bandgap
VREFLO
Ref low
2 × Bandgap – P2[6] 2.510 – P2[6] 2.602 – P2[6] 2.685 – P2[6]
(P2[6] = 1.3 V)
V
Ref high
2 × Bandgap + P2[6] 2.498 – P2[6] 2.589 – P2[6] 2.674 – P2[6]
(P2[6] = 1.3 V)
V
AGND
2 × Bandgap
V
Ref low
2 × Bandgap – P2[6] 2.509 – P2[6] 2.601 – P2[6] 2.685 – P2[6]
(P2[6] = 1.3 V)
V
Ref high
2 × Bandgap + P2[6] 2.500 – P2[6] 2.591 – P2[6] 2.675 – P2[6]
(P2[6] = 1.3 V)
V
AGND
2 × Bandgap
Ref low
2 × Bandgap – P2[6] 2.508 – P2[6] 2.601 – P2[6] 2.686 – P2[6]
(P2[6] = 1.3 V)
RefPower = High VREFHI
Opamp bias = Low
RefPower =
VREFHI
Medium
Opamp bias = High V
AGND
VREFLO
VREFHI
RefPower =
Medium
Opamp bias = Low V
AGND
VREFLO
Document Number: 001-48111 Rev. *K
2.525
2.528
2.529
2.530
2.598
2.601
2.601
2.603
V
2.666
2.668
V
2.668
2.669
V
V
Page 44 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 34. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b101
Reference Power
Settings
Symbol
Description
Min
Typ
Max
Units
Ref high
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.218 P2[4] + 1.283 P2[4] + 1.344
V
VAGND
AGND
P2[4]
P2[4]
–
VREFLO
Ref low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.329 P2[4] – 1.297 P2[4] – 1.265
V
Ref high
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.225 P2[4] + 1.287 P2[4] + 1.346
V
RefPower = High
VREFHI
Opamp bias = High
RefPower = High VREFHI
Opamp bias = Low
P2[4]
AGND
P2[4]
P2[4]
VREFLO
Ref low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.330 P2[4] – 1.301 P2[4] – 1.271
V
Ref high
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.226 P2[4] + 1.288 P2[4] + 1.346
V
AGND
P2[4]
P2[4]
–
Ref low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.330 P2[4] – 1.302 P2[4] – 1.272
V
Ref high
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.227 P2[4] + 1.289 P2[4] + 1.347
V
VREFLO
VREFHI
RefPower =
Medium
Opamp bias = Low V
AGND
VREFLO
RefPower = High VREFHI
Opamp bias = High V
AGND
VREFLO
RefPower = High VREFHI
Opamp bias = Low V
AGND
VREFLO
P2[4]
P2[4]
VAGND
RefPower =
VREFHI
Medium
Opamp bias = High V
AGND
0b110
Reference
P2[4]
P2[4]
P2[4]
–
P2[4]
AGND
P2[4]
P2[4]
Ref low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.331 P2[4] – 1.303 P2[4] – 1.273
P2[4]
V
–
Ref high
2 × Bandgap
2.506
2.597
2.674
V
AGND
Bandgap
1.263
1.302
1.336
V
Ref low
VSS
VSS
VSS + 0.006
VSS + 0.014
V
Ref high
2 × Bandgap
2.508
2.595
2.675
V
AGND
Bandgap
1.263
1.302
1.336
V
Ref low
VSS
VSS
VSS + 0.003
VSS + 0.008
V
RefPower =
VREFHI
Medium
V
Opamp bias = High AGND
VREFLO
Ref high
2 × Bandgap
2.508
2.595
2.676
V
AGND
Bandgap
1.263
1.302
1.336
V
Ref low
VSS
VSS
VSS + 0.002
VSS + 0.005
V
RefPower =
VREFHI
Medium
V
Opamp bias = Low AGND
VREFLO
Ref high
2 × Bandgap
2.508
2.596
2.677
V
AGND
Bandgap
1.263
1.302
1.336
V
Ref low
VSS
VSS
VSS + 0.001
VSS + 0.003
V
Document Number: 001-48111 Rev. *K
Page 45 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 34. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b111
Reference Power
Settings
Symbol
RefPower = High
VREFHI
Opamp bias = High V
AGND
VREFLO
RefPower = High VREFHI
Opamp bias = Low V
AGND
VREFLO
Reference
Description
Min
Typ
Max
Units
Ref high
3.2 × Bandgap
4.056
4.155
4.222
V
AGND
1.6 × Bandgap
2.012
2.083
2.168
V
Ref low
VSS
VSS
VSS + 0.01
VSS + 0.035
V
Ref high
3.2 × Bandgap
4.061
4.153
4.223
V
AGND
1.6 × Bandgap
2.023
2.082
2.145
V
Ref low
VSS
VSS
VSS + 0.006
VSS + 0.022
V
VREFHI
RefPower =
Medium
V
Opamp bias = High AGND
VREFLO
Ref high
3.2 × Bandgap
4.063
4.154
4.224
V
AGND
1.6 × Bandgap
2.020
2.083
2.152
V
Ref low
VSS
VSS
VSS + 0.006
VSS + 0.024
V
VREFHI
RefPower =
Medium
V
Opamp bias = Low AGND
VREFLO
Ref high
3.2 × Bandgap
4.061
4.154
4.225
V
AGND
1.6 × Bandgap
2.026
2.081
2.140
V
Ref low
VSS
VSS
VSS + 0.004
VSS + 0.017
V
Table 35. 3.3-V DC Analog Reference Specifications
Reference
Reference Power
ARF_CR
Settings
[5:3]
0b000
Symbol
RefPower = High
VREFHI
Opamp bias = High
VAGND
Reference
Description
Min
Typ
Max
Units
Ref high
VDD/2 + Bandgap
VDD/2 + 1.223
VDD/2 + 1.283
VDD/2 + 1.343 V
AGND
VDD/2
VDD/2 – 0.013
VDD/2 – 0.003
VDD/2 + 0.005 V
Ref low
VDD/2 – Bandgap
VDD/2 – 1.322
VDD/2 – 1.297
VDD/2 – 1.270 V
Ref high
VDD/2 + Bandgap
VDD/2 + 1.228
VDD/2 + 1.288
VDD/2 + 1.345 V
AGND
VDD/2
VDD/2 – 0.008
VDD/2 – 0.002
VDD/2 + 0.005 V
Ref low
VDD/2 – Bandgap
VDD/2 – 1.322
VDD/2 – 1.298
VDD/2 – 1.271 V
RefPower =
VREFHI
Medium
V
Opamp bias = High AGND
VREFLO
Ref high
VDD/2 + Bandgap
VDD/2 + 1.232
VDD/2 + 1.290
VDD/2 + 1.346 V
AGND
VDD/2
VDD/2 – 0.008
VDD/2 – 0.001
VDD/2 + 0.006 V
Ref low
VDD/2 – Bandgap
VDD/2 – 1.322
VDD/2 – 1.299
VDD/2 – 1.272 V
RefPower =
VREFHI
Medium
V
AGND
Opamp bias = Low
VREFLO
Ref high
VDD/2 + Bandgap
VDD/2 + 1.233
VDD/2 + 1.291
VDD/2 + 1.347 V
AGND
VDD/2
VDD/2 – 0.006
VDD/2
VDD/2 + 0.006 V
Ref low
VDD/2 – Bandgap
VDD/2 – 1.322
VDD/2 – 1.299
VDD/2 – 1.272 V
VREFLO
RefPower = High
VREFHI
Opamp bias = Low
VAGND
VREFLO
Document Number: 001-48111 Rev. *K
Page 46 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 35. 3.3-V DC Analog Reference Specifications (continued)
Reference
Reference Power
ARF_CR
Settings
[5:3]
0b001
Symbol
RefPower = High
VREFHI
Opamp bias = High
Description
Ref high
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
VAGND
AGND
VREFLO
Ref low
Min
Typ
Max
Units
P2[4] + P2[6] – P2[4] + P2[6] –
0.045
0.017
P2[4] + P2[6] + V
0.016
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] –
0.019
P2[4] – P2[6] +
0.004
P2[4] – P2[6] + V
0.023
Ref high
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] – P2[4] + P2[6] –
0.036
0.012
P2[4] + P2[6] + V
0.013
VAGND
AGND
P2[4]
P2[4]
P2[4]
P2[4]
VREFLO
Ref low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] –
0.021
P2[4] – P2[6] –
0.001
P2[4] – P2[6] + V
0.021
Ref high
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] – P2[4] + P2[6] –
0.034
0.011
P2[4] + P2[6] + V
0.013
AGND
P2[4]
P2[4]
P2[4]
P2[4]
Ref low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] –
0.023
P2[4] – P2[6] –
0.002
P2[4] – P2[6] + V
0.016
Ref high
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] – P2[4] + P2[6] –
0.033
0.009
P2[4] + P2[6] + V
0.014
AGND
P2[4]
P2[4]
P2[4]
P2[4]
Ref low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] –
0.024
P2[4] – P2[6] –
0.003
P2[4] – P2[6] + V
0.020
Ref high
VDD
VDD – 0.042
VDD – 0.008
VDD
AGND
VDD/2
VDD/2 – 0.035
VDD/2 – 0.001
VDD/2 + 0.031 V
Ref low
VSS
VSS
VSS + 0.003
VSS + 0.0165 V
V
Ref high
VDD
VDD – 0.035
VDD – 0.005
VDD
AGND
VDD/2
VDD/2 – 0.031
VDD/2 – 0.001
VDD/2 + 0.028 V
RefPower = High
VREFHI
Opamp bias = Low
RefPower =
VREFHI
Medium
Opamp bias = High
VAGND
VREFLO
RefPower =
VREFHI
Medium
Opamp bias = Low
VAGND
VREFLO
0b010
Reference
RefPower = High
VREFHI
Opamp bias = High
VAGND
VREFLO
RefPower = High
VREFHI
Opamp bias = Low
VAGND
VREFLO
–
–
–
–
V
V
Ref low
VSS
VSS
VSS + 0.002
VSS + 0.012
V
RefPower =
VREFHI
Medium
V
Opamp bias = High AGND
VREFLO
Ref high
VDD
VDD – 0.044
VDD – 0.005
VDD
V
AGND
VDD/2
VDD/2 – 0.052
VDD/2
VDD/2 + 0.046 V
Ref low
VSS
VSS
VSS + 0.002
VSS + 0.014
V
RefPower =
VREFHI
Medium
Opamp bias = Low VAGND
VREFLO
Ref high
VDD
VDD – 0.036
VDD – 0.004
VDD
V
VDD/2 + 0.029 V
0b011
All power settings.
Not allowed for
3.3 V.
0b100
All power settings.
Not allowed for
3.3 V.
AGND
VDD/2
VDD/2 – 0.032
VDD/2
Ref low
VSS
VSS
VSS + 0.001
VSS + 0.012
V
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Document Number: 001-48111 Rev. *K
Page 47 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 35. 3.3-V DC Analog Reference Specifications (continued)
Reference
Reference Power
ARF_CR
Settings
[5:3]
0b101
Symbol
RefPower = High
VREFHI
Opamp bias = High
Min
Units
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.323
P2[4] – 1.293
P2[4] –1.262
V
Ref high
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.232
P2[4] + 1.29
P2[4] + 1.344 V
VAGND
AGND
P2[4]
P2[4]
P2[4]
P2[4]
VREFLO
Ref low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.324
P2[4] – 1.296
P2[4] – 1.267 V
Ref high
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.233
P2[4] + 1.291
P2[4] + 1.345 V
AGND
P2[4]
P2[4]
P2[4]
P2[4]
Ref low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.324
P2[4] – 1.298
P2[4] – 1.269 V
Ref high
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.234
P2[4] + 1.292
P2[4] +1.345
V
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
Ref low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.324
P2[4] – 1.299
P2[4] – 1.270 V
Ref high
2 × Bandgap
2.504
2.595
2.672
AGND
Bandgap
1.262
1.301
1.336
V
Ref low
VSS
VSS
VSS + 0.006
VSS + 0.013
V
Ref high
2 × Bandgap
2.506
2.593
2.674
V
AGND
Bandgap
1.262
1.301
1.336
V
RefPower =
VREFHI
Medium
Opamp bias = Low
VAGND
VREFLO
RefPower = High
VREFHI
Opamp bias = High
VAGND
VREFLO
RefPower = High
VREFHI
Opamp bias = Low
VAGND
VREFLO
P2[4] + 1.286
Max
VAGND
VREFLO
P2[4] + 1.226
Typ
P2[4] + Bandgap
(P2[4] = VDD/2)
RefPower =
VREFHI
Medium
Opamp bias = High
VAGND
0b111
Description
Ref high
RefPower = High
VREFHI
Opamp bias = Low
0b110
Reference
P2[4] + 1.343 V
–
–
V
Ref low
VSS
VSS
VSS + 0.003
VSS + 0.008
V
RefPower =
VREFHI
Medium
Opamp bias = High VAGND
VREFLO
Ref high
2 × Bandgap
2.506
2.594
2.675
V
AGND
Bandgap
1.262
1.301
1.335
V
Ref low
VSS
VSS
VSS + 0.002
VSS + 0.007
V
RefPower =
VREFHI
Medium
Opamp bias = Low VAGND
VREFLO
Ref high
2 × Bandgap
2.507
2.595
2.675
V
AGND
Bandgap
1.262
1.301
1.335
V
Ref low
VSS
VSS
VSS + 0.001
VSS + 0.005
V
All power settings.
Not allowed for
3.3 V.
–
–
–
–
–
–
–
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 36. DC Analog PSoC Block Specifications
Symbol
RCT
CSC
Description
Resistor Unit Value (Continuous Time)
Capacitor Unit Value (Switch Cap)
Document Number: 001-48111 Rev. *K
Min
–
–
Typ
12.24
80
Max
–
–
Units
k
fF
Notes
Page 48 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
DC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 37. DC Analog Mux Bus Specifications
Symbol
RSW
RVSS
Description
Switch Resistance to Common Analog Bus
Resistance of Initialization Switch to VSS
Min
–
–
Typ
–
–
Max
400
800
Units


Notes
VDD  3.0 V
DC SAR10 ADC Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 38. DC SAR10 ADC Specifications
Symbol
INLSAR10
DNLSAR10
ISAR10
IVREFSAR10
VVREFSAR10
VOSSAR10
SARIMP
Description
Integral nonlinearity for VREF 3 V
Integral nonlinearity for VREF < 3 V
Differential nonlinearity for VREF 3 V
Differential nonlinearity for VREF > 3 V
Active current consumption
Input current into P2[5] when configured as
the SAR10 ADC's VREF input.
Input reference voltage at P2[5] when
configured as the SAR10 ADC's external
voltage reference.
Offset voltage
SAR input impedence
Min
–2.5
–5
–1.5
–4
0.08
–
Typ
–
–
–
–
0.5
–
Max
2.5
5
1.5
4
0.497
0.5
Units
LSB
LSB
LSB
LSB
mA
mA
2.7
–
VDD –
0.3 V
V
5
–
7.7
1.64
10
–
mV
M
Notes
10-bit resolution
10-bit resolution
10-bit resolution
10-bit resolution
The internal voltage reference buffer is
disabled in this configuration.
When VREF is buffered inside the
SAR10 ADC, the voltage level at P2[5]
(when configured as the external
reference voltage) must always be at
least 300 mV less than the chip supply
voltage level on the VDD pin.
(VVREFSAR10 < (VDD – 300 mV)).
Frequency dependant = 1/ Fs °C.
142.9 kHz (maximum) and Cin = 4.28 pF
(typical)
Table 39. DC IDAC Specifications
Min
Typ
Max
Units
IDAC_DNL
Symbol
Differential nonlinearity
–5.0
2.0
5.0
LSB
IDAC_INL
Integral nonlinearity
–5.0
2.0
5.0
LSB
IDAC_Gain
Gain per bit – Range 1 (91 µA)
283
357
447
nA
Gain per bit – Range 2 (318 µA)
985
1250
1532
nA
Gain per bit – Range 3 (637 µA)
1959
2500
3056
nA
Offset at Code 0 vs LSB Ideal – Range 1
(91 µA)
2.0%
20%
%
Offset at Code 0 vs LSB Ideal – Range 2
(318 µA)
1.0%
10%
%
Offset at Code 0 vs LSB Ideal – Range 3
(637 µA)
1.0%
10%
%
IDACOffset
Description
Document Number: 001-48111 Rev. *K
Notes
Valid for all 3 current ranges
Valid for all 3 current ranges
Measured at full scale
Measured as a % of LSB (Current @
Code 0)/(LSB Ideal Current)
Page 49 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Technical Reference Manual
for CY8C28xxx PSoC devices, for more information on the VLT_CR register.
Table 40. DC POR and LVD Specifications
Symbol
VPPOR0R
VPPOR1R
VPPOR2R
VPPOR0
VPPOR1
VPPOR2
VPH0
VPH1
VPH2
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
Description
VDD Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VDD Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
PPOR Hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VDD Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
VDD Value for PUMP Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
–
–
–
2.91
4.39
4.55
2.985
4.49
4.65
V
V
V
–
–
–
2.82
4.39
4.55
2.90
4.49
4.64
V
V
V
–
–
–
92
0
0
–
–
–
mV
mV
mV
2.83
2.93
3.04
3.90
4.38
4.54
4.62
4.71
2.91
3.01
3.12
3.99
4.47
4.63
4.71
4.80
3.00[19]
3.10
3.21
4.09
4.58
4.74[20]
4.83
4.92
V
V
V
V
V
V
V
V
2.93
3.00
3.16
4.09
4.53
4.61
4.70
4.88
3.01
3.08
3.24
4.17
4.62
4.71
4.80
4.98
3.10
3.17
3.33
4.28
4.74
4.82
4.91
5.10
V
V
V
V
V
V
V
V
Notes
VDD must be greater than or equal
to 2.5 V during startup, reset from
the XRES pin, or reset from
Watchdog.
VDD must be greater than or equal
to 2.5 V during startup, reset from
the XRES pin, or reset from
Watchdog.
Notes
19. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
20. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
Document Number: 001-48111 Rev. *K
Page 50 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 41. DC Programming Specifications
Symbol
VDDP
Description
VDD for programming and erase
Min
4.5
Typ
5
Max
5.5
VDDLV
VDDHV
Low VDD for verify
3
3.1
3.2
High VDD for verify
5.1
5.2
5.3
VDDIWRITE Supply Voltage for Flash write operation
3
–
5.25
IDDP
VILP
–
–
5
–
25
0.8
2.2
–
–
V
–
–
0.21
mA
–
–
1.5
mA
–
–
0.75
V
VDD – 1.0
–
VDD
V
50,000[21]
1,800,000
–
–
–
–
–
–
10
–
–
Years
Supply Current During Programming or Verify
Input Low Voltage During Programming or
Verify
VIHP
Input High Voltage During Programming or
Verify
IILP
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
IIHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
VOLV
Output Low Voltage During Programming or
Verify
VOHV
Output High Voltage During Programming or
Verify
FlashENPB Flash Endurance (per block)
FlashENT Flash Endurance (total)[22]
FlashDR
Flash Data Retention
Units
Notes
V
This specification applies
to the functional
requirements of external
programmer tools.
V
This specification applies
to the functional
requirements of external
programmer tools.
V
This specification applies
to the functional
requirements of external
programmer tools.
V
This specification applies
to this device when it is
executing internal flash
writes.
mA
V
Driving internal pull-down
resistor.
Driving internal pull-down
resistor.
Erase/write cycles per block.
Erase/write cycles. Must be
programmed and read at the
same voltage to meet this.
Notes
21. The 50,000 cycle Flash endurance per block will only be guaranteed if the Flash is operating within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V
to 5.25 V.
22. A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever
sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 001-48111 Rev. *K
Page 51 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
DC I2C Specifications
Table 42 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 42. DC I2C Specifications[23]
Symbol
VILI2C
Input low level
Description
VIHI2C
Input high level
Min
–
–
0.7 × VDD
Typ
Max
–
0.3 × VDD
–
0.25 × VDD
–
–
Units
V
V
V
Notes
3.0 V VDD 3.6 V
4.75 V VDD 5.25 V
3.0 V VDD 5.25 V
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 43. AC Chip-Level Specifications
Symbol
FIMO
Description
Internal Main Oscillator Frequency
Min
23.4
Typ
24
Max
24.6[24]
Units
MHz
FIMO6
Internal Main Oscillator Frequency for
6 MHz
5.5
6
6.5[24]
MHz
FCPU1
CPU Frequency (5 V Nominal)
0.091
24
24.6[24]
MHz
FCPU2
CPU Frequency (3.3 V Nominal)
0.091
12
12.3[25]
MHz
FBLK5
FBLK33
F32K1
Digital PSoC Block Frequency
Digital PSoC Block Frequency
Internal Low Speed Oscillator
Frequency
External Crystal Oscillator
0
0
15
–
24
32
49.2[24, 26]
24.6[26]
64
MHz
MHz
kHz
–
32.768
–
kHz
Internal Low Speed Oscillator
Untrimmed Frequency
5
–
100
kHz
–
0.5
0.5
23.986
–
–
–
10
50
MHz
ms
ms
External Crystal Oscillator Startup to
1%
External Crystal Oscillator Startup to
100 ppm
–
1700
2620
ms
–
2800
3800
ms
External Reset Pulse Width
24 MHz Duty Cycle
10
40
–
50
–
60
s
%
F32K2
F32K_U
FPLL
PLL Frequency
tPLLSLEW
PLL Lock Time
tPLLSLEWSLO PLL Lock Time for Low Gain Setting
Notes
Trimmed. Utilizing factory trim
values. SLIMO Mode = 0.
Trimmed for 5 V or 3.3 V operation
using factory trim values. SLIMO
Mode = 1.
Trimmed. Utilizing factory trim
values. SLIMO mode = 0.
Trimmed. Utilizing factory trim
values. SLIMO mode = 0.
4.75 V< VDD <5.25 V
3.0 V<VDD<3.6 V
Trimmed. Utilizing factory trim
values.
Accuracy is capacitor and crystal
dependent. 50% duty cycle.
After a reset and before the m8c
starts to run, the ILO is not trimmed.
See the System Resets section of the
PSoC Technical Reference manual
for details on timing this.
Multiple (x732) of crystal frequency.
W
TOS
TOSACC
tXRST
DC24M
The crystal oscillator frequency is
within 100 ppm of its final value by the
end of the Tosacc period. Correct
operation assumes a properly loaded
1 µW maximum drive level 32.768
kHz crystal. 3.0 V  VDD  5.5 V, –40
°C  TA  85 °C.
Note
23. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs.
Document Number: 001-48111 Rev. *K
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Table 43. AC Chip-Level Specifications (continued)
Symbol
DCILO
Fout48M
Description
Internal Low Speed Oscillator Duty
Cycle
48 MHz Output Frequency
FMAX
Maximum Frequency of Signal on Row
Input or Row Output.
SRPOWERUP Supply Ramp Time
tPOWERUP
Time for POR Release to Code
Execution
tjit_IMO [27]
24 MHz IMO cycle-to-cycle jitter (RMS)
24 MHz IMO long term N cycle-to-cycle
jitter (RMS)
24 MHz IMO period jitter (RMS)
tjit_PLL [27]
24 MHz IMO cycle-to-cycle jitter (RMS)
24 MHz IMO long term N cycle-to-cycle
jitter (RMS)
24 MHz IMO period jitter (RMS)
Min
20
Typ
50
Max
80
Units
%
Notes
46.8
48.0
49.2[24,25]
MHz
–
–
12.3
MHz
0
–
–
16
–
100
s
ms
–
–
200
300
1300
1300
ps
ps
N = 32
–
–
–
200
200
400
800
1100
2800
ps
ps
ps
N = 32
–
200
1400
ps
Trimmed. Utilizing factory trim
values.
Figure 9. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 10. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Notes
24. 4.75 V < VDD < 5.25 V.
25. 3.0 V < VDD < 3.6 V. See application note Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 for information on trimming for operation at 3.3 V.
26. See the individual user module datasheets for information on maximum frequencies for user modules.
27. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-48111 Rev. *K
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Figure 11. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
AC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 44. AC GPIO Specifications
Symbol
FGPIO
tRiseF
tFallF
tRiseS
tFallS
Description
GPIO Operating Frequency
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12.3
18
18
–
–
Units
MHz
ns
ns
ns
ns
Notes
Normal Strong Mode
VDD = 4.5 to 5.25 V, 10% – 90%
VDD = 4.5 to 5.25 V, 10% – 90%
VDD = 3 to 5.25 V, 10% – 90%
VDD = 3 to 5.25 V, 10% – 90%
Figure 12. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only. The Operational Amplifiers covered by these specifications are components of both the Analog
Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. Settling times, slew rates, and gain bandwidth are based
on the Analog Continuous Time PSoC block.
Power = High and Opamp bias = High is not supported at 3.3 V.
Table 45. 5 V AC Operational Amplifier Specifications
Symbol
tROA
tSOA
Description
Rising Settling Time from 80% of V to 0.1% of
V (Active Probe Loading, Unity Gain)
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = High
Falling Settling Time from 20% of V to 0.1%
of V (Active Probe Loading, Unity Gain)
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = High
Document Number: 001-48111 Rev. *K
Min
Typ
Max
Units
–
–
–
–
–
–
3.9
0.72
0.62
s
s
s
–
–
–
–
–
–
5.9
0.92
0.72
s
s
s
Notes
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Table 45. 5 V AC Operational Amplifier Specifications (continued)
Symbol
SRROA
SRFOA
BWOA
ENOA
Description
Rising Slew Rate (20% to 80%)(Active Probe
Loading, Unity Gain)
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = High
Falling Slew Rate (80% to 20%)(Active Probe
Loading, Unity Gain)
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = High
Gain Bandwidth Product
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = High
Noise at 1 kHz
Power = Medium, Opamp bias = High
Min
Typ
Max
Units
0.15
1.7
6.5
–
–
–
–
–
–
V/s
V/s
V/s
0.01
0.5
4.0
–
–
–
–
–
–
V/s
V/s
V/s
0.75
3.1
5.4
–
–
–
–
100
–
–
–
–
MHz
MHz
MHz
nV/rt-Hz
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
s
s
–
–
–
–
5.41
0.72
s
s
0.31
2.7
–
–
–
–
V/s
V/s
0.24
1.8
–
–
–
–
V/s
V/s
0.67
2.8
–
–
–
100
–
–
–
MHz
MHz
nV/rt-Hz
Notes
Table 46. 3.3 V AC Operational Amplifier Specifications
Symbol
tROA
tSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising Settling Time from 80% of V to 0.1% of
V (Active Probe Loading, Unity Gain)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Falling Settling Time from 20% of V to 0.1%
of V (Active Probe Loading, Unity Gain)
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Rising Slew Rate (20% to 80%)(Active Probe
Loading, Unity Gain)
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Falling Slew Rate (80% to 20%)(Active Probe
Loading, Unity Gain)
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Gain Bandwidth Product
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Noise at 1 kHz
Power = Medium, Opamp bias = High
Document Number: 001-48111 Rev. *K
Notes
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When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 13. Typical AGND Noise with P2[4] Bypass
VnAGND Emerald = 2*Vbg
-90
-100
-110
E0.0
E0.01
-120
E0.1
E1.0
E10.0
-130
-140
-150
0.001
0.01
0.1
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 14. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 001-48111 Rev. *K
0.01
0.1
Freq (kHz)
1
10
100
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AC Type-E Operational Amplifier Specifications
Table 47 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. The Operational Amplifiers covered by these specifications
are components of the Limited Type E Analog PSoC blocks.
Table 47. AC Type-E Operational Amplifier Specifications
Symbol
tCOMP
Description
Comparator Mode Response Time
Min
–
Typ
75
Max
100
Units
ns
Notes
50 mV overdrive.
AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical
parameters apply to 5 V at 25 °C and are for design guidance only.
Table 48. AC Low Power Comparator Specifications
Symbol
tRLPC
Description
LPC Response Time
Document Number: 001-48111 Rev. *K
Min
–
Typ
–
Max
50
Units
s
Notes
 50 mV overdrive.
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AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 49. AC Digital Block Specifications
Function
All
functions
Timer
Counter
Dead
Band
CRCPRS
(PRS
Mode)
CRCPRS
(CRC
Mode)
SPIM
SPIS
Tranmitter
Receiver
Description
Block Input Clock Frequency
VDD  4.75 V
VDD < 4.75 V
Input Clock Frequency
No Capture, VDD  4.75 V
No Capture, VDD < 4.75 V
With Capture
Capture Pulse Width
Input Clock Frequency
No Enable Input, VDD  4.75 V
No Enable Input, VDD < 4.75 V
With Enable Input
Enable Input Pulse Width
Kill Pulse Width
Asynchronous Restart Mode
Synchronous Restart Mode
Disable Mode
Input Clock Frequency
VDD  4.75 V
VDD < 4.75 V
Input Clock Frequency
VDD  4.75 V
VDD < 4.75 V
Input Clock Frequency
Input Clock Frequency
Input Clock (SCLK) Frequency
Width of SS_Negated Between Transmissions
Input Clock Frequency
VDD  4.75 V, 2 Stop Bits
VDD  4.75 V, 1 Stop Bit
VDD < 4.75 V
Input Clock Frequency
VDD  4.75 V, 2 Stop Bits
VDD  4.75 V, 1 Stop Bit
VDD < 4.75 V
Min
Typ
Max
Units
–
–
–
–
49
25
MHz
MHz
–
–
–
50[28]
–
–
–
–
49
25
25
–
MHz
MHz
MHz
ns
–
–
–
50[28]
–
–
–
–
49
25
25
–
MHz
MHz
MHz
ns
20
50[28]
50[28]
–
–
–
–
–
–
ns
ns
ns
–
–
–
–
49
25
MHz
MHz
–
–
–
–
–
–
49
25
25
MHz
MHz
MHz
–
–
8.2
MHz
–
50[13]
–
–
4.1
–
MHz
ns
–
–
–
–
–
–
49
25
25
MHz
MHz
MHz
–
–
–
–
–
–
49
25
25
MHz
MHz
MHz
Notes
The SPI serial clock (SCLK)
frequency is equal to the input clock
frequency divided by 2.
The input clock is the SPI SCLK in
SPIS mode.
The baud rate is equal to the input
clock frequency divided by 8.
The baud rate is equal to the input
clock frequency divided by 8.
Note
28. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-48111 Rev. *K
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AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 50. 5 V AC Analog Output Buffer Specifications
Symbol
tROB
tSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising Settling Time to 0.1%, 1 V Step, 100 pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1 V Step, 100 pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1 V Step, 100 pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1 V Step, 100 pF Load
Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load
Power = Low
Power = High
Large Signal Bandwidth, 1 Vpp, 3dB BW, 100 pF Load
Power = Low
Power = High
Min
Typ
Max
Units
–
–
–
–
2.5
2.9
s
s
–
–
–
–
2.3
2.3
s
s
0.65
0.65
–
–
–
–
V/s
V/s
0.65
0.65
–
–
–
–
V/s
V/s
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Min
Typ
Max
Units
–
–
–
–
3.8
3.8
s
s
–
–
–
–
3.2
2.9
s
s
0.5
0.5
–
–
–
–
V/s
V/s
0.5
0.5
–
–
–
–
V/s
V/s
0.64
0.64
–
–
–
–
MHz
MHz
200
200
–
–
–
–
kHz
kHz
Notes
Table 51. 3.3 V AC Analog Output Buffer Specifications
Symbol
tROB
tSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising Settling Time to 0.1%, 1 V Step, 100 pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1 V Step, 100 pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1 V Step, 100 pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1 V Step, 100 pF Load
Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load
Power = Low
Power = High
Large Signal Bandwidth, 1 Vpp, 3dB BW, 100 pF Load
Power = Low
Power = High
Document Number: 001-48111 Rev. *K
Notes
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AC SAR10 ADC Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 52. AC SAR10 ADC Specifications
Symbol
FINSAR10
FSSAR10
Description
Input clock frequency for SAR10 ADC
Sample rate for SAR10 ADC
SAR10 ADC Resolution = 10 bits
Min
–
–
Typ
–
–
Max
2.0
142.9
Units
MHz
ksps
Notes
For 10-bit resolution, the
sample rate is the ADC's input
clock divided by 14.
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 53. 5 V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
–
Power-up IMO to Switch
150
–
–
s
Notes
Table 54. 3.3 V AC External Clock Specifications
Min
Typ
Max
Units
FOSCEXT
Symbol
Frequency with CPU Clock divide by 1[29]
Description
0.093
–
12.3
MHz
FOSCEXT
Frequency with CPU Clock divide by 2 or greater[30]
0.186
–
24.6
MHz
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power-up IMO to Switch
150
–
–
s
Notes
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 55. AC Programming Specifications
Symbol
tRSCLK
tFSCLK
tSSCLK
tHSCLK
FSCLK
tERASEB
tWRITE
tDSCLK
Description
Rise Time of SCLK
Fall Time of SCLK
Data Setup Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Document Number: 001-48111 Rev. *K
Min
1
1
40
40
0
–
–
–
Typ
–
–
–
–
–
10
40
–
Max
20
20
–
–
8
–
–
55
Units
ns
ns
ns
ns
MHz
ms
ms
ns VDD  3.6
Notes
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Table 55. AC Programming Specifications
Symbol
tDSCLK3
tERASEALL
Description
Data Out Delay from Falling Edge of SCLK
Flash Erase Time (Bulk)
Min
–
–
Typ
–
40
tPROGRAM_HOT
tPROGRAM_COLD
Flash Block Erase + Flash Block Write Time
Flash Block Erase + Flash Block Write Time
–
–
–
–
Max
75
–
Units
Notes
ns 3.0  VDD  3.6
ms Erase all blocks and protection
fields at once.
100[31] ms 0 °C  Tj  100 °C
200[31] ms –40 °C  Tj  0 °C
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 56. AC Characteristics of the I2C SDA and SCL Pins
Symbol
FSCLI2C
tHDSTAI2C
tLOWI2C
tHIGHI2C
tSUSTAI2C
tHDDATI2C
tSUDATI2C
tSUSTOI2C
tBUFI2C
tSPI2C
Standard Mode
Fast Mode
Min
Max
Min
Max
SCL clock frequency
0
100
0
400
Hold time (repeated) START condition. After this
4.0
–
0.6
–
period, the first clock pulse is generated.
LOW period of the SCL clock
4.7
–
1.3
–
HIGH period of the SCL clock
4.0
–
0.6
–
Setup time for a repeated START condition
4.7
–
0.6
–
Data hold time
0
–
0
–
Data setup time
250
–
100[32]
–
Setup time for STOP condition
4.0
–
0.6
–
Bus free time between a STOP and START
4.7
–
1.3
–
condition
Pulse width of spikes are suppressed by the
–
–
0
50
input filter.
Description
Units
Notes
kHz
s
s
s
s
s
ns
s
s
ns
Figure 15. Definition for Timing for Fast/Standard Mode on the I2C Bus
I2C_SDA
TSUDATI2C
THDSTAI2C
TSPI2C
THDDATI2CTSUSTAI2C
TBUFI2C
I2C_SCL
THIGHI2C TLOWI2C
S
START Condition
TSUSTOI2C
Sr
Repeated START Condition
P
S
STOP Condition
Notes
29. Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
30. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent
duty cycle requirement is met.
31. For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note, AN2015 at http://ww.cypress.com under Application Notes for more information.
32. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement TSUDATI2C  250 ns must then be met. This is automatically the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + TSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-48111 Rev. *K
Page 61 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Packaging Information
This section illustrates the packaging specifications for the CY8C28xxx PSoC devices, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools' dimensions, refer to the Emulator Pod Dimension drawings at http://www.cypress.com..
Packaging Dimensions
Figure 16. 20-pin SSOP (210 Mils) Package Outline, 51-85077
51-85077 *E
Document Number: 001-48111 Rev. *K
Page 62 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Figure 17. 28-pin SSOP (210 Mils) Package Outline, 51-85079
51-85079 *E
Figure 18. 44-pin TQFP (10 × 10 × 1.4 mm) Package Outline, 51-85064
51-85064 *E
Document Number: 001-48111 Rev. *K
Page 63 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Figure 19. 48-pin QFN (7 × 7 × 1.0 mm) Package Outline, 001-45616
001-45616 *D
Important Note For information on the preferred dimensions for mounting QFN packages, see the following application note,
“Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages" available at http://www.amkor.com.
Document Number: 001-48111 Rev. *K
Page 64 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Figure 20. 56-pin SSOP (300 Mils) Package Outline, 51-85062
51-85062 *F
Document Number: 001-48111 Rev. *K
Page 65 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Thermal Impedances
Table 57. Thermal Impedances per Package
Package
20-SSOP
28-SSOP
44-TQFP
48-QFN[34]
56-SSOP
Typical JA [33]
80.8 °C/W
45.4 °C/W
24.0 °C/W
16.7 °C/W
67.5 °C/W
Capacitance on Crystal Pins
Table 58. Typical Package Capacitance on Crystal Pins
Package
20-SSOP
28-SSOP
44-TQFP
48-QFN
56-SSOP
Package Capacitance
Pin9 = 0.0056 pF
Pin11 = 0.006048 pF
Pin13 = 0.006796 pF
Pin15 = 0.006755 pF
Pin16 = 0.009428 pF
Pin18 = 0.008635 pF
Pin17 = 0.008493 pF
Pin19 = 0.008742 pF
Pin27 = 0.007916 pF
Pin31 = 0.007132 pF
Solder Reflow Specifications
Table 59 shows the solder reflow temperature limits that must not be exceeded.
Table 59. Solder Reflow Specifications
Maximum Peak
Temperature (TC)
Maximum Time above
TC – 5 °C
20-SSOP
260 °C
30 seconds
28-SSOP
260 °C
30 seconds
44-TQFP
260 °C
30 seconds
48-QFN
260 °C
30 seconds
56-SSOP
260 °C
30 seconds
Package
Notes
33. TJ = TA + POWER × JA
34. To achieve the thermal impedance specified for the QFN package, refer to Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages
available at http://www.amkor.com for PCB requirements.
35. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Document Number: 001-48111 Rev. *K
Page 66 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Development Tool Selection
This section presents the development tools available for all current PSoC device families including the CY8C28xxx family.
Software
PSoC Designer
Evaluation Tools
At the core of the PSoC development software suite is PSoC
Designer. Utilized by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for over half a
decade. PSoC Designer is available free of charge at
http://www.cypress.com.
All evaluation tools can be purchased from the Cypress Online
Store.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC Programmer is available free of charge
at http://www.cypress.com.
Development Kits
All development kits can be purchased from the Cypress Online
Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the content of specific memory locations. Advanced
emulation features are supported in PSoC Designer. The kit
includes:
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
■
PSoC Designer Software CD
■
Evaluation Board with LCD Module
■
ICE-Cube In-Circuit Emulator
■
MiniProg Programming Unit
■
Pod kit for CY8C29x66 PSoC Family
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
Cat-5 Adapter
■
PSoC Designer Software CD
■
Mini-Eval Programming Board
■
Getting Started Guide
■
110 ~ 240 V Power Supply, Euro-Plug Adapter
■
USB 2.0 Cable
■
ISSP Cable
■
USB 2.0 Cable and Blue Cat-5 Cable
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
Document Number: 001-48111 Rev. *K
Page 67 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Device Programmers
software. The latest PSoC ISSP software for this kit can be
downloaded from http://www.cypress.com. The kit includes:
All device programmers can be purchased from the Cypress
Online Store.
■
CY3207 Programmer Unit
CY3207ISSP In-System Serial Programmer (ISSP)
■
PSoC ISSP Software CD
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
■
110 ~ 240 V Power Supply, Euro-Plug Adapter
■
USB 2.0 Cable
Note The CY3207ISSP programmer needs the PSoC ISSP
software. It is not compatible with the PSoC Programmer
Accessories (Emulation and Programming)
Table 60. Emulation and Programming Accessories
Part #
Pin Package
Pod Kit[36]
Foot Kit[37]
CY8C28243-24PVXI
20-SSOP
CY3250-28XXX
CY3250-20SSOP-FK
CY8C28403-24PVXI
CY8C28413-24PVXI
CY8C28433-24PVXI
CY8C28445-24PVXI
CY8C28452-24PVXI
28-SSOP
CY3250-28XXX
CY3250-28SSOP-FK
CY8C28513-24AXI
CY8C28533-24AXI
CY8C28545-24AXI
44-TQFP
CY3250-28XXX
CY8C28623-24LTXI
CY8C28643-24LTXI
CY8C28645-24LTXI
48-QFN
CY3250-28XXXQFN CY3250-48QFN-FK
CY3250-44TQFP-FK
Adapter[38]
Adapters can be found at
http://www.emulation.com.
Notes
36. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples.
37. Foot kit includes surface mount feet that can be soldered to the target PCB.
38. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 001-48111 Rev. *K
Page 68 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Ordering Information
XRES Pin
RAM (KBytes)
Flash (KBytes)
Analog Outputs
Analog Inputs
Digital I/O Pins
10-bit SAR ADC
Decimators
HW I2C
Limited Analog Blocks
Regular Analog Blocks
Digital Blocks
CapSense
Temperature Range
Ordering Code
Package
The following table lists the CY8C28xxx PSoC devices key package features and ordering codes.
28-Pin (210-Mil) SSOP
CY8C28403-24PVXI
–40 °C to 85 °C
N
12
0
0
2
0
Y
24
8
0
16
1
Y
28-Pin (210-Mil) SSOP
(Tape and Reel)
CY8C28403-24PVXIT
–40 °C to 85 °C
N
12
0
0
2
0
Y
24
8
0
16
1
Y
28-Pin (210-Mil) SSOP
CY8C28413-24PVXI
–40 °C to 85 °C
Y
12
0
4
1
2
Y
24
24
0
16
1
Y
28-Pin (210-Mil) SSOP
(Tape and Reel)
CY8C28413-24PVXIT
–40 °C to 85 °C
Y
12
0
4
1
2
Y
24
24
0
16
1
Y
44-Pin TQFP
CY8C28513-24AXI
–40 °C to 85 °C
Y
12
0
4
1
2
Y
40
40
0
16
1
Y
44-Pin TQFP (Tape and CY8C28513-24AXIT
Reel)
–40 °C to 85 °C
Y
12
0
4
1
2
Y
40
40
0
16
1
Y
48-Pin Sawn QFN
CY8C28623-24LTXI
–40 °C to 85 °C
N
12
6
0
2
2
N
44
10
2
16
1
Y
48-Pin Sawn QFN
(Tape and Reel)
CY8C28623-24LTXIT
–40 °C to 85 °C
N
12
6
0
2
2
N
44
10
2
16
1
Y
28-Pin (210-Mil) SSOP
CY8C28433-24PVXI
–40 °C to 85 °C
Y
12
6
4
1
4
Y
24
24
2
16
1
Y
28-Pin (210-Mil) SSOP
(Tape and Reel)
CY8C28433-24PVXIT
–40 °C to 85 °C
Y
12
6
4
1
4
Y
24
24
2
16
1
Y
44-Pin TQFP
CY8C28533-24AXI
–40 °C to 85 °C
Y
12
6
4
1
4
Y
40
40
2
16
1
Y
44-Pin TQFP (Tape and CY8C28533-24AXIT
Reel)
–40 °C to 85 °C
Y
12
6
4
1
4
Y
40
40
2
16
1
Y
20-Pin (210-Mil) SSOP
CY8C28243-24PVXI
–40 °C to 85 °C
N
12
12
0
2
4
Y
16
16
4
16
1
Y
20-Pin (210-Mil) SSOP
(Tape and Reel)
CY8C28243-24PVXIT
–40 °C to 85 °C
N
12
12
0
2
4
Y
16
16
4
16
1
Y
48-Pin Sawn QFN
CY8C28643-24LTXI
–40 °C to 85 °C
N
12
12
0
2
4
Y
44
44
4
16
1
Y
48-Pin Sawn QFN
(Tape and Reel)
CY8C28643-24LTXIT
–40 °C to 85 °C
N
12
12
0
2
4
Y
44
44
4
16
1
Y
28-Pin (210-Mil) SSOP
CY8C28445-24PVXI
–40 °C to 85 °C
Y
12
12
4
2
4
Y
24
24
4
16
1
Y
28-Pin (210-Mil) SSOP
(Tape and Reel)
CY8C28445-24PVXIT
–40 °C to 85 °C
Y
12
12
4
2
4
Y
24
24
4
16
1
Y
44-Pin TQFP
CY8C28545-24AXI
–40 °C to 85 °C
Y
12
12
4
2
4
Y
40
40
4
16
1
Y
–40 °C to 85 °C
Y
12
12
4
2
4
Y
40
40
4
16
1
Y
44-Pin TQFP (Tape and CY8C28545-24AXIT
Reel)
48-Pin Sawn QFN
CY8C28645-24LTXI
–40 °C to 85 °C
Y
12
12
4
2
4
Y
44
44
4
16
1
Y
48-Pin Sawn QFN
(Tape and Reel)
CY8C28645-24LTXIT
–40 °C to 85 °C
Y
12
12
4
2
4
Y
44
44
4
16
1
Y
28-Pin (210-Mil) SSOP
CY8C28452-24PVXI
–40 °C to 85 °C
Y
8
12
4
1
4
N
24
24
4
16
1
Y
28-Pin (210-Mil) SSOP
(Tape and Reel)
CY8C28452-24PVXIT
–40 °C to 85 °C
Y
8
12
4
1
4
N
24
24
4
16
1
Y
56-Pin SSOP OCD
CY8C28000-24PVXI
–40 °C to 85 °C
Y
12
12
4
2
4
Y
44
44
4
16
1
Y
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Document Number: 001-48111 Rev. *K
Page 69 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Ordering Code Definitions
CY 8 C 28 xxx - SP xxxx
Package Type:
PVX = SSOP Pb-free
LTX = QFN Pb-free
AX = TQFP Pb-free
Thermal Rating:
C = Commercial
I = Industrial
E = Extended
CPU Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
Document Number: 001-48111 Rev. *K
Page 70 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Acronyms
Acronyms Used
Table 61 lists the acronyms that are used in this document.
Table 61. Acronyms Used in this Datasheet
Acronym
AC
Description
Acronym
Description
alternating current
MIPS
million instructions per second
ADC
analog-to-digital converter
OCD
on-chip debug
API
application programming interface
PCB
printed circuit board
complementary metal oxide semiconductor
PDIP
plastic dual-in-line package
CPU
central processing unit
PGA
programmable gain amplifier
CRC
cyclic redundancy check
PLL
phase-locked loop
continuous time
POR
power on reset
CMOS
CT
DAC
DC
digital-to-analog converter
direct current
PPOR
PRS
precision power on reset
pseudo-random sequence
DTMF
dual-tone multi-frequency
PSoC®
ECO
external crystal oscillator
PWM
pulse width modulator
electrically erasable programmable read-only
memory
QFN
quad flat no leads
real time clock
EEPROM
GPIO
general purpose I/O
RTC
ICE
in-circuit emulator
SAR
IDE
integrated development environment
SC
SLIMO
Programmable System-on-Chip
successive approximation
switched capacitor
ILO
internal low speed oscillator
IMO
internal main oscillator
SMP
slow IMO
switch mode pump
I/O
input/output
SOIC
small-outline integrated circuit
IrDA
infrared data association
SPITM
serial peripheral interface
ISSP
in-system serial programming
SRAM
static random access memory
LCD
liquid crystal display
SROM
supervisory read only memory
LED
light-emitting diode
SSOP
shrink small-outline package
LPC
low power comparator
UART
universal asynchronous receiver / transmitter
LVD
low voltage detect
USB
MAC
multiply-accumulate
WDT
universal serial bus
watchdog timer
MCU
microcontroller unit
XRES
external reset
Reference Documents
CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34,
CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical
Reference Manual (TRM) (001-14463)
Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459)
Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 (001-17397)
Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503)
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com.
Document Number: 001-48111 Rev. *K
Page 71 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Document Conventions
Units of Measure
Table 62 lists the unit sof measures.
Table 62. Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
kB
1024 bytes
µs
microsecond
dB
decibels
ms
millisecond
°C
degree Celsius
ns
nanosecond
fF
femto farad
ps
picosecond
pF
picofarad
µV
microvolts
kHz
kilohertz
MHz
megahertz
mVpp
rt-Hz
mV
millivolts
millivolts peak-to-peak
root hertz
nV
nanovolts
k
kilohm
V
volts

ohm
µW
microwatts
W
watt
µA
microampere
mA
milliampere
mm
millimeter
nA
nanoampere
ppm
parts per million
pA
pikoampere
%
mH
millihenry
percent
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.
Glossary
active high
5. A logic signal having its asserted state as the logic 1 state.
6. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous
time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain
stages, and much more.
analog-to-digital
(ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically,
an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs
the reverse operation.
API (Application
Programming
Interface)
A series of software routines that comprise an interface between a computer application and
lower level services and functions (for example, user modules and libraries). APIs serve as
building blocks for programmers that create software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
Bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with
the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally)
reference.
Document Number: 001-48111 Rev. *K
Page 72 of 78
CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
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Glossary (continued)
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or
loss); it is sometimes represented more specifically as, for example, full width at half maximum.
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a
reference level to operate the device.
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital
PSoC block or an analog PSoC block.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring
data from one device to another. Usually refers to an area reserved for IO operations, into
which data is read, or from which data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as
it is received from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets
with similar routing patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented
using vector notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is
sometimes used to synchronize different logic blocks.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously
satisfy predetermined amplitude requirements.
compiler
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register,
is set to ‘1’.
crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric
crystal is less sensitive to ambient temperature than other circuit components.
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear
check (CRC)
feedback shift register. Similar calculations may be used for a variety of other purposes such as
data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location
to the central processing unit and vice versa. More generally, a set of signals used to convey
data between digital functions.
debugger
A hardware and software system that allows the user to analyze the operation of the system
under development. A debugger usually allows the developer to step through the firmware one
step at a time, set break points, and analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
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Glossary (continued)
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC
generator, pseudo-random number generator, or SPI.
digital-to-analog
(DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analogto-digital (ADC) converter performs the reverse operation.
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
emulator
Duplicates (provides an emulation of) the functions of one system with a different system, so that
the second system appears to behave like the first system.
external reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and
blocks to stop and return to a pre-defined state.
flash
An electrically programmable and erasable, non-volatile technology that provides users with the
programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means
that the data is retained when power is off.
Flash block
The smallest amount of Flash ROM space that may be programmed at one time and the smallest
amount of Flash space that may be protected. A Flash block holds 64 bytes.
frequency
The number of cycles or events per unit of time, for a periodic function.
gain
The ratio of output current, voltage, or power to input current, voltage, or power, respectively.
Gain is usually expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an
Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The
original system was created in the early 1980s as a battery control interface, but it was later used
as a simple internal bus system for building control electronics. I2C uses only two bi-directional
pins, clock and data, both running at +5 V and pulled high with resistors. The bus operates at 100
kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows users to test the project in a hardware environment, while
viewing the debugging device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event
external to that process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the M8C receives a hardware
interrupt. Many interrupt sources may each exist with its own priority and individual ISR code
block. Each ISR code block ends with the RETI instruction, returning the device to the point in
the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a
(LVD)
selected threshold.
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Glossary (continued)
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside
a PSoC by interfacing to the Flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are
cascaded in width, the master device is the one that controls the timing for data exchanges
between the cascaded devices and an external interface. The controlled device is called the
slave device.
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition
to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason
for this is to permit the realization of a controller with a minimal quantity of chips, thus
achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of
the controller. The microcontroller is normally not used for general-purpose computation as is a
microprocessor.
mixed-signal
The reference to a circuit containing both analog and digital techniques and components.
modulator
A device that imposes a signal on a carrier.
noise
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
A circuit that may be crystal controlled and is used to generate a clock frequency.
parity
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the
sum of all the digits of the binary data either always even (even parity) or always odd (odd parity).
phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative
to a reference signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC
device and their physical counterparts in the printed circuit board (PCB) package. Pinouts
involve pin numbers as a link between schematic and PCB design (both being computer generated
files) and may also involve pin names.
port
A group of pins, usually eight.
power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is
one type of hardware reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-onChip™ is a trademark of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied measurand
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out
and new data can be written in.
register
A storage device with a specific capacity, such as a bit or byte.
reset
A means of bringing a system back to a know state. See hardware reset and software reset.
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Glossary (continued)
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but
new data cannot be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one
value to another.
shift register
A memory storage device that sequentially shifts a word either left or right to output a stream of
serial data.
slave device
A device that allows another device to control the timing for data exchanges between two
devices. Or when devices are cascaded in width, the slave device is the one that allows another
device to control the timing of data exchanges between the cascaded devices and an external
interface. The controlling device is called the master device.
SRAM
An acronym for static random access memory. A memory device allowing users to store and
retrieve data at a high rate of speed. The term static is used because, after a value has been
loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is
removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the
device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be
accessed in normal user code, operating from Flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next
character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does
not drive any value in the Z state and, in many respects, may be considered to be disconnected
from the rest of the circuit, allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data
and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and
configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high
level API (Application Programming Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified
during normal program execution and not just during initialization. Registers in bank 1 are most
likely to be modified only during the initialization phase of the program.
VDD
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually
5 V or 3.3 V.
VSS
A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified
period of time.
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Document History Page
Document Title: CY8C28243, CY8C28403, CY8C28413, CY8C28433, CY8C28445, CY8C28452, CY8C28513, CY8C28533,
CY8C28545, CY8C28623, CY8C28643, CY8C28645 PSoC® Programmable System-on-Chip™
Document Number: 001-48111
Origin of
Submission
Revision
ECN
Description of Change
Change
Date
**
2593460 BTK/PYRS
10/20/08
New document (Revision **).
*A
2652217 BTK/PYRS
02/02/09
Extensive updates to content.
Added registers maps.
Updated Getting Started section
Updated Development Tools section
Added some SAR10 ADC specifications.
Added more analog system figures
*B
2675937
BTK
03/18/09
Updated DC Analog Reference Specifications tables
Minor content updates
*C
2679015
HMI
03/26/2009
Post to external web.
*D
2750217
TDU
08/10/09
Updates to Electrical Specifications section
Minor content updates
*E
2768143
TDU
09/23/09
Updated DC Operational Amplifier, DC Analog Reference, DC SAR10ADC,
and DC POR specifications; Added Figure 15 and Figure 16; Updated AC
TypeE-Operational and AC SAR10ADC specifications
*F
2805324
ALH
11/11/09
Added Contents page. Updated Electrical Specifications.
*G
2902396
NJF
03/30/2010
Updated Cypress website links.
Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum
Ratings.
Updated DC SAR10 ADC Specifications.
Modified Note 23.
Removed AC Analog Mux Bus Specifications, Third Party Tools and Build a
PSoC Emulator into your Board.
Updated Packaging Information and Ordering Code Definitions.
Updated links in Sales, Solutions, and Legal Information.
*H
3063584
NJF
10/20/10
Added PSoC Device Characteristics table .
Added DC I2C Specifications table.
Added F32K_U max limit.
Added Tjit_IMO specification, removed existing jitter specifications.
Updated Analog reference tables.
Updated Units of Measure, Acronyms, Glossary, and References sections.
Updated solder reflow specifications.
No specific changes were made to AC Digital Block Specifications table and
I2C Timing Diagram. They were updated for clearer understanding.
Updated Figure 13 since the labelling for y-axis was incorrect.
Template and styles update.
*I
3148779
NJF
01/20/11
Added Footnote # 34 to Thermal Impedances section.
Table 7. 56-Pin Part Pinout (SSOP) (page 15) - Pin#28 - Pin Name changed
to"VSS".
Table 5. 44-Pin Part Pinout (TQFP) (page 13) - Pin#17 - Pin Type changed
to"Power”.
Under DC SAR10 ADC Specifications table, for parameter VVREFSAR10, Max
value changed from 4.95 V to VDD – 0.3 V.
Updated Table 59, “Solder Reflow Specifications,” on page 66 as per spec
25-00090.
*J
3598237 LURE/XZNG
04/24/2012
Changed the PWM description string from “8- to 32-bit” to “8- and 16-bit”.
*K
3758002
GULA
10/01/2012
Updated Packaging Information (spec 001-45616 (Changed revision from
*B to *D), spec 51-85062 (Changed revision from *D to *F)).
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
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cypress.com/go/memory
cypress.com/go/image
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USB Controllers
Wireless/RF
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cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2008-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-48111 Rev. *K
Revised October 1, 2012
Page 78 of 78
PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.