CYPRESS CY8C24633

CY8C24633
PSoC® Programmable System-on-Chip
Features
■
Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ 8 × 8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3.0 to 5.25V Operating Voltage
❐ Industrial Temperature Range: -40°C to +85°C
■
Advanced Peripherals (PSoC® Blocks)
❐ Four Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 8-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI Masters or Slaves
• Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
❐ High speed 8-bit SAR ADC optimized for motor control
■
Precision, Programmable Clocking
❐ Internal ±5% 24/48 MHz Oscillator
❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
Cypress Semiconductor Corporation
Document Number: 001-20160 Rev. *D
•
■
Flexible On-Chip Memory
❐ 8K Bytes Flash Program Storage 50,000 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■
Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐ Up to eight Analog Inputs on GPIO plus two additional analog
inputs with restricted routing
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
■
Additional System Resources
2
❐ I C Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■
Complete Development Tools
❐ Free development Software (PSoC Designer™)
❐ Full-Featured In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 20, 2010
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CY8C24633
Block Diagram
Port 3
Port 2
Port 1 Port 0
Analog
Drivers
PSoC CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
SROM
Global Analog Interconnect
Flash 8K
CPUCore (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
Analog
Block Array
2 Columns
4 Blocks
1 Row
4 Blocks
Digital
Clocks
Multiply
Accum.
ANALOG SYSTEM
SAR8 ADC
Decimator
I2C
Analog
Ref
Analog
Input
Muxing
POR and LVD
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
Document Number: 001-20160 Rev. *D
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CY8C24633
Contents
PSoC Functional Overview .............................................. 4
The PSoC Core ........................................................... 4
The Digital System ...................................................... 4
The Analog System ..................................................... 5
Additional System Resources ..................................... 6
PSoC Device Characteristics ...................................... 6
Getting Started .................................................................. 7
Application Notes ........................................................ 7
Development Kits ........................................................ 7
Training ....................................................................... 7
CYPros Consultants .................................................... 7
Solutions Library .......................................................... 7
Technical Support ....................................................... 7
Development Tools .......................................................... 7
PSoC Designer Software Subsystems ........................ 7
In-Circuit Emulator ....................................................... 8
Designing with PSoC Designer ....................................... 8
Select Components ..................................................... 8
Configure Components ............................................... 8
Organize and Connect ................................................ 8
Generate, Verify, and Debug ....................................... 8
Pinouts .............................................................................. 9
28-Pin Part Pinout ....................................................... 9
56-Pin Part Pinout ..................................................... 10
Document Number: 001-20160 Rev. *D
Register Reference ......................................................... 11
Register Conventions ................................................ 11
Register Mapping Tables .......................................... 11
Electrical Specifications ................................................ 14
Absolute Maximum Ratings ...................................... 15
Operating Temperature ............................................ 15
DC Electrical Characteristics ..................................... 16
AC Electrical Characteristics ..................................... 29
Thermal Impedances ................................................ 40
Capacitance on Crystal Pins .................................... 40
Solder Reflow Peak Temperature ............................. 40
Ordering Information ...................................................... 41
Packaging Information ................................................... 42
Acronyms ........................................................................ 43
Acronyms Used ......................................................... 43
Reference Documents .................................................... 43
Document Conventions ................................................. 44
Units of Measure ....................................................... 44
Numeric Conventions ................................................ 44
Glossary .......................................................................... 45
Document History Page ................................................. 50
Sales, Solutions, and Legal Information ...................... 51
Worldwide Sales and Design Support ....................... 51
Products .................................................................... 51
PSoC® Solutions ....................................................... 51
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PSoC Functional Overview
The Digital System
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references.
Figure 1. Digital System Block Diagram
Port 3
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system
interrupt on high level, low level, and change from last read.
Document Number: 001-20160 Rev. *D
ToAnalog
System
8
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
8
Row Output
Configuration
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to
±5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
To System Bus
Port 0
DIGITAL SYSTEM
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose I/O).
Memory encompasses 8 KB of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
Port 1
Digital PSoC Block Array
The PSoC Core
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 11 vectors,
to simplify programming of real time embedded events. Program
execution is timed and protected using the included Sleep and
Watch Dog Timers (WDT).
Port 2
Digital Clocks
FromCore
The PSoC architecture, as illustrated in the Block Diagram, is
comprised of four main areas: PSoC Core, Digital System,
Analog System, and System Resources. Configurable global
buses allows all the device resources to be combined into a
complete custom system. The PSoC CY8C24x33 family can
have up to three I/O ports that connect to the global digital and
analog interconnects, providing access to four digital blocks and
four analog blocks.
Row Input
Configuration
The PSoC family consists of many programmable
system-on-chip with on-chip Controller devices. These devices
are designed to replace multiple traditional MCU-based system
components with one, low cost single-chip programmable
device. PSoC devices include configurable blocks of analog and
digital logic, as well as programmable interconnects. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM
data memory, and configurable I/O are included in a range of
convenient pinouts and packages.
8
GOE[7:0]
GOO[7:0]
Digital peripheral configurations include those listed below.
■
PWMs (8 to 32 bit)
■
PWMs with Dead Band (8 to 32 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity (up to 1)
■
SPI master and slave (up to 1)
■
I2C slave and master (1 available as a System Resource)
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA (up to 1)
■
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks are connected to any GPIO through a series
of global buses that route any signal to any pin. The buses also
allow signal multiplexing and performing logic operations. This
configurability frees your designs from the constraints of a fixed
peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 6.
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The Analog System
The Analog system is composed of an 8-bit SAR ADC and four
configurable blocks. The programmable 8-bit SAR ADC is an
optimized ADC that runs up to 300 Ksps, with monotonic
guarantee. It also has the features to support a motor control
application.
Figure 2. Analog System Block Diagram
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
Each analog block is comprised of an opamp circuit allowing the
creation of complex analog signal flows. Analog peripherals are
very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog
functions (most available as user modules) are listed below.
P0[1]
P0[0]
■
Filters (2 and 4 pole band pass, low-pass, and notch)
P2[1]
■
Amplifiers (up to 2, with selectable gain to 48x)
■
Instrumentation amplifiers (1 with selectable gain to 93x)
■
Comparators (up to 2, with 16 selectable thresholds)
■
DACs (up to 2, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 2, with 6- to 9-bit resolution)
■
High current output drivers (two with 30 mA drive as a Core
Resource)
■
1.3V reference (as a System Resource)
■
DTMF dialer
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
AGNDIn RefIn
P0[7]
P2[3]
P2[6]
P2[4]
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
Block Array
ACB00
ACB01
ASD11
ASC21
P0[7:0]
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks. The Analog Column 0 contains the SAR8 ADC block
rather than the standard SC blocks.
ACI2[3:0]
8-Bit SAR ADC
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-20160 Rev. *D
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Additional System Resources
■
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include a multiplier, decimator, low voltage
detection, and power on reset. Brief statements describing the
merits of each system resource are presented below.
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
■
■
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math as well
as digital filters.
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3
analog blocks. The following table lists the resources available for specific PSoC device groups.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
CY8C29x66
up to 64
CY8C28xxx
up to 44
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
4
16
up to 12
4
up to 3
up to 12
up to 44
up to 4
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
SAR
ADC
4
12
2K
32 K
No
up to 6
up to
12 + 4[1]
1K
16 K
Yes
CY8C27x43
up to 44
2
8
up to 12
4
4
12
256
16 K
No
CY8C24x94
up to 56
1
4
up to 48
2
2
6
1K
16 K
No
CY8C24x23A
up to 24
1
4
up to 12
2
2
6
256
4K
No
CY8C23x33
up to 26
1
4
up to 12
2
2
4
256
8K
Yes
CY8C24x33
up to 26
1
4
up to 12
2
2
4
256
8K
Yes
[1]
CY8C22x45
up to 38
2
8
up to 38
0
4
6
1K
16 K
No
CY8C21x45
up to 24
1
4
up to 24
0
4
6[1]
512
8K
Yes
CY8C21x34
up to 28
1
4
up to 28
0
2
4[1]
512
8K
No
CY8C21x23
up to 16
1
4
up to 8
0
2
4[1]
256
4K
No
CY8C20x34
up to 28
0
0
up to 28
0
0
3[1,2]
512
8K
No
0
[1,2]
up to
2K
up to
32 K
No
CY8C20xx6
up to 36
0
0
up to 36
0
3
Notes
1. Limited analog functionality.
2. Two analog blocks and one CapSense®.
Document Number: 001-20160 Rev. *D
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Getting Started
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
For in depth information, along with detailed programming
details, see the Technical Reference Manual for this PSoC
device.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at http://www.cypress.com.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs and are available at
http://www.cypress.com.
Development Kits
PSoC Development Kits are available online from Cypress at
http://www.cypress.com and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
Training
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
On-Chip Controllers that match your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
Free PSoC technical training (on demand, webinars, and
workshops) is available online at http://www.cypress.com. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com and refer to
CYPros Consultants.
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Solutions Library
Code Generation Tools
Visit our growing library of solution focused designs at
http://www.cypress.com. Here you can find various application
designs that include firmware and hardware design files that
enable you to complete your designs quickly.
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Technical Support
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
For assistance with technical issues, search KnowledgeBase
articles and forums at http://www.cypress.com. If you cannot find
an answer to your question, call technical support at
1-800-541-4736.
Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
Document Number: 001-20160 Rev. *D
Hybrid Designs
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
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Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select components
2. Configure components
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I2C-bus, for example), and the logic to control how they interact
with one another (called valuators).
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed signal
varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
Document Number: 001-20160 Rev. *D
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in the PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Organize and Connect
You can build signal chains at the chip level by interconnecting
user modules to each other and the I/O pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run-time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
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Pinouts
The PSoC CY8C24633 is available in 28-pin SSOP and 56-pin SSOP OCD packages. Refer to the following information for details.
Every port pin (labeled with a “P”), except Vss, Vdd, and XRES in the following tables and illustrations, is capable of Digital I/O.
28-Pin Part Pinout
The 28-pin part is for the CY8C24633 PSoC device.
Table 2. 28-Pin Part Pinout (SSOP)
Pin
No. Digital Analog
Pin
Name
Description
AIO, P0[7]
1
28
Vdd
IO, P0[5]
2
27
P0[6], AIO, AnColMux and ADC IP
IO, P0[3]
3
26
P0[4], AIO, AnColMux and ADC IP
AIO, P0[1]
4
25
P0[2], AIO, AnColMux and ADC IP
Analog Col Mux IP and Column
O/P and ADC IP
IO, P2[7]
5
24
P0[0], AIO, AnColMux and ADC IP
IO, P2[5]
6
23
P2[6], IO
P0[1]
Analog Col Mux IP and ADC IP
AIO, P2[3]
7
22
AIO, P2[1]
8
21
P2[4], IO
P2[2], AIO
1
I/O
I
P0[7]
Analog Col Mux IP and ADC IP
2
I/O
I/O
P0[5]
Analog Col Mux IP and Column
O/P and ADC IP
3
I/O
I/O
P0[3]
4
I/O
5
I/O
P2[7]
GPIO
AVref, IO, P3[0]
9
20
P2[0], AIO
6
I/O
P2[5]
GPIO
I2C SCL, IO, P1[7]
10
19
XRES
7
I/O
I
P2[3]
Direct switched capacitor input
I2C SDA, IO, P1[5]
11
18
P1[6], IO
IO, P1[3]
12
17
P1[4], IO, EXTCLK
8
I/O
I
P2[1]
Direct switched capacitor input
I2C SCL, ISSP SCL, XTALin, IO, P1[1]
13
16
P1[2], IO
Vss
14
15
P1[0], IO, XTALout, ISSP SDA, I2CSDA
9
I/O
I
Figure 3. CY8C24633 PSoC Device
AVref
P3[0]
[3]
GPIO/ADC Vref (optional)
10
I/O
P1[7]
I2C SCL
11
I/O
P1[5]
I2C SDA
P1[3]
GPIO
12
I/O
13
I/O
P1[1][4] GPIO, Xtal input, I2C SCL, ISSP
SCL
Power
14
Vss
Ground pin
P1[0][4] GPIO, Xtal output, I2C SDA, ISSP
SDA
15
I/O
16
I/O
P1[2]
17
I/O
P1[4]
GPIO, external clock IP
18
I/O
P1[6]
GPIO
XRES
External reset
19
GPIO
20
I/O
I
P2[0]
Direct switched capacitor input
21
I/O
I
P2[2]
Direct switched capacitor input
22
I/O
P2[4]
GPIO
23
I/O
P2[6]
GPIO
24
I/O
I
P0[0]
Analog Col Mux IP and ADC IP
25
I/O
I
P0[2]
Analog Col Mux IP and ADC IP
26
I/O
I
P0[4]
Analog Col Mux IP and ADC IP
27
I/O
I
P0[6]
Analog Col Mux IP and ADC IP
Vdd
Supply voltage
28
SSOP
Power
LEGEND A = Analog, I = Input, and O = Output
Notes
3. Even though P3[0] is an odd port, it resides on the left side of the pinout.
4. ISSP pin, which is not High Z at POR.
Document Number: 001-20160 Rev. *D
Page 9 of 51
[+] Feedback
CY8C24633
56-Pin Part Pinout
The 56-pin OCD (On-Chip Debug) part is for the CY8C24633 (CY8C24033) PSoC device.
Note OCD parts are only used for in-circuit debugging. OCD parts are NOT available for production.
Table 3. 56-Pin OCD Part Pinout (SSOP)
Pin
No.
Name
1
NC
2
P0[7]
Analog column mux input: AI
3
P0[5]
Analog column mux input and column output: AIO
4
P0[3]
Analog column mux input and column output: AIO
5
P0[1]
Analog column mux input: AI
6
P2[7]
7
P2[5]
8
P2[3]
Direct switched capacitor block input: AI
9
P2[1]
Direct switched capacitor block input: AI
10
NC
No internal connection
11
P3[0]
NC
No internal connection
13
NC
GPIO/ADC Vref (optional)
No internal connection
14
OCDE OCD even data I/O
15
OCDO OCD odd data output
16
NC
No internal connection
17
NC
No internal connection
18
NC
No internal connection
19
NC
No internal connection
20
NC
No internal connection
21
NC
No internal connection
22
NC
No internal connection
23
P1[7]
I2C Serial Clock (SCL)
24
P1[5]
I2C Serial Data (SDA)
25
NC
No internal connection
27
OCD
SSOP
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Vdd
P0[6],AI
P0[4],AIO
P0[2],AIO
P0[0],AI
P2[6],External VRef
P2[4],External AGND
P2[2],AI
P2[0],AI
NC
NC
NC
NC
CCLK
HCLK
XRES
NC
NC
NC
P3[1]
NC
NC
P1[6]
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA,SDATA
NC
NC
Not For Production
P1[3]
Vss
Ground connection
29
NC
No internal connection
NC
No internal connection
31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
P1[1][5] Crystal (XTALin), I2C Serial Clock (SCL)
28
30
NC
AI,P0[7]
AIO,P0[5]
AIO,P0[3]
AI,P0[1]
P2[7]
P2[5]
AI,P2[3]
AI,P2[1]
NC
GPIO/ADC VRef,P3[0]
NC
NC
OCDE
OCDO
NC
NC
NC
NC
NC
NC
NC
I2CSCL, P1[7]
I2CSDA, P1[5]
NC
P1[3]
SCLK, I2CSCL, XTALin,P1[1]
Vss
No internal connection
12
26
Figure 4. CY8C24033 OCD PSoC Device
Description
P1[0][5] Crystal (XTALout), I2C Serial Data (SDA)
32
P1[2]
33
P1[4]
34
P1[6]
35
NC
36
NC
37
P3[1]
38
Optional External Clock Input (EXTCLK)
Pin No. Name
Description
44
NC
No internal connection
45
NC
No internal connection
46
NC
No internal connection
47
NC
No internal connection
No internal connection
48
P2[0] Direct switched capacitor block input: AI
No internal connection
49
P2[2] Direct switched capacitor block input: AI
GPIO
50
P2[4] External Analog Ground (AGND)
NC
No internal connection
51
P2[6] External Voltage Reference (VRef)
39
NC
No internal connection
52
P0[0] Analog column mux input: AI
40
NC
No internal connection
53
P0[2] Analog column mux input and column output: AIO
41
XRES Active high pin reset with internal pull down
54
P0[4]
Analog column mux input and column output: AIO
42
HCLK
OCD high speed clock output
55
P0[6]
Analog column mux input: AI
43
CCLK
OCD CPU clock output
56
Vdd
Supply voltage
LEGEND A = Analog, I = Input, O = Output.
Note
5. ISSP pin, which is not High Z at POR.
Document Number: 001-20160 Rev. *D
Page 10 of 51
[+] Feedback
CY8C24633
Register Reference
This section lists the registers of the CY8C24633 PSoC device by using mapping tables, in offset order.
Register Conventions
Register Mapping Tables
The register conventions specific to this section are listed in the
following table.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks. The XIO bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XIO bit
is set the user is in Bank 1.
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 001-20160 Rev. *D
Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
Page 11 of 51
[+] Feedback
CY8C24633
Table 4. Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
Addr (0,Hex) Access
Name
00
RW
01
RW
02
RW
03
RW
04
RW
05
RW
06
RW
07
RW
08
RW
09
RW
0A
RW
0B
RW
0C
RW
0D
RW
0E
RW
0F
RW
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
DBB00DR0
20
#
AMX_IN
DBB00DR1
21
W
DBB00DR2
22
RW
DBB00CR0
23
#
ARF_CR
DBB01DR0
24
#
CMP_CR0
DBB01DR1
25
W
ASY_CR
DBB01DR2
26
RW
CMP_CR1
DBB01CR0
27
#
SARADC_DL
DCB02DR0
28
#
DCB02DR1
29
W
SARADC_C0
DCB02DR2
2A
RW
SARADC_C1
DCB02CR0
2B
#
DCB03DR0
2C
#
TMP_DR0
DCB03DR1
2D
W
TMP_DR1
DCB03DR2
2E
RW
TMP_DR2
DCB03CR0
2F
#
TMP_DR3
30
ACB00CR3
31
ACB00CR0
32
ACB00CR1
33
ACB00CR2
34
ACB01CR3
35
ACB01CR0
36
ACB01CR1 *
37
ACB01CR2 *
38
39
3A
3B
3C
3D
3E
3F
Blank fields are reserved.
# Access is bit specific.
Document Number: 001-20160 Rev. *D
Addr (0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
Name
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
#
#
RW
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
Addr (0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
Access
Name
RW
RW
RW
RW
RW
RW
RW
RW
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR3
INT_MSK3
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
RW
RW
RW
RW
RW
RW
RW
CPU_F
CPU_SCR1
CPU_SCR0
Addr (0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
#
#
Page 12 of 51
[+] Feedback
CY8C24633
Table 5. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
Addr (1,Hex) Access
Name
00
RW
01
RW
02
RW
03
RW
04
RW
05
RW
06
RW
07
RW
08
RW
09
RW
0A
RW
0B
RW
0C
RW
0D
RW
0E
RW
0F
RW
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
DBB00FN
20
RW
CLK_CR0
DBB00IN
21
RW
CLK_CR1
DBB00OU
22
RW
ABF_CR0
23
AMD_CR0
DBB01FN
24
RW
DBB01IN
25
RW
DBB01OU
26
RW
AMD_CR1
27
ALT_CR0
DCB02FN
28
RW
DCB02IN
29
RW
DCB02OU
2A
RW
2B
DCB03FN
2C
RW
TMP_DR0
DCB03IN
2D
RW
TMP_DR1
DCB03OU
2E
RW
TMP_DR2
2F
TMP_DR3
30
ACB00CR3
31
ACB00CR0
32
ACB00CR1
33
ACB00CR2
34
ACB01CR3
35
ACB01CR0
36
ACB01CR1
37
ACB01CR2 *
38
39
3A
3B
3C
3D
3E
3F
Blank fields are reserved.
# Access is bit specific.
Document Number: 001-20160 Rev. *D
Addr (1,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
Addr (1,Hex)
80
81
82
83
ASD11CR0
84
ASD11CR1
85
ASD11CR2
86
ASD11CR3
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
SARADC_TRS
A8
SARADC_TRCL
A9
SARADC_TRCH
AA
SARADC_C2
AB
SARADC_LCR
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
Access
Name
RW
RW
RW
RW
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
RW
RW
RW
RW
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
RW
RW
RW
#
RW
IMO_TR
ILO_TR
BDG_TR
ECO_TR
RW
RW
RW
RW
RW
RW
RW
CPU_F
FLS_PR1
CPU_SCR1
CPU_SCR0
Addr (1,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
W
W
RW
W
RL
RW
#
#
Page 13 of 51
[+] Feedback
CY8C24633
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C24633 PSoC device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted.
Refer to Table 22 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
Figure 5a. IMO Frequency Trim Options
5.25
SLIMO Mode = 0
Figure 5. Voltage versus CPU Frequency
5.25
4.75
Vdd Voltage
Vdd Voltage
lid g
Va ratin n
pe io
O Reg
4.75
SLIMO
Mode=1
SLIMO
Mode=0
SLIMO
Mode=1
SLIMO
Mode=0
3.60
3.00
3.00
93 kHz
3 MHz
CPU Frequency
Document Number: 001-20160 Rev. *D
12 MHz
24 MHz
93 kHz
6 MHz
12 MHz
24 MHz
IMO Frequency
Page 14 of 51
[+] Feedback
CY8C24633
Absolute Maximum Ratings
Table 6. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage Temperature
Min
-55
Typ
25
–
125
See
package
label
-40
-0.5
Vss - 0.5
Vss - 0.5
-25
2000
–
–
See
package
label
72
hours
–
–
–
–
–
–
–
+85
+6.0
Vdd + 0.5
Vdd + 0.5
+50
–
200
TBAKETEMP Bake temperature
TBAKETIME
Bake time
TA
Vdd
VIO
VIOZ
IMIO
ESD
LU
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
DC Voltage Applied to Tri-state
Maximum Current into any Port Pin
Electro Static Discharge Voltage
Latch Up Current
Max
+100
Units
Notes
o
C Higher storage temperatures
reduce data retention time.
Recommended storage temperature is +25oC ± 25oC. Extended
duration storage temperatures
above 65oC degrade reliability.
o
C
o
C
V
V
V
mA
V
mA
Human Body Model ESD.
Operating Temperature
Table 7. Operating Temperature
Symbol
Description
Min
Typ
Max
Units
TA
Ambient Temperature
-40
–
+85
oC
TJ
Junction Temperature
-40
–
+100
oC
Document Number: 001-20160 Rev. *D
Notes
The temperature rise from ambient to
junction is package specific. See
Thermal Impedances by Package on
page 40. The user must limit the
power consumption to comply with
this requirement.
Page 15 of 51
[+] Feedback
CY8C24633
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 8. DC Chip-Level Specifications
Symbol
Description
Vdd
Supply Voltage
IDD
Supply Current
Min
3.0
–
Typ
–
5
Max
5.25
8
Units
V
mA
IDD3
Supply Current
–
3.3
6.0
mA
ISB
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT.[6]
–
3
6.5
μA
ISBH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT at high temperature.[6]
–
4
25
μA
ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal.[6]
–
4
7.5
μA
ISBXTLH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal at high
temperature.[6]
–
5
26
μA
VREF
Reference Voltage (Bandgap)
1.28
1.30
1.33
V
Notes
See Table 18 on page 26.
Conditions are Vdd = 5.0V, TA = 25 oC,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz, VC2 = 93.75
kHz, VC3 = 93.75 kHz, analog power
= off. SLIMO mode = 0. IMO = 24 MHz.
Conditions are Vdd = 3.3V, TA = 25 oC,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz, VC2 = 93.75
kHz, VC3 = 93.75 kHz, analog power
= off. SLIMO mode = 0. IMO = 24 MHz.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V, -40 oC ≤
TA ≤ 55oC, analog power = off.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V, 55 oC <
TA ≤ 85oC, analog power = off.
Conditions are with properly loaded, 1
μW max, 32.768 kHz crystal. Vdd =
3.3V, -40 oC ≤ TA ≤ 55oC, analog
power = off.
Conditions are with properly loaded,
1μW max, 32.768 kHz crystal. Vdd =
3.3 V, 55 oC < TA ≤ 85oC, analog power
= off.
Trimmed for appropriate Vdd.
Vdd > 3.0V.
Note
6. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have
similar functions enabled.
Document Number: 001-20160 Rev. *D
Page 16 of 51
[+] Feedback
CY8C24633
DC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9. 5V and 3.3V DC GPIO Specifications
Symbol
Description
RPU
Pull Up Resistor
Pull Down Resistor
RPD
High Output Level
VOH
Min
4
4
Vdd – 1.0
Typ
5.6
5.6
–
Max
8
8
–
Units
kΩ
kΩ
V
VOL
Low Output Level
–
–
0.75
V
IOH
IOL
VIL
VIH
VH
IIL
CIN
High Level Source Current
Low Level Sink Current
Input Low Level
Input High Level
Input Hysterisis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
10
25
–
2.1
–
–
–
–
–
–
–
60
1
3.5
–
–
0.8
–
–
10
mA
mA
V
V
mV
nA
pF
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Document Number: 001-20160 Rev. *D
Notes
IOH = 10 mA, Vdd = 4.75 to 5.25V
(maximum 40 mA on even port pins
(for example, P0[2], P1[4]), maximum
40 mA on odd port pins (for example,
P0[3], P1[5])). 80 mA maximum
combined IOH budget.
IOL = 25 mA, Vdd = 4.75 to 5.25V
(maximum 100 mA on even port pins
(for example, P0[2], P1[4]), maximum
100 mA on odd port pins (for example,
P0[3], P1[5])). 100 mA maximum
combined IOH budget.
Vdd = 3.0 to 5.25.
Vdd = 3.0 to 5.25.
Gross tested to 1 μA.
Package and pin dependent. Temp =
25oC.
Package and pin dependent. Temp =
25oC.
Page 17 of 51
[+] Feedback
CY8C24633
DC Operational Amplifier Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at
25°C and are for design guidance only.
Table 10. 5-V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
Min
Typ
Max
Units
–
–
–
–
–
–
1.6
1.3
1.2
7.0
20
4.5
10
8
7.5
35.0
–
9.5
VCMOA
Common Mode Voltage Range
Common Mode Voltage Range (high power
or high opamp bias)
0.0
0.5
–
–
Vdd
Vdd - 0.5
GOLOA
Open Loop Gain
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
High Output Voltage Swing (internal
signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Low Output Voltage Swing (internal
signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Supply Current (including associated
AGND buffer)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
Supply Voltage Rejection Ratio
60
60
80
–
–
–
–
–
–
mV
mV
mV
μV/oC
pA
Gross tested to 1 μA.
pF
Package and pin dependent.
Temp = 25oC.
V
The common-mode input voltage
V
range is measured through an
analog output buffer. The specification includes the limitations
imposed by the characteristics of
the analog output buffer.
Specification is applicable at high
dB
power. For all other bias modes
dB
(except high power, high opamp
dB
bias), minimum is 60 dB.
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
–
–
–
–
–
52
300
600
1200
2400
4600
80
400
800
1600
3200
6400
–
μA
μA
μA
μA
μA
dB
TCVOSOA
IEBOA
CINOA
VOHIGHOA
VOLOWOA
ISOA
PSRROA
Document Number: 001-20160 Rev. *D
Notes
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd 1.25V) ≤ VIN ≤ Vdd.
Page 18 of 51
[+] Feedback
CY8C24633
Table 11. 3.3-V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOA
Input offset voltage (absolute value)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
–
–
–
1.65
1.32
–
10
8
–
mV
mV
mV
Notes
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
TCVOSOA
Average input offset voltage drift
–
7.0
35.0
µV/°C
IEBOA
Input leakage current (port 0 analog pins)
–
20
–
pA
Gross tested to 1 μA
CINOA
Input capacitance (port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 °C
VCMOA
Common mode voltage range
0.2
–
VDD – 0.2
V
The common-mode input voltage
range is measured through an
analog output buffer. The
specification includes the limitations
imposed by the characteristics of the
analog output buffer.
GOLOA
Open loop gain
Power = low, ppamp Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
60
60
80
–
–
–
–
–
–
dB
dB
dB
VOHIGHOA
High output voltage swing (internal signals)
Power = low, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
VDD – 0.2
VDD – 0.2
VDD – 0.2
–
–
–
–
–
–
V
V
V
VOLOWOA
Low output voltage swing (internal signals)
Power = low, ppamp Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
ISOA
Supply current (including associated AGND
buffer)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = medium, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
–
–
–
–
–
–
150
300
600
1200
2400
–
200
400
800
1600
3200
–
μA
μA
μA
μA
μA
μA
Supply voltage rejection ratio
64
80
–
dB
PSRROA
Specification is applicable at low
Opamp bias. For high Opamp bias
mode (except high power, high
Opamp bias), minimum is 60 dB.
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
VSS ≤ VIN ≤ (VDD – 2.25) or
(VDD – 1.25 V) ≤ VIN ≤ VDD
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 12. DC Low Power Comparator Specifications
Symbol
VREFLPC
ISLPC
VOSLPC
Description
Low Power Comparator (LPC) Reference
Voltage Range
LPC Supply Current
LPC Voltage Offset
Document Number: 001-20160 Rev. *D
Min
0.2
Typ
–
Max
Vdd - 1
Units
V
–
–
10
2.5
40
30
μA
mV
Notes
Page 19 of 51
[+] Feedback
CY8C24633
DC Analog Output Buffer Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 13. 5V DC Analog Output Buffer Specifications
Symbol
CL
Description
Load Capacitance
Min
–
Typ
–
Max
200
Units
pF
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
Common-Mode Input Voltage Range
Output Resistance
Power = Low
Power = High
VOHIGHOB High Output Voltage Swing
(Load = 32Ω to Vdd/2)
Power = Low
Power = High
VOLOWOB Low Output Voltage Swing
(Load = 32Ω to Vdd/2)
Power = Low
Power = High
ISOB
Supply Current Including Bias Cell
(No Load)
Power = Low
Power = High
PSRROB Supply Voltage Rejection Ratio
–
–
0.5
3
+6
–
12
–
Vdd - 1.0
mV
μV/°C
V
–
–
1
1
–
–
W
W
0.5 x Vdd + 1.1
0.5 x Vdd + 1.1
–
–
–
–
V
V
–
–
–
–
0.5 x Vdd - 1.3
0.5 x Vdd - 1.3
V
V
–
–
52
1.1
2.6
64
5.1
8.8
–
mA
mA
dB
VOSOB
TCVOSOB
VCMOB
ROUTOB
Notes
This specification applies to
the external circuit that is
being driven by the analog
output buffer.
VOUT > (Vdd - 1.25).
Table 14. 3.3V DC Analog Output Buffer Specifications
Symbol
CL
Description
Load Capacitance
Min
–
Typ
–
Max
200
VOSOB
TCVOSOB
VCMOB
ROUTOB
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
Common-Mode Input Voltage Range
Output Resistance
Power = Low
Power = High
High Output Voltage Swing
(Load = 1 kΩ to Vdd/2)
Power = Low
Power = High
Low Output Voltage Swing
(Load = 1 kΩ to Vdd/2)
Power = Low
Power = High
Supply Current Including Bias Cell
(No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio
–
–
0.5
3
+6
–
12
–
Vdd – 1.0
–
–
1
1
–
–
W
W
0.5 x Vdd + 1.0
0.5 x Vdd + 1.0
–
–
–
–
V
V
–
–
–
–
0.5 x Vdd - 1.0
0.5 x Vdd - 1.0
V
V
–
–
52
0.8
2.0
64
2.0
4.3
–
mA
mA
dB
VOHIGHOB
VOLOWOB
ISOB
PSRROB
Document Number: 001-20160 Rev. *D
Units
Notes
pF
This specification applies to
the external circuit that is
being driven by the analog
output buffer.
mV
μV/°C
V
VOUT > (Vdd - 1.25).
Page 20 of 51
[+] Feedback
CY8C24633
DC Analog Reference Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 15. 5-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
0b000
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
VAGND
AGND
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b001
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
Description
Min
Typ
Max
Units
VDD/2 + Bandgap
VDD/2 + 1.136 VDD/2 + 1.288 VDD/2 + 1.409
V
VDD/2
VDD/2 – 0.138 VDD/2 + 0.003 VDD/2 + 0.132
VDD/2 – 1.417 VDD/2 – 1.289 VDD/2 – 1.154
V
VREFLO
Ref Low
VDD/2 – Bandgap
VREFHI
Ref High
VDD/2 + Bandgap
VAGND
AGND
V
V
VDD/2
VDD/2 + 1.202 VDD/2 + 1.290 VDD/2 + 1.358
VDD/2 – 0.055 VDD/2 + 0.001 VDD/2 + 0.055
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.369 VDD/2 – 1.295 VDD/2 – 1.218
V
VREFHI
Ref High
VDD/2 + Bandgap
V
VAGND
AGND
VDD/2
VDD/2 + 1.211 VDD/2 + 1.292 VDD/2 + 1.357
VDD/2 – 0.055
VDD/2
VDD/2 + 0.052
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.368 VDD/2 – 1.298 VDD/2 – 1.224
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.215 VDD/2 + 1.292 VDD/2 + 1.353
VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.033
V
VDD/2 – 1.368 VDD/2 – 1.299 VDD/2 – 1.225
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.076
0.021
0.041
V
V
VAGND
AGND
VREFLO
Ref Low
VDD/2 – Bandgap
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.025
0.011
0.085
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.069
0.014
0.043
V
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.029
0.005
0.052
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.072
0.011
0.048
V
VDD/2
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
V
V
–
–
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.031
0.002
0.057
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.070
0.009
0.047
V
VAGND
AGND
VREFLO
Ref Low
Document Number: 001-20160 Rev. *D
P2[4]
P2[4]
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.033
0.001
0.039
–
–
V
Page 21 of 51
[+] Feedback
CY8C24633
Table 15. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b010
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b011
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b100
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
Description
VDD
Min
Typ
Max
Units
VDD – 0.121
VDD – 0.003
VDD
V
VAGND
AGND
VDD/2 – 0.040
VDD/2
VDD/2 + 0.034
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.019
V
VREFHI
Ref High
VDD
VDD – 0.083
VDD – 0.002
VDD
V
VDD/2
VAGND
AGND
VREFLO
Ref Low
VSS
VSS
VSS + 0.004
VSS + 0.016
V
VREFHI
Ref High
VDD
VDD – 0.075
VDD – 0.002
VDD
V
VDD/2
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
VDD
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
VAGND
AGND
VREFLO
VDD/2
VDD/2
VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.033
VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.032
V
V
VSS
VSS + 0.003
VSS + 0.015
V
VDD – 0.074
VDD – 0.002
VDD
V
VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.032
V
VSS
VSS + 0.002
VSS + 0.014
V
3 × Bandgap
3.753
3.874
3.979
V
2 × Bandgap
2.511
2.590
2.657
V
Ref Low
Bandgap
1.243
1.297
1.333
V
VREFHI
Ref High
3 × Bandgap
3.767
3.881
3.974
V
VAGND
AGND
2 × Bandgap
2.518
2.592
2.652
V
VREFLO
Ref Low
Bandgap
1.241
1.295
1.330
V
VREFHI
Ref High
3 × Bandgap
2.771
3.885
3.979
V
VAGND
AGND
2 × Bandgap
2.521
2.593
2.649
V
VREFLO
Ref Low
Bandgap
1.240
1.295
1.331
V
VREFHI
Ref High
3 × Bandgap
3.771
3.887
3.977
V
VAGND
AGND
2 × Bandgap
2.522
2.594
2.648
V
VREFLO
Ref Low
Bandgap
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
1.239
1.295
1.332
V
2.481 + P2[6]
2.569 + P2[6]
2.639 + P2[6]
V
VAGND
AGND
2.511
2.590
2.658
V
VREFLO
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.515 – P2[6]
2.602 – P2[6]
2.654 – P2[6]
V
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.498 + P2[6]
2.579 + P2[6]
2.642 + P2[6]
V
VAGND
AGND
2.518
2.592
2.652
V
VREFLO
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.513 – P2[6]
2.598 – P2[6]
2.650 – P2[6]
V
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.504 + P2[6]
2.583 + P2[6]
2.646 + P2[6]
V
VAGND
AGND
2.521
2.592
2.650
V
VREFLO
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.513 – P2[6]
2.596 – P2[6]
2.649 – P2[6]
V
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.505 + P2[6]
2.586 + P2[6]
2.648 + P2[6]
V
VAGND
AGND
2.521
2.594
2.648
V
VREFLO
Ref Low
2.513 – P2[6]
2.595 – P2[6]
2.648 – P2[6]
V
Document Number: 001-20160 Rev. *D
2 × Bandgap
2 × Bandgap
2 × Bandgap
2 × Bandgap
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
Page 22 of 51
[+] Feedback
CY8C24633
Table 15. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b101
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b110
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b111
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
Description
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4]
Min
Typ
Max
Units
P2[4] + 1.228
P2[4] + 1.284
P2[4] + 1.332
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.358
P2[4] – 1.293
P2[4] – 1.226
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.236
P2[4] + 1.289
P2[4] + 1.332
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.357
P2[4] – 1.297
P2[4] – 1.229
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.237
P2[4] + 1.291
P2[4] + 1.337
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.356
P2[4] – 1.299
P2[4] – 1.232
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.237
P2[4] + 1.292
P2[4] + 1.337
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.357
P2[4] – 1.300
P2[4] – 1.233
V
VREFHI
Ref High
2 × Bandgap
2.512
2.594
2.654
V
VAGND
AGND
Bandgap
1.250
1.303
1.346
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.011
VSS + 0.027
V
VREFHI
Ref High
2 × Bandgap
2.515
2.592
2.654
V
VAGND
AGND
Bandgap
1.253
1.301
1.340
V
P2[4]
P2[4]
P2[4]
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.02
V
VREFHI
Ref High
2 × Bandgap
2.518
2.593
2.651
V
VAGND
AGND
Bandgap
1.254
1.301
1.338
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.004
VSS + 0.017
V
VREFHI
Ref High
2 × Bandgap
2.517
2.594
2.650
V
VAGND
AGND
Bandgap
1.255
1.300
1.337
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.003
VSS + 0.015
V
VREFHI
Ref High
3.2 × Bandgap
4.011
4.143
4.203
V
1.6 × Bandgap
2.020
2.075
2.118
V
VSS
VSS + 0.011
VSS + 0.026
V
4.138
4.203
V
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.022
1.6 × Bandgap
2.023
2.075
2.114
VSS
VSS + 0.006
VSS + 0.017
V
4.141
4.207
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.026
1.6 × Bandgap
2.024
2.075
2.114
V
VSS
VSS + 0.004
VSS + 0.015
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.030
4.143
4.206
V
VAGND
AGND
1.6 × Bandgap
2.024
2.076
2.112
V
VREFLO
Ref Low
VSS
VSS + 0.003
VSS + 0.013
V
Document Number: 001-20160 Rev. *D
VSS
Page 23 of 51
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CY8C24633
Table 16. 3.3-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
0b000
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
VAGND
AGND
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b001
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b010
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b011
All power settings
Not allowed at 3.3 V
Description
Min
Typ
Max
Units
VDD/2 + Bandgap
VDD/2 + 1.170 VDD/2 + 1.288 VDD/2 + 1.376
V
VDD/2
VDD/2 – Bandgap
VDD/2 – 0.098 VDD/2 + 0.003 VDD/2 + 0.097
VDD/2 – 1.386 VDD/2 – 1.287 VDD/2 – 1.169
V
VDD/2 + Bandgap
VDD/2 + 1.210 VDD/2 + 1.290 VDD/2 + 1.355
V
VDD/2
V
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 0.055 VDD/2 + 0.001 VDD/2 + 0.054
VDD/2 – 1.359 VDD/2 – 1.292 VDD/2 – 1.214
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.198 VDD/2 + 1.292 VDD/2 + 1.368
V
VAGND
AGND
VDD/2
VDD/2 – 0.041
VDD/2 + 0.04
V
VDD/2
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.362 VDD/2 – 1.295 VDD/2 – 1.220
V
VREFHI
Ref High
VDD/2 + Bandgap
V
VAGND
AGND
VDD/2
VDD/2 + 1.202 VDD/2 + 1.292 VDD/2 + 1.364
VDD/2 – 0.033
VDD/2
VDD/2 + 0.030
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.364 VDD/2 – 1.297 VDD/2 – 1.222
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.072
0.017
0.041
V
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.029
0.010
0.048
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.066
0.010
0.043
V
P2[4]
P2[4]
P2[4]
P2[4]
–
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.024
0.004
0.034
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.073
0.007
0.053
V
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.028
0.002
0.033
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.073
0.006
0.056
V
P2[4]
P2[4]
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
VREFHI
Ref High
VDD
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
VDD
VAGND
AGND
P2[4]
VDD/2
VDD/2
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
–
–
P2[4]
P2[4]
P2[4]
–
P2[4] – P2[6]
– 0.030
P2[4] – P2[6]
P2[4] – P2[6] +
0.032
V
VDD – 0.102
VDD – 0.003
VDD
V
VDD/2 – 0.040 VDD/2 + 0.001 VDD/2 + 0.039
VSS
VSS + 0.005
VSS + 0.020
V
V
VDD – 0.082
VDD – 0.002
VDD
V
VDD/2 – 0.031
VDD/2
VDD/2 + 0.028
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.003
VSS + 0.015
V
VREFHI
Ref High
VDD
VDD – 0.083
VDD – 0.002
VDD
V
VAGND
AGND
VDD/2
VREFLO
Ref Low
VSS
VREFHI
Ref High
VDD
VAGND
AGND
VREFLO
Ref Low
–
–
Document Number: 001-20160 Rev. *D
VDD/2
VSS
–
VDD/2 – 0.032 VDD/2 – 0.001 VDD/2 + 0.029
VSS
VSS + 0.002
VSS + 0.014
VDD – 0.081
VDD – 0.002
VDD
VDD/2 – 0.033 VDD/2 – 0.001 VDD/2 + 0.029
VSS
VSS + 0.002
VSS + 0.013
–
–
–
V
V
V
V
V
–
Page 24 of 51
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CY8C24633
Table 16. 3.3-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
Reference Power
Settings
Symbol
Reference
Description
Typ
Max
Units
–
–
–
–
P2[4] + 1.211
P2[4] + 1.285
P2[4] + 1.348
V
P2[4]
P2[4]
P2[4]
–
0b100
All power settings
Not allowed at 3.3 V
–
–
0b101
RefPower = high
Opamp bias = high
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.354
P2[4] – 1.290
P2[4] – 1.197
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.209
P2[4] + 1.289
P2[4] + 1.353
V
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b110
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b111
All power settings
Not allowed at 3.3 V
–
Min
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4]
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.352
P2[4] – 1.294
P2[4] – 1.222
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.218
P2[4] + 1.291
P2[4] + 1.351
V
P2[4]
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.351
P2[4] – 1.296
P2[4] – 1.224
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.215
P2[4] + 1.292
P2[4] + 1.354
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.352
P2[4] – 1.297
P2[4] – 1.227
V
VREFHI
Ref High
2 × Bandgap
2.460
2.594
2.695
V
Bandgap
1.257
1.302
1.335
V
VSS
VSS + 0.01
VSS + 0.029
V
2.592
2.692
V
V
P2[4]
P2[4]
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
2 × Bandgap
2.462
Bandgap
1.256
1.301
1.332
VSS
VSS + 0.005
VSS + 0.017
V
2.593
2.682
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
2 × Bandgap
2.473
Bandgap
1.257
1.301
1.330
V
VSS
VSS + 0.003
VSS + 0.014
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
2 × Bandgap
2.470
2.594
2.685
V
VAGND
AGND
Bandgap
1.256
1.300
1.332
V
VREFLO
Ref Low
VSS
VSS + 0.002
VSS + 0.012
V
–
–
–
–
–
–
Document Number: 001-20160 Rev. *D
VSS
–
Page 25 of 51
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CY8C24633
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 17. DC Analog PSoC Block Specifications
Symbol
RCT
Description
Resistor Unit Value (Continuous Time)
Min
–
Typ
12.2
Max
–
Units
kΩ
Notes
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register.
Table 18. DC POR and LVD Specifications
Symbol
Description
VPPOR0
VPPOR1
VPPOR2
Vdd Value for PPOR Trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
Notes
Vdd must be greater than or equal
to 2.5V during startup, reset from
the XRES pin, or reset from
Watchdog.
–
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.45
2.92
3.02
3.13
4.48
4.64
4.73
4.81
2.51[7]
2.99[8]
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
V
V
Notes
7. Always greater than 50 mV above VPPOR (PORLEV=00) for falling supply.
8. Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply.
Document Number: 001-20160 Rev. *D
Page 26 of 51
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CY8C24633
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 19. DC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
This specification applies to
the functional requirements of
external programmer tools
This specification applies to
the functional requirements of
external programmer tools
This specification applies to
the functional requirements of
external programmer tools
This specification applies to
this device when it is
executing internal flash writes
VDDP
VDD for programming and erase
4.5
5
5.5
V
VDDLV
Low VDD for verify
3.0
3.1
3.2
V
VDDHV
High VDD for verify
5.1
5.2
5.3
V
VDDIWRITE
Supply voltage for flash write operation
3.0
–
5.25
V
IDDP
VILP
–
–
5
–
25
0.8
mA
V
2.1
–
–
V
–
–
0.2
mA
–
–
1.5
mA
–
–
V
Vdd - 1.0
–
Vss +
0.75
Vdd
FlashENPB
Supply Current During Programming or Verify
Input Low Voltage During Programming or
Verify
Input High Voltage During Programming or
Verify
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
Output Low Voltage During Programming or
Verify
Output High Voltage During Programming or
Verify
Flash Endurance (per block)
50,000[9]
–
–
–
FlashENT
FlashDR
Flash Endurance (total)[10]
Flash Data Retention
1,800,000
10
–
–
–
–
–
Years
VIHP
IILP
IIHP
VOLV
VOHV
Driving internal pull down
resistor.
Driving internal pull down
resistor.
V
Erase/write cycles per
block.
Erase/write cycles.
DC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 20. DC I2C Specifications[11]
Symbol
Description
VILI2C
Input low level
VIHI2C
Input high level
Min
–
–
0.7 × VDD
Typ
–
–
–
Max
0.3 × VDD
0.25 × VDD
–
Units
V
V
V
Notes
3.0 V ≤ VDD ≤ 3.6 V
4.75 V ≤ VDD ≤ 5.25 V
3.0 V ≤ VDD ≤ 5.25 V
Notes
9. The 50,000 cycle Flash endurance per block will only be guaranteed if the Flash is operating within one voltage range. Voltage ranges are 2.4V to 3.0V, 3.0V to 3.6V,
and 4.75V to 5.25V.
10. A maximum of 36 x 50,000 block endurance cycles is allowed. This can be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block
ever sees more than 50,000 cycles).
For the full industrial range, use a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash
APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
11. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs.
Document Number: 001-20160 Rev. *D
Page 27 of 51
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CY8C24633
SAR8 ADC DC Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 21. SAR8 ADC DC Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VADCVREF
Reference Voltage at Pin P3[0] When
Configured as ADC Reference
Voltage
3.0
–
5.25
V
The voltage level at P3[0] (when
configured as ADC reference voltage)
should always be maintained to be less
than chip supply voltage level on Vdd
pin. VADCVREF < Vdd.
IADCVREF
Current When P3[0] is Configured as
ADC VREF
3
–
–
mA
INL
R-2R Integral Non-Linearity[12]
-1.2
–
+1.2
LSB
The maximum LSB is over a sub-range
not exceeding 1/16 of the full-scale
range.
DNL
R-2R Differential Non-Linearity[13]
-1
–
+1
LSB
Output is monatonic.
Notes
12. At the 7F and 80 points, the maximum INL is 1.5 LSB.
13. For the 7F to 80 transition, the DNL specification is waived.
Document Number: 001-20160 Rev. *D
Page 28 of 51
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CY8C24633
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 22. 5V and 3.3V AC Chip-Level Specifications
Min
Typ
Max
Units
Notes
FIMO24
Symbol
Internal Main Oscillator Frequency for 24 MHz
Description
22.8
24
25.2[14,15,16]
MHz
Trimmed for 5V or 3.3V operation
using factory trim values. See Figure
5b on page 14. SLIMO mode = 0.
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.5
6
6.5[14,15,16]
MHz
Trimmed for 5V or 3.3V operation
using factory trim values. See Figure
5b on page 14. SLIMO mode = 1.
FCPU1
CPU Frequency (5V Nominal)
0.093
24
24.6[14,15]
MHz
SLIMO mode = 0.
FCPU2
CPU Frequency (3.3V Nominal)
0.093
12
12.3[15,16]
MHz
SLIMO mode = 0.
F48M
Digital PSoC Block Frequency
0
48
49.2[14,15,17]
MHz
Refer to the Table 27 on page 35.
F24M
Digital PSoC Block Frequency
0
24
24.6[15,17]
MHz
F32K1
Internal Low Speed Oscillator Frequency
15
32
75
kHz
F32K2
External Crystal Oscillator
–
32.768
–
kHz
F32K_U
Internal Low Speed Oscillator Untrimmed
Frequency
5
–
100
kHz
FPLL
PLL Frequency
–
23.986
–
MHz
DCILO
Internal Low Speed Oscillator Duty Cycle
20
50
80
%
TPLLSLEW
PLL Lock Time
0.5
–
10
ms
TPLLSLEWSLOW PLL Lock Time for Low Gain Setting
0.5
–
50
ms
TOS
External Crystal Oscillator Startup to 1%
–
1700
2620
ms
TOSACC
External Crystal Oscillator Startup to 100 ppm
–
2800
3800
ms
μs
TXRST
External Reset Pulse Width
10
–
–
DC24M
24 MHz Duty Cycle
40
50
60
%
Step24M
24 MHz Trim Step Size
–
50
–
kHz
Fout48M
48 MHz Output Frequency
46.8
48.0
49.2[14,16]
MHz
FMAX
Maximum frequency of signal on row input or row
output.
–
–
12.3
MHz
TRAMP
Supply Ramp Time
NA
–
–
μs
SRPOWER_UP
Power Supply Slew Rate
–
–
250
V/ms
TPOWERUP
Time from End of POR to CPU Executing Code
–
16
100
ms
tjit_IMO [18]
24 MHz IMO cycle-to-cycle jitter (RMS)
–
200
700
ps
24 MHz IMO long term N cycle-to-cycle jitter
(RMS)
–
300
900
ps
24 MHz IMO period jitter (RMS)
–
100
400
ps
24 MHz IMO cycle-to-cycle jitter (RMS)
–
200
800
ps
24 MHz IMO long term N cycle-to-cycle jitter
(RMS)
–
300
1200
ps
24 MHz IMO period jitter (RMS)
–
100
700
ps
tjit_PLL [18]
Accuracy is capacitor and crystal
dependent. 50% duty cycle.
Is a multiple (x732) of crystal
frequency.
The crystal oscillator frequency is
within 100 ppm of its final value by the
end of the Tosacc period. Correct
operation assumes a properly loaded
1 uW maximum drive level 32.768
kHz crystal. 3.0V ≤ Vdd ≤ 5.5V, -40 oC
≤ TA ≤ 85 oC.
Trimmed. Utilizing factory trim
values.
N = 32
N = 32
Notes
14. 4.75V < Vdd < 5.25V.
15. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
16. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
17. See the individual user module data sheets for information on maximum frequencies for user modules.
18. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-20160 Rev. *D
Page 29 of 51
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CY8C24633
Figure 6. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 7. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 8. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Document Number: 001-20160 Rev. *D
Page 30 of 51
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AC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 23. 5V and 3.3V AC GPIO Specifications
Symbol
FGPIO
TRiseF
TFallF
TRiseS
TFallS
Description
GPIO Operating Frequency
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12
18
18
–
–
Units
MHz
ns
ns
ns
ns
Notes
Normal Strong Mode
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Figure 9. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
Document Number: 001-20160 Rev. *D
TFallF
TFallS
Page 31 of 51
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CY8C24633
AC Operational Amplifier Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 24. 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
Description
Rising Settling Time from 80% of ΔV to 0.1% of
ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1%
of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Document Number: 001-20160 Rev. *D
Min
Typ
Max
Units
–
–
–
–
–
–
3.9
0.72
0.62
μs
μs
μs
–
–
–
–
–
–
5.9
0.92
0.72
μs
μs
μs
0.15
1.7
6.5
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.01
0.5
4.0
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.75
3.1
5.4
–
–
–
–
–
–
MHz
MHz
MHz
Notes
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Table 25. 3.3-V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOA
Input offset voltage (absolute value)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
–
–
–
1.65
1.32
–
10
8
–
mV
mV
mV
Notes
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
TCVOSOA
Average input offset voltage drift
–
7.0
35.0
µV/°C
IEBOA
Input leakage current (port 0 analog pins)
–
20
–
pA
Gross tested to 1 μA
CINOA
Input capacitance (port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 °C
VCMOA
Common mode voltage range
0.2
–
VDD – 0.2
V
The common-mode input voltage
range is measured through an
analog output buffer. The
specification includes the limitations
imposed by the characteristics of the
analog output buffer.
GOLOA
Open loop gain
Power = low, ppamp Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
60
60
80
–
–
–
–
–
–
dB
dB
dB
VOHIGHOA
High output voltage swing (internal signals)
Power = low, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
VDD – 0.2
VDD – 0.2
VDD – 0.2
–
–
–
–
–
–
V
V
V
VOLOWOA
Low output voltage swing (internal signals)
Power = low, ppamp Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
ISOA
Supply current (including associated AGND
buffer)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = medium, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
–
–
–
–
–
–
150
300
600
1200
2400
–
200
400
800
1600
3200
–
μA
μA
μA
μA
μA
μA
Supply voltage rejection ratio
64
80
–
dB
PSRROA
Document Number: 001-20160 Rev. *D
Specification is applicable at low
Opamp bias. For high Opamp bias
mode (except high power, high
Opamp bias), minimum is 60 dB.
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
VSS ≤ VIN ≤ (VDD – 2.25) or
(VDD – 1.25 V) ≤ VIN ≤ VDD
Page 33 of 51
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CY8C24633
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 10. Typical AGND Noise with P2[4] Bypass
nV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 11. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 001-20160 Rev. *D
0.01
0.1
Freq (kHz)
1
10
100
Page 34 of 51
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AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 26. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
μs
Notes
≥ 50 mV overdrive comparator
reference set within VREFLPC.
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 27. 5-V and 3.3-V AC Digital Block Specifications
Function
All functions
Timer
Counter
Dead Band
CRCPRS
(PRS
Mode)
CRCPRS
(CRC
Mode)
SPIM
SPIS
Description
Block input clock frequency
VDD ≥ 4.75 V
VDD < 4.75 V
Input clock frequency
No capture, VDD ≥ 4.75 V
No capture, VDD < 4.75 V
With capture
Capture pulse width
Input clock frequency
No enable input, VDD ≥ 4.75 V
No enable input, VDD < 4.75 V
With enable input
Enable input pulse width
Kill pulse width
Asynchronous restart mode
Synchronous restart mode
Disable mode
Input clock frequency
VDD ≥ 4.75 V
VDD < 4.75 V
Input clock frequency
VDD ≥ 4.75 V
VDD < 4.75 V
Input clock frequency
Input clock frequency
Input clock (SCLK) frequency
Width of SS_negated between
transmissions
Min
Typ
Max
Unit
–
–
–
–
49.2
24.6
MHz
MHz
–
–
–
50[19]
–
–
–
–
49.2
24.6
24.6
–
MHz
MHz
MHz
ns
–
–
–
50[19]
–
–
–
–
49.2
24.6
24.6
–
MHz
MHz
MHz
ns
20
50[19]
50[19]
–
–
–
–
–
–
ns
ns
ns
–
–
–
–
49.2
24.6
MHz
MHz
–
–
–
–
–
–
49.2
24.6
24.6
MHz
MHz
MHz
–
–
8.2
MHz
–
50[19]
–
–
4.1
–
MHz
ns
Notes
The SPI serial clock (SCLK) frequency is equal to
the input clock frequency divided by 2.
The input clock is the SPI SCLK in SPIS mode.
Note
19. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-20160 Rev. *D
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Table 27. 5-V and 3.3-V AC Digital Block Specifications (continued)
Function
Transmitter
Receiver
Description
Input clock frequency
VDD ≥ 4.75 V, 2 stop bits
VDD ≥ 4.75 V, 1 stop bit
VDD < 4.75 V
Input clock frequency
VDD ≥ 4.75 V, 2 stop bits
VDD ≥ 4.75 V, 1 stop bit
VDD < 4.75 V
Min
Typ
Max
Unit
–
–
–
–
–
–
49.2
24.6
24.6
MHz
MHz
MHz
Notes
The baud rate is equal to the input clock frequency
divided by 8.
The baud rate is equal to the input clock frequency
divided by 8.
–
–
–
–
–
–
49.2
24.6
24.6
MHz
MHz
MHz
AC Analog Output Buffer Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 28. 5V AC Analog Output Buffer Specifications
Symbol
Description
TROB
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
TSOB
Falling Settling Time to 0.1%, 1V Step, 100 pF
Load
Power = Low
Power = High
SRROB Rising Slew Rate (20% to 80%), 1V Step, 100 pF
Load
Power = Low
Power = High
SRFOB
Falling Slew Rate (80% to 20%), 1V Step, 100 pF
Load
Power = Low
Power = High
BWOB
Small Signal Bandwidth, 20 mVpp, 3dB BW, 100
pF Load
Power = Low
Power = High
BWOB
Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF
Load
Power = Low
Power = High
Document Number: 001-20160 Rev. *D
Min
Typ
Max
Units
–
–
–
–
2.5
2.5
μs
μs
–
–
–
–
2.2
2.2
μs
μs
0.65
0.65
–
–
–
–
V/μs
V/μs
0.65
0.65
–
–
–
–
V/μs
V/μs
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Notes
Page 36 of 51
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Table 29. 3.3V AC Analog Output Buffer Specifications
Symbol
Description
TROB
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
TSOB
Falling Settling Time to 0.1%, 1V Step, 100 pF
Load
Power = Low
Power = High
SRROB Rising Slew Rate (20% to 80%), 1V Step, 100 pF
Load
Power = Low
Power = High
SRFOB
Falling Slew Rate (80% to 20%), 1V Step, 100 pF
Load
Power = Low
Power = High
BWOB
Small Signal Bandwidth, 20 mVpp, 3dB BW, 100 pF
Load
Power = Low
Power = High
BWOB
Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF
Load
Power = Low
Power = High
Min
Typ
Max
Units
–
–
–
–
3.8
3.8
μs
μs
–
–
–
–
2.6
2.6
μs
μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.7
0.7
–
–
–
–
MHz
MHz
200
200
–
–
–
–
kHz
kHz
Notes
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 30. 5V AC External Clock Specifications
Symbol
FOSCEXT
Min
Typ
Max
Units
Frequency
Description
0.093
–
24.6
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Notes
Table 31. 3.3V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency with CPU Clock Divide by 1
[20]
0.093
–
12.3
MHz
FOSCEXT
Frequency with CPU Clock Divide by 2 or
Greater[21]
0.186
–
24.6
MHz
–
High Period with CPU Clock Divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock Divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Document Number: 001-20160 Rev. *D
Notes
Page 37 of 51
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AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 32. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
TDSCLK
TDSCLK3
TERASEALL
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Flash Erase Time (Bulk)
Min
1
1
40
40
0
–
–
–
–
–
Typ
–
–
–
–
–
20
80
–
–
20
Max
20
20
–
–
8
–
–
45
50
–
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
ms
TPROGRAM_HOT
TPROGRAM_COLD
Flash Block Erase + Flash Block Write Time
Flash Block Erase + Flash Block Write Time
–
–
–
–
200
400
ms
ms
Notes
Vdd > 3.6
3.0 ≤ Vdd ≤ 3.6
Erase all blocks and
protection fields at once.
0°C ≤ TJ ≤ 100°C
-40°C ≤ TJ ≤ 0°C
SAR8 ADC AC Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 33. SAR8 ADC AC Specifications
Min
Typ
Max
Units
Freq3
Symbol
Input clock frequency 3V
Description
–
–
3.0
MHz
Freq5
Input clock frequency 5V
–
–
3.0
MHz
Notes
Notes
20. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle
requirements.
21. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the
fifty percent duty cycle requirement is met.
Document Number: 001-20160 Rev. *D
Page 38 of 51
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AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 34. AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V
Symbol
Description
FSCLI2C
THDSTAI2C
SCL Clock Frequency
Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Set-up Time for a Repeated START Condition
Data Hold Time
Data Set-up Time
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START
Condition
Pulse Width of spikes are suppressed by the input
filter.
TLOWI2C
THIGHI2C
TSUSTAI2C
THDDATI2C
TSUDATI2C
TSUSTOI2C
TBUFI2C
TSPI2C
Standard-Mode
Min
Max
0
100
4.0
–
Fast-Mode
Min
Max
0
400
0.6
–
Units
Notes
kHz
μs
4.7
4.0
4.7
0
250
4.0
4.7
–
–
–
–
–
–
–
1.3
0.6
0.6
0
100[22]
0.6
1.3
–
–
–
–
–
–
–
μs
μs
μs
μs
ns
μs
μs
–
–
0
50
ns
Table 35. AC Characteristics of the I2C SDA and SCL Pins for Vdd < 3.0V (Fast-Mode Not Supported)
Symbol
Description
FSCLI2C
THDSTAI2C
SCL Clock Frequency
Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Set-up Time for a Repeated START Condition
Data Hold Time
Data Set-up Time
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START
Condition
Pulse Width of spikes are suppressed by the input
filter.
TLOWI2C
THIGHI2C
TSUSTAI2C
THDDATI2C
TSUDATI2C
TSUSTOI2C
TBUFI2C
TSPI2C
Standard-Mode
Min
Max
0
100
4.0
–
Fast-Mode
Min
Max
–
–
–
–
Units
Notes
kHz
μs
4.7
4.0
4.7
0
250
4.0
4.7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
μs
μs
μs
μs
ns
μs
μs
–
–
–
–
ns
Figure 12. Definition for Timing for Fast-/Standard-Mode on the I2C Bus
I2C_SDA
TSUDATI2C
THDSTAI2C
TSPI2C
THDDATI2CTSUSTAI2C
TBUFI2C
I2C_SCL
THIGHI2C TLOWI2C
S
START Condition
TSUSTOI2C
Sr
Repeated START Condition
P
S
STOP Condition
Note
22. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement TSUDATI2C ≥ 250 ns must then be met. This is automatically
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line trmax + TSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-20160 Rev. *D
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CY8C24633
Thermal Impedances
Table 36. Thermal Impedances by Package
Typical θJA [23]
95 oC/W
67 oC/W
Package
28 SSOP
56 SSOP
Capacitance on Crystal Pins
Table 37. Typical Package Capacitance on Crystal Pins
Package
Package Capacitance
28 SSOP
2.8 pF
56 SSOP
Pin 27 0.33 pF
Pin 31 0.35 pF
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 38. Solder Reflow Peak Temperature
Package
28 SSOP
56 SSOP
Maximum Peak Temperature
260 °C
260 °C
Document Number: 001-20160 Rev. *D
Time at Maximum Peak Temperature
20 s
20 s
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CY8C24633
Ordering Information
The following table lists the CY8C24633 PSoC device family key package features and ordering codes.
Digital I/O Pins
Analog Inputs
Analog Outputs
XRES Pin
8
8
256 –40 °C to +85 °C
256 –40 °C to +85 °C
4
4
4
4
25
25
12
12
2
2
Yes
Yes
CY8C24033-24PVXI[24]
8
256 –40 °C to +85 °C
4
4
24
12
2
Yes
Temperature
Range
CY8C24633-24PVXI
CY8C24633-24PVXIT
RAM
(Bytes)
Analog Blocks
(Columns of 3)
28-Pin (210 Mil) SSOP
28-Pin (210 Mil) SSOP
(Tape and Reel)
56-Pin OCD SSOP
Ordering Code
Flash
(Kbytes)
Package
Digital Blocks
(Rows of 4)
Table 39. CY8C24x33 PSoC Device Family Key Features and Ordering Information
Ordering Code Definitions
CY 8 C 24 XXX- SP XX
Package Type:
PX = PDIP Pb-free
SX = SOIC Pb-free
PVX = SSOP Pb-free
LFX/LKX/LQX/LTX = QFN Pb-free
AX = TQFP Pb-free
BVX = VFBGA Pb-free
Speed: 24 MHz
Thermal Rating:
C = Commercial
I = Industrial
E = Extended
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
Notes
23. TJ = TA + POWER x θJA.
24. This part may be used for in-circuit debugging. It is NOT available for production.
Document Number: 001-20160 Rev. *D
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CY8C24633
Packaging Information
This section illustrates the packaging specifications for the CY8C24633 PSoC device, along with the thermal impedances for each
package, solder reflow peak temperature, and the typical package capacitance on crystal pins.
Figure 13. 28-Pin (210-Mil) SSOP
51-85079 *D
Figure 14. 56-Pin (300-Mil) SSOP
32
51-85062 *D
Document Number: 001-20160 Rev. *D
Page 42 of 51
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CY8C24633
Acronyms
Acronyms Used
Table 40 lists the acronyms that are used in this document.
Table 40. Acronyms Used in this Datasheet
Acronym
AC
ADC
Description
Acronym
Description
alternating current
MIPS
million instructions per second
analog-to-digital converter
OCD
on-chip debug
printed circuit board
API
application programming interface
PCB
CPU
central processing unit
PGA
programmable gain amplifier
CRC
cyclic redundancy check
PLL
phase-locked loop
CT
DAC
continuous time
digital-to-analog converter
DC
direct current
DNL
differential nonlinearity
POR
PPOR
PRS
PSoC®
pseudo-random sequence
Programmable System-on-Chip
DTMF
dual-tone multi-frequency
ECO
external crystal oscillator
RTC
real time clock
electrically erasable programmable read-only
memory
SAR
successive approximation
EEPROM
GPIO
general purpose I/O
ICE
in-circuit emulator
IDE
integrated development environment
PWM
power on reset
precision power on reset
SC
SLIMO
pulse width modulator
switched capacitor
slow IMO
SMP
switch mode pump
ILO
internal low speed oscillator
SOIC
small-outline integrated circuit
IMO
internal main oscillator
SPITM
serial peripheral interface
INL
integral nonlinearity
SRAM
static random access memory
I/O
input/output
SROM
supervisory read only memory
infrared data association
SSOP
shrink small-outline package
ISSP
in-system serial programming
UART
LPC
low power comparator
USB
universal serial bus
LVD
low voltage detect
WDT
watchdog timer
MAC
multiply-accumulate
XRES
external reset
MCU
microcontroller unit
IrDA
universal asynchronous reciever / transmitter
Reference Documents
PSoC® CY8C24633 Technical Reference Manual (TRM) (001-29639)
Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459)
Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 (001-17397)
Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503)
Document Number: 001-20160 Rev. *D
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CY8C24633
Document Conventions
Units of Measure
Table 41 lists the unit sof measures.
Table 41. Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
kB
1024 bytes
ms
millisecond
dB
decibels
ns
nanosecond
picosecond
°C
degree Celsius
ps
pF
picofarad
µV
microvolts
kHz
kilohertz
mV
millivolts
MHz
megahertz
nV
nanovolts
LSB
least significant bit
V
volts
kΩ
kilohm
µW
microwatts
µA
microampere
W
watt
mA
milliampere
mm
nA
nanoampere
mVpp
pA
pikoampere
ppm
µs
microsecond
%
millimeter
millivolts peak-to-peak
parts per million
percent
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.
Document Number: 001-20160 Rev. *D
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CY8C24633
Glossary
active high
5. A logic signal having its asserted state as the logic 1 state.
6. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous
time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain
stages, and much more.
analog-to-digital
(ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically,
an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs
the reverse operation.
API (Application
Programming
Interface)
A series of software routines that comprise an interface between a computer application and
lower level services and functions (for example, user modules and libraries). APIs serve as
building blocks for programmers that create software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
Bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with
the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally)
reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or
loss); it is sometimes represented more specifically as, for example, full width at half maximum.
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a
reference level to operate the device.
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital
PSoC block or an analog PSoC block.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring
data from one device to another. Usually refers to an area reserved for IO operations, into
which data is read, or from which data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as
it is received from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets
with similar routing patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented
using vector notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is
sometimes used to synchronize different logic blocks.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously
satisfy predetermined amplitude requirements.
Document Number: 001-20160 Rev. *D
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Glossary
(continued)
compiler
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register,
is set to ‘1’.
crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric
crystal is less sensitive to ambient temperature than other circuit components.
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear
check (CRC)
feedback shift register. Similar calculations may be used for a variety of other purposes such as
data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location
to the central processing unit and vice versa. More generally, a set of signals used to convey
data between digital functions.
debugger
A hardware and software system that allows the user to analyze the operation of the system
under development. A debugger usually allows the developer to step through the firmware one
step at a time, set break points, and analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC
generator, pseudo-random number generator, or SPI.
digital-to-analog
(DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analogto-digital (ADC) converter performs the reverse operation.
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
emulator
Duplicates (provides an emulation of) the functions of one system with a different system, so that
the second system appears to behave like the first system.
external reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and
blocks to stop and return to a pre-defined state.
flash
An electrically programmable and erasable, non-volatile technology that provides users with the
programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means
that the data is retained when power is off.
Flash block
The smallest amount of Flash ROM space that may be programmed at one time and the smallest
amount of Flash space that may be protected. A Flash block holds 64 bytes.
frequency
The number of cycles or events per unit of time, for a periodic function.
gain
The ratio of output current, voltage, or power to input current, voltage, or power, respectively.
Gain is usually expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an
Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The
original system was created in the early 1980s as a battery control interface, but it was later used
as a simple internal bus system for building control electronics. I2C uses only two bi-directional
pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100
kbits/second in standard mode and 400 kbits/second in fast mode.
Document Number: 001-20160 Rev. *D
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Glossary
(continued)
ICE
The in-circuit emulator that allows users to test the project in a hardware environment, while
viewing the debugging device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event
external to that process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the M8C receives a hardware
interrupt. Many interrupt sources may each exist with its own priority and individual ISR code
block. Each ISR code block ends with the RETI instruction, returning the device to the point in
the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a
(LVD)
selected threshold.
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside
a PSoC by interfacing to the Flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are
cascaded in width, the master device is the one that controls the timing for data exchanges
between the cascaded devices and an external interface. The controlled device is called the
slave device.
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition
to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason
for this is to permit the realization of a controller with a minimal quantity of chips, thus
achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of
the controller. The microcontroller is normally not used for general-purpose computation as is a
microprocessor.
mixed-signal
The reference to a circuit containing both analog and digital techniques and components.
modulator
A device that imposes a signal on a carrier.
noise
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
A circuit that may be crystal controlled and is used to generate a clock frequency.
parity
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the
sum of all the digits of the binary data either always even (even parity) or always odd (odd parity).
phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative
to a reference signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC
device and their physical counterparts in the printed circuit board (PCB) package. Pinouts
involve pin numbers as a link between schematic and PCB design (both being computer generated
files) and may also involve pin names.
Document Number: 001-20160 Rev. *D
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Glossary
(continued)
port
A group of pins, usually eight.
power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is
one type of hardware reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-onChip™ is a trademark of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied measurand
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out
and new data can be written in.
register
A storage device with a specific capacity, such as a bit or byte.
reset
A means of bringing a system back to a know state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but
new data cannot be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one
value to another.
shift register
A memory storage device that sequentially shifts a word either left or right to output a stream of
serial data.
slave device
A device that allows another device to control the timing for data exchanges between two
devices. Or when devices are cascaded in width, the slave device is the one that allows another
device to control the timing of data exchanges between the cascaded devices and an external
interface. The controlling device is called the master device.
SRAM
An acronym for static random access memory. A memory device allowing users to store and
retrieve data at a high rate of speed. The term static is used because, after a value has been
loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is
removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the
device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be
accessed in normal user code, operating from Flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next
character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
Document Number: 001-20160 Rev. *D
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Glossary
(continued)
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does
not drive any value in the Z state and, in many respects, may be considered to be disconnected
from the rest of the circuit, allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data
and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and
configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high
level API (Application Programming Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified
during normal program execution and not just during initialization. Registers in bank 1 are most
likely to be modified only during the initialization phase of the program.
VDD
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually
5 V or 3.3 V.
VSS
A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified
period of time.
Document Number: 001-20160 Rev. *D
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CY8C24633
Document History Page
Document Title: CY8C24633 PSoC® Programmable-System-on-Chip
Document Number: 001-20160
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
1411003
HMT
See ECN
New spec. Separate device from 001-14643.
*A
1648723
HMT
See ECN
Update SAR ADC electrical specs. Update INL, DNL, and VOL specs. Finetune
specs. Add 56 SSOP package capacitance data. Change title. Make data sheet Final.
*B
2763970 POA/AESA 09/16/2009 Update Getting Started, Development Tools, and Designing with PSoC Designer
sections.
*C
2871212
JHU/HMT
02/04/2010
■
■
■
■
*D
3115813
NJF
12/20/10
Document Number: 001-20160 Rev. *D
Add Table of Contents.
Update DC GPIO, AC Chip-Level, and AC Programming Specifications as follows:
❐ Add IOH, IOL. Existing parameter. Previously only in “Notes” section of VOH/VOL.
Now added as a separate line item for ease of location in data sheet.
❐ Add Flash Endurance Note regarding the programming and verifying Flash should
be in the same voltage range. Added to clarify Flash behavior for the customer.
❐ Add F32K_U to clarify minimum ILO frequency out before the part boots up.
❐ Add DCILO upon request from a few customers.
❐ Add TPOWERUP, typical amount of time taken by PSoC to begin executing code
out of Flash after powerup. Added to clarify PSoC behavior at startup for customer.
❐ Revise FIMO6 limits. No impact to form, fit, function, or customer application.
❐ Revise TRAMP from 0 to NA. Replace TRAMP (time) with SRPOWER_UP to
accurately define the powerup requirement.
❐ Add SRPOWER_UP, change from no limitation to limitations based on test equipment ratings, to which the part will now be tested.
❐ Add TPROGRAM_HOT of maximum time it takes to erase and program a block
when die temperature is >0°C. Added to clarify Flash behavior to the customer.
❐ Add TPROGRAM_COLD of maximum time it takes to erase and program a block
over the full temperature range (–40°C to 85°C). Added to clarify Flash behavior
to the customer.
❐ Revise TWRITE to align with recommended values for third party programmers.
Data sheet now matches the typical value as recommended.
Update copyright and Sales, Solutions, and Legal Information URLs.
Update 28-Pin SSOP package diagram.
Updated PSoC Device Characteristics table .
Added DC I2C Specifications table.
Added Tjit_IMO specification, removed existing jitter specifications.
Updated DC Analog Reference Specifications and 3.3 V DC operational amplifier
specifications tables.
Updated Units of Measure, Acronyms, Glossary, and References sections.
Updated solder reflow specifications.
No specific changes were made to AC Digital Block Specifications table and I2C
Timing Diagram. They were updated for clearer understanding.
Updated Figure 10 since the labelling for y-axis was incorrect.
Added ordering code definitions.
Page 50 of 51
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CY8C24633
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/automotive
PSoC® Solutions
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007-2009, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products
for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-20160 Rev. *D
Revised December 20, 2010
Page 51 of 51
PSoC Designer™ is a trademark and PSoC® is a registered trademark of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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