CY7C1339G 4-Mbit (128 K × 32) Pipelined Sync SRAM 4-Mbit (128 K × 32) Pipelined Sync SRAM Features Functional Description ■ Registered inputs and outputs for pipelined operation The CY7C1339G SRAM integrates 128 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BW[A:D], and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. ■ 128 K × 32 common I/O architecture ■ 3.3 V core power supply (VDD) ■ 2.5 V/3.3 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 4.0 ns (for 133-MHz device) ■ Provide high-performance 3-1-1-1 access rate ■ User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed writes ■ Asynchronous output enable ■ Available in Pb-free 100-pin TQFP package ■ “ZZ” sleep mode option Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle.This part supports byte write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1339G operates from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Logic Block Diagram A 0, A 1, A A DDRESS REGISTER 2 A [1:0] M ODE A DV CLK Q1 BURST COUNTER CLR A ND Q0 LOGIC A DSC A DSP BW D DQ D BYTE W RITE REGISTER DQ D BYTE W RITE DRIVER BW C DQ C BYTE W RITE REGISTER DQ C BYTE W RITE DRIVER DQ B BYTE W RITE REGISTER DQ B BYTE W RITE DRIVER BW B GW CE 1 CE 2 CE 3 OE ZZ ENA BLE REGISTER SENSE A M PS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQ A BYTE W RITE DRIVER DQ A BYTE W RITE REGISTER BW A BW E M EM ORY A RRA Y INPUT REGISTERS PIPELINED ENABLE SLEEP CONTROL Errata: For information on silicon errata, see "Errata" on page 19. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation Document Number: 38-05520 Rev. *N • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 25, 2013 CY7C1339G Contents Selection Guide ................................................................ 3 Pin Configurations ........................................................... 3 Pin Definitions .................................................................. 4 Functional Overview ........................................................ 5 Single Read Accesses ................................................ 5 Single Write Accesses Initiated by ADSP ................... 5 Single Write Accesses Initiated by ADSC ................... 5 Burst Sequences ......................................................... 6 Sleep Mode ................................................................. 6 Interleaved Burst Address Table ................................. 6 Linear Burst Address Table ......................................... 6 ZZ Mode Electrical Characteristics .............................. 6 Truth Table ........................................................................ 7 Partial Truth Table for Read/Write .................................. 8 Maximum Ratings ............................................................. 9 Operating Range ............................................................... 9 Electrical Characteristics ................................................. 9 Capacitance .................................................................... 10 Thermal Resistance ........................................................ 10 AC Test Loads and Waveforms ..................................... 10 Document Number: 38-05520 Rev. *N Switching Characteristics .............................................. 11 Switching Waveforms .................................................... 12 Ordering Information ...................................................... 16 Ordering Code Definitions ......................................... 16 Package Diagrams .......................................................... 17 Acronyms ........................................................................ 18 Document Conventions ................................................. 18 Units of Measure ....................................................... 18 Errata ............................................................................... 19 Part Numbers Affected .............................................. 19 Product Status ........................................................... 19 Ram9 Sync/NoBL ZZ Pin Issues Errata Summary .... 19 Document History Page ................................................. 20 Sales, Solutions, and Legal Information ...................... 22 Worldwide Sales and Design Support ....................... 22 Products .................................................................... 22 PSoC® Solutions ...................................................... 22 Cypress Developer Community ................................. 22 Technical Support ..................................................... 22 Page 2 of 22 CY7C1339G Selection Guide 133 MHz Unit Maximum access time Description 4.0 ns Maximum operating current 225 mA Maximum CMOS standby current 40 mA Pin Configurations BYTE C NC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1339G 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA NC BYTE B BYTE A MODE A A A A A1 A0 NC/72M NC/36M VSS VDD NC/18M NC/9M A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 BYTE D 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout[1] Note 1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 19. Document Number: 38-05520 Rev. *N Page 3 of 22 CY7C1339G Pin Definitions Name A0, A1, A I/O Description InputAddress inputs used to select one of the 128 K address locations. Sampled at the rising edge of synchronous the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the two-bit counter. InputByte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled BWA, BWB, BWC, BWD synchronous on the rising edge of CLK. GW InputGlobal write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write synchronous is conducted (all bytes are written, regardless of the values on BW[A:D] and BWE). BWE InputByte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted synchronous LOW to conduct a byte write. CLK CE1 CE2 CE3 Inputclock Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 synchronous and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE2 to select/deselect the device. CE3 is sampled only when a new external address is loaded. OE InputOutput enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputAdvance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it synchronous automatically increments the address in a burst cycle. ADSP InputAddress strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputAddress strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ[2] InputZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a tri-state condition. VDD Power supply Power supply inputs to the core of the device. VSS Ground Ground for the core of the device. VDDQ I/O power supply Power supply for the I/O circuitry. VSSQ I/O ground Ground for the I/O circuitry. MODE Inputstatic Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode pin has an internal pull-up. Note 2. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 19. Document Number: 38-05520 Rev. *N Page 4 of 22 CY7C1339G Pin Definitions (continued) Name NC, NC/9M, NC/18M, NC/72M, NC/144M, NC/288M, NC/576M, NC/1G I/O Description – No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M, NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the die. Functional Overview Single Write Accesses Initiated by ADSP All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 4.0 ns (133-MHz device). This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The Write signals (GW, BWE, and BW[A:D]) and ADV inputs are ignored during this first cycle. The CY7C1339G supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the byte write enable (BWE) and byte write select (BW[A:D]) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous chip selects (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the write signals (GW, BWE) are all deserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the address register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the output registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately. Document Number: 38-05520 Rev. *N ADSP-triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the write operation is controlled by BWE and BW[A:D] signals. The CY7C1339G provides byte write capability that is described in the Write Cycle Descriptions table. Asserting the byte write enable input (BWE) with the selected byte write (BW[A:D]) input, will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1339G is a common I/O device, the output enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BW[A:D]) are asserted active to conduct a write to the desired byte(s). ADSC-triggered write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQs is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1339G is a common I/O device, the output enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Page 5 of 22 CY7C1339G Burst Sequences The CY7C1339G provides a two-bit wraparound counter, fed by A1:A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Interleaved Burst Address Table (MODE = Floating or VDD) Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported. First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Linear Burst Address Table (MODE = GND) First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions IDDZZ Snooze mode standby current ZZ > VDD– 0.2 V tZZS Device operation to ZZ ZZ > VDD – 0.2 V tZZREC ZZ recovery time ZZ < 0.2 V tZZI ZZ active to snooze current tRZZI Min Max Unit – 40 mA – 2tCYC ns 2tCYC – ns This parameter is sampled – 2tCYC ns ZZ Inactive to exit snooze current This parameter is sampled 0 – ns Document Number: 38-05520 Rev. *N Page 6 of 22 CY7C1339G Truth Table The truth table for CY7C1339G follows. [3, 4, 5, 6, 7, 8] Operation Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect cycle, power-down None H X X L X L X X X L–H Tri-state Deselect cycle, power-down None L L X L L X X X X L–H Tri-state Deselect cycle, power-down None L X H L L X X X X L–H Tri-state Deselect cycle, power-down None L L X L H L X X X L–H Tri-state Deselect cycle, power-down None L X H L H L X X X L–H Tri-state Snooze mode, power-down None X X X H X X X X X X Tri-state External L H L L L X X X L L–H Q READ cycle, begin burst READ cycle, begin burst External L H L L L X X X H L–H Tri-state WRITE cycle, begin burst External L H L L H L X L X L–H D READ cycle, begin burst External L H L L H L X H L L–H Q READ cycle, begin burst External L H L L H L X H H L–H Tri-state READ cycle, continue burst Next X X X L H H L H L L–H READ cycle, continue burst Next X X X L H H L H H L–H Tri-state READ cycle, continue burst Next H X X L X H L H L L–H READ cycle, continue burst Next H X X L X H L H H L–H Tri-state WRITE cycle, continue burst Next X X X L H H L L X L–H D WRITE cycle, continue burst Next H X X L X H L L X L–H D READ cycle, suspend burst Current X X X L H H H H L L–H Q READ cycle, suspend burst Current X X X L H H H H H L–H Tri-state READ cycle, suspend burst Current H X X L X H H H L L–H READ cycle, suspend burst Current H X X L X H H H H L–H Tri-state WRITE cycle, suspend burst Current X X X L H H H L X L–H D WRITE cycle, suspend burst Current H X X L X H H L X L–H D Q Q Q Notes 3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 4. WRITE = L when any one or more byte write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all byte write enable signals (BWA, BWB, BWC, BWD), BWE, GW = H. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CE1, CE2, and CE3 are available only in the TQFP package. 7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 38-05520 Rev. *N Page 7 of 22 CY7C1339G Partial Truth Table for Read/Write The partial truth table for Read/Write for CY7C1339G follows. [9, 10] GW BWE BWD BWC BWB BWA Read Function H H X X X X Read H L H H H H Write byte A – DQA H L H H H L Write byte B – DQB H L H H L H Write bytes B, A H L H H L L Write byte C– DQC H L H L H H Write bytes C, A H L H L H L Write bytes C, B H L H L L H Write bytes C, B, A H L H L L L Write byte D– DQD H L L H H H Write bytes D, A H L L H H L Write bytes D, B H L L H L H Write bytes D, B, A H L L H L L Write bytes D, C H L L L H H Write bytes D, C, A H L L L H L Write bytes D, C, B H L L L L H Write all bytes H L L L L L Write all bytes L X X X X X Notes 9. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 10. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active. Document Number: 38-05520 Rev. *N Page 8 of 22 CY7C1339G Maximum Ratings DC input voltage ................................. –0.5 V to VDD + 0.5 V Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied .......................................... –55 °C to +125 °C Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD DC voltage applied to outputs in tri-state ..........................................–0.5 V to VDDQ + 0.5 V Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (per MIL-STD-883, method 3015) ......................... > 2001 V Latch-up current ................................................... > 200 mA Operating Range Range Ambient Temperature Commercial 0 °C to +70 °C VDD VDDQ 3.3 V– 5% / 2.5 V – 5% to + 10% VDD Electrical Characteristics Over the Operating Range Parameter [11, 12] Description VDD Power supply voltage VDDQ I/O supply voltage VOH Output HIGH voltage VOL VIH VIL IX IOZ IDD Test Conditions for 3.3 V I/O, IOH = –4.0 mA for 2.5 V I/O, IOH = –1.0 mA Output LOW voltage for 3.3 V I/O, IOL = 8.0 mA for 2.5 V I/O, IOL = 1.0 mA Input HIGH voltage [11.] for 3.3 V I/O for 2.5 V I/O Input LOW voltage [11.] for 3.3 V I/O for 2.5 V I/O Input leakage current except ZZ GND VI VDDQ and MODE Input current of MODE Input = VSS Input = VDD Input current of ZZ Input = VSS Input = VDD Output leakage current GND VI VDDQ, output disabled VDD operating supply current VDD = Max, IOUT = 0 mA, 7.5-ns cycle, f = fMAX = 1/tCYC 133 MHz Min 3.135 2.375 2.4 2.0 – – 2.0 1.7 –0.3 –0.3 –5 Max Unit 3.6 V VDD V – V – V 0.4 V 0.4 V VDD + 0.3 V V VDD + 0.3 V V 0.8 V 0.7 V 5 A –30 – –5 – –5 – – 5 – 30 5 225 A A A A A mA 7.5-ns cycle, 133 MHz – 90 mA 7.5-ns cycle, 133 MHz – 40 mA ISB1 Automatic CE power-down current – TTL inputs ISB2 Automatic CE power-down current – CMOS inputs ISB3 Automatic CE power-down current – CMOS inputs VDD = Max, device deselected, 7.5-ns cycle, VIN 0.3 V or VIN > VDDQ – 0.3 V, 133 MHz f = fMAX = 1/tCYC – 75 mA ISB4 Automatic CE power-down current – TTL inputs VDD = Max, device deselected, 7.5-ns cycle, VIN VIH or VIN VIL, f = 0 133 MHz – 45 mA VDD = Max, device deselected, VIN VIH or VIN VIL, f = fMAX = 1/tCYC VDD = Max, device deselected, VIN 0.3 V or VIN > VDDQ – 0.3 V, f=0 Notes 11. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2). 12. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document Number: 38-05520 Rev. *N Page 9 of 22 CY7C1339G Capacitance Parameter [13] Description CIN Input capacitance CCLK Clock input capacitance CI/O Input/output capacitance 100-pin TQFP Package Test Conditions TA = 25 C, f = 1 MHz, VDD = 3.3 V, VDDQ = 3.3 V Unit 5 pF 5 pF 5 pF Test Conditions 100-pin TQFP Package Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 30.32 C/W 6.85 C/W Thermal Resistance Parameter [13] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms 3.3 V I/O Test Load R = 317 3.3 V OUTPUT OUTPUT RL = 50 Z0 = 50 VT = 1.5 V (a) GND 5 pF R = 351 INCLUDING JIG AND SCOPE 10% 1 ns 1 ns (c) R = 1667 2.5 V OUTPUT OUTPUT RL = 50 GND R = 1538 VT = 1.25 V (a) ALL INPUT PULSES VDDQ 5 pF INCLUDING JIG AND SCOPE 90% 10% 90% (b) 2.5 V I/O Test Load Z0 = 50 ALL INPUT PULSES VDDQ (b) 10% 90% 10% 90% 1 ns 1 ns (c) Note 13. Tested initially and after any design or process change that may affect these parameters. Document Number: 38-05520 Rev. *N Page 10 of 22 CY7C1339G Switching Characteristics Over the Operating Range Parameter [14, 15] tPOWER Description VDD(typical) to the first access [16] -133 Unit Min Max 1 – ms Clock tCYC Clock cycle time 7.5 – ns tCH Clock HIGH 3.0 – ns tCL Clock LOW 3.0 – ns Output Times tCO Data output valid after CLK rise – 4.0 ns tDOH Data output hold after CLK rise 1.5 – ns 0 – ns tCLZ Clock to low Z [17, 18, 19] [17, 18, 19] tCHZ Clock to high Z tOEV OE LOW to output valid tOELZ OE LOW to output low Z [17, 18, 19] tOEHZ OE HIGH to output high Z [17, 18, 19] – 4.0 ns – 4.0 ns 0 – ns – 4.0 ns Set-up Times tAS Address set-up before CLK rise 1.5 – ns tADS ADSC, ADSP set-up before CLK rise 1.5 – ns tADVS ADV set-up before CLK rise 1.5 – ns tWES GW, BWE, BWX set-up before CLK rise 1.5 – ns tDS Data input set-up before CLK rise 1.5 – ns tCES Chip enable set-up before CLK rise 1.5 – ns Hold Times tAH Address hold after CLK rise 0.5 – ns tADH ADSP, ADSC hold after CLK rise 0.5 – ns tADVH ADV hold after CLK rise 0.5 – ns tWEH GW, BWE, BWX hold after CLK rise 0.5 – ns tDH Data input hold after CLK rise 0.5 – ns tCEH Chip enable hold after CLK rise 0.5 – ns Notes 14. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 15. Test conditions shown in (a) of Figure 2 on page 10 unless otherwise noted. 16. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 17. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 10. Transition is measured ± 200 mV from steady-state voltage. 18. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z prior to low Z under the same system conditions. 19. This parameter is sampled and not 100% tested. Document Number: 38-05520 Rev. *N Page 11 of 22 CY7C1339G Switching Waveforms Figure 3. Read Cycle Timing [20] t CYC CLK t CH t ADS t CL t ADH ADSP tADS tADH ADSC tAS tAH A1 ADDRESS A2 tWES A3 Burst continued with new base address tWEH GW, BWE, BW[A:D] tCES Deselect cycle tCEH CE tADVS tADVH ADV ADV suspends burst. OE t OEHZ t CLZ Data Out (Q) High-Z Q(A1) tOEV tCO t OELZ tDOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) t CO Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note 20. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document Number: 38-05520 Rev. *N Page 12 of 22 CY7C1339G Switching Waveforms (continued) Figure 4. Write Cycle Timing [21, 22] t CYC CLK tCH tADS tCL tADH ADSP tADS ADSC extends burst tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst tWES tWEH BWE, BW[A :D] tWES tWEH GW tCES tCEH CE t t ADVS ADVH ADV ADV suspends burst OE tDS Data In (D) High-Z t OEHZ tDH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Notes 21. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW. Document Number: 38-05520 Rev. *N Page 13 of 22 CY7C1339G Switching Waveforms (continued) Figure 5. Read/Write Cycle Timing [23, 24, 25] tCYC CLK tCL tCH tADS tADH ADSP ADSC tAS ADDRESS A1 tAH A2 A3 A4 tWES tWEH tDS tDH A5 A6 D(A5) D(A6) BWE, BW[A:D] tCES tCEH CE ADV OE tCO tOELZ Data In (D) High-Z tOEHZ tCLZ Data Out (Q) High-Z Q(A1) D(A3) Q(A4) Q(A2) Back-to-Back READs Single WRITE Q(A4+1) BURST READ DON’T CARE Q(A4+2) Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes 23. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 24. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 25. GW is HIGH. Document Number: 38-05520 Rev. *N Page 14 of 22 CY7C1339G Switching Waveforms (continued) Figure 6. ZZ Mode Timing [26, 27] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 26. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 27. DQs are in high Z when exiting ZZ sleep mode. Document Number: 38-05520 Rev. *N Page 15 of 22 CY7C1339G Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (MHz) 133 Package Diagram Ordering Code CY7C1339G-133AXC Package Type 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Operating Range Commercial Ordering Code Definitions CY 7 C 1339 G - 133 A X C Temperature range: C = Commercial Pb-free Package Type: A = 100-pin TQFP Speed Grade: 133 MHz Process Technology: G 90 nm 1339 = Part Identifier Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05520 Rev. *N Page 16 of 22 CY7C1339G Package Diagrams Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050 51-85050 *D Document Number: 38-05520 Rev. *N Page 17 of 22 CY7C1339G Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius EIA Electronic Industries Alliance MHz megahertz I/O Input/Output µA microampere JEDEC Joint Electron Devices Engineering Council mA milliampere OE Output Enable mm millimeter SRAM Static Random Access Memory ms millisecond TQFP Thin Quad Flat Pack mV millivolt TTL Transistor-Transistor Logic ns nanosecond ohm % percent pF picofarad V volt W watt Document Number: 38-05520 Rev. *N Symbol Unit of Measure Page 18 of 22 CY7C1339G Errata This section describes the Ram9 Sync/NoBL ZZ pin, JTAG and Chip Enable issues. Details include trigger conditions, the devices affected, proposed workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions. Part Numbers Affected Density & Revision Package Type Operating Range 4Mb-Ram9 Synchronous SRAMs: CY7C133*G All packages Commercial/ Industrial Product Status All of the devices in the Ram9 4Mb Sync/NoBL family are qualified and available in production quantities. Ram9 Sync/NoBL ZZ Pin Issues Errata Summary The following table defines the errata applicable to available Ram9 4Mb Sync/NoBL family devices. Item 1. Issues ZZ Pin Description Device When asserted HIGH, the ZZ pin places device in a “sleep” condition with data integrity preserved.The ZZ pin currently does not have an internal pull-down resistor and hence cannot be left floating externally by the user during normal mode of operation. 4M-Ram9 (90nm) Fix Status For the 4M Ram9 (90 nm) devices, there is no plan to fix this issue. 1. ZZ Pin Issue ■ PROBLEM DEFINITION The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the SRAM. ■ TRIGGER CONDITIONS Device operated with ZZ pin left floating. ■ SCOPE OF IMPACT When the ZZ pin is left floating, the device delivers incorrect data. ■ WORKAROUND Tie the ZZ pin externally to ground. ■ FIX STATUS Fix was done for the 72Mb RAM9 Synchronous SRAMs and 72M RAM9 NoBL SRAMs devices. Fixed devices have a new revision. The following table lists the devices affected and the new revision after the fix. Document Number: 38-05520 Rev. *N Page 19 of 22 CY7C1339G Document History Page Document Title: CY7C1339G, 4-Mbit (128 K × 32) Pipelined Sync SRAM Document Number: 38-05520 Rev. ECN No. Issue Date Orig. of Change Description of Change ** 224368 See ECN RKF New data sheet. *A 288909 See ECN VBL Updated Ordering Information (Updated part numbers (Added Pb-free BGA package), changed TQFP package to Pb-free TQFP package). *B 332895 See ECN SYT Updated Pin Configurations (Modified Address Expansion balls in the pinouts for 100-pin TQFP and 119-ball BGA Packages as per JEDEC standards). Updated Pin Definitions. Updated Electrical Characteristics (Updated test conditions for VOL and VOH parameters). Updated Thermal Resistance (Replaced TBDs for JA and JC to their respective values). Updated Ordering Information (By shading and unshading MPNs as per availability). *C 351194 See ECN PCI Updated Ordering Information (Updated part numbers). *D 366728 See ECN PCI Updated Electrical Characteristics (Updated test conditions for VDD and VDDQ parameters, updated Note 12 (Changed test condition from VIH < VDD to VIH < VDD). *E 420883 See ECN RXU Changed status from Preliminary to Final. Changed address of Cypress Semiconductor Corporation from “3901 North First Street” to “198 Champion Court”. Updated Operating Range (Added Automotive Range). Updated Electrical Characteristics (Changed “Input Load Current except ZZ and MODE” to “Input Leakage Current except ZZ and MODE”). Updated Ordering Information (Updated part numbers, replaced Package Name column with Package Diagram in the Ordering Information table). Replaced Package Diagram of 51-85050 from *A to *B *F 480368 See ECN VKN Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND). Updated Ordering Information (Updated part numbers). *G 2896584 03/19/2010 NJY Updated Ordering Information (Removed obsolete part numbers). Updated Package Diagrams. *H 3045943 10/03/2010 NJY Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits and updated in new template. *I 3052769 10/08/2010 NJY Updated Ordering Information (Removed pruned part CY7C1339G-133AXI). *J 3365114 09/07/2011 PRIT Updated Package Diagrams. Updated in new template. Document Number: 38-05520 Rev. *N Page 20 of 22 CY7C1339G Document History Page (continued) Document Title: CY7C1339G, 4-Mbit (128 K × 32) Pipelined Sync SRAM Document Number: 38-05520 Rev. ECN No. Issue Date *K 3587066 05/10/2012 Orig. of Change Description of Change NJY / PRIT Updated Features (Removed 250 MHz, 200 MHz, and 166 MHz frequencies related information, removed 119-ball BGA package related information). Updated Functional Description (Removed the Note “For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.” and its reference). Updated Selection Guide (Removed 250 MHz, 200 MHz, and 166 MHz frequencies related information). Updated Pin Configurations (Removed 119-ball BGA package related information). Updated Pin Definitions (Removed 119-ball BGA package related information). Updated Functional Overview (Removed 250 MHz, 200 MHz, and 166 MHz frequencies related information). Updated Truth Table (Updated Note 6 (Removed 119-ball BGA package related information)). Updated Operating Range (Removed Industrial and Automotive Temperature Ranges). Updated Electrical Characteristics (Removed 250 MHz, 200 MHz, and 166 MHz frequencies related information, removed Industrial and Automotive Temperature Ranges). Updated Capacitance (Removed 119-ball BGA package related information). Updated Thermal Resistance (Removed 119-ball BGA package related information). Updated Switching Characteristics (Removed 250 MHz, 200 MHz, and 166 MHz frequencies related information). Updated Package Diagrams (Removed 119-ball BGA package related information). *L 3766472 10/04/2012 PRIT No technical updates. Completing sunset review. *M 3984870 05/02/2013 PRIT Added Errata. *N 4039556 06/25/2013 PRIT Added Errata Footnotes. Updated in new template. Document Number: 38-05520 Rev. *N Page 21 of 22 CY7C1339G Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05520 Rev. *N Revised June 25, 2013 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 22 of 22