CY7C1327G 4-Mbit (256 K × 18) Pipelined Sync SRAM 4-Mbit (256 K × 18) Pipelined Sync SRAM Features Functional Description ■ Registered inputs and outputs for pipelined operation The CY7C1327G SRAM integrates 256 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BW[A:B], and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. ■ 256 K × 18 common I/O Architecture ■ 3.3 V core power supply (VDD) ■ 2.5 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 3.5 ns (for 166-MHz device) ■ Provide high performance 3-1-1-1 access rate ■ User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed writes ■ Asynchronous output enable ■ Offered in Pb-free 100-pin TQFP package ■ “ZZ” sleep mode option Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports byte write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1327G operates from a +3.3 V core power supply while all outputs also operate with a +3.3 V or a +2.5 V supply. All inputs and outputs are JEDEC-standard JESD8-5compatible. Logic Block Diagram A0, A1, A ADDRESS REGISTER 2 MODE A[1:0] BURST Q1 COUNTER AND LOGIC CLR Q0 ADV CLK ADSC ADSP BW B DQ B, DQP B WRITE DRIVER DQ B, DQP B WRITE REGISTER MEMORY ARRAY BW A DQ A, DQP A WRITE DRIVER DQ A, DQP A WRITE REGISTER SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS DQs DQP A DQP B E BWE GW CE 1 CE2 CE3 ENABLE REGISTER INPUT REGISTERS PIPELINED ENABLE OE ZZ SLEEP CONTROL Cypress Semiconductor Corporation Document Number: 38-05519 Rev. *K • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 20, 2012 CY7C1327G Contents Selection Guide ................................................................ 3 Pin Configurations ........................................................... 3 Pin Definitions .................................................................. 4 Functional Overview ........................................................ 5 Single Read Accesses ................................................ 5 Single Write Accesses Initiated by ADSP ................... 5 Single Write Accesses Initiated by ADSC ................... 5 Burst Sequences ......................................................... 5 Sleep Mode ................................................................. 5 Interleaved Burst Address Table ................................. 6 Linear Burst Address Table ......................................... 6 ZZ Mode Electrical Characteristics .............................. 6 Truth Table ........................................................................ 7 Truth Table for Read/Write .............................................. 8 Maximum Ratings ............................................................. 9 Operating Range ............................................................... 9 Neutron Soft Error Immunity ........................................... 9 Document Number: 38-05519 Rev. *K Electrical Characteristics ................................................. 9 Capacitance .................................................................... 10 Thermal Resistance ........................................................ 10 AC Test Loads and Waveforms ..................................... 11 Switching Characteristics .............................................. 12 Switching Waveforms .................................................... 13 Ordering Information ...................................................... 17 Ordering Code Definitions ......................................... 17 Package Diagrams .......................................................... 18 Acronyms ........................................................................ 19 Document Conventions ................................................. 19 Units of Measure ....................................................... 19 Document History Page ................................................. 20 Sales, Solutions, and Legal Information ...................... 22 Worldwide Sales and Design Support ....................... 22 Products .................................................................... 22 PSoC Solutions ......................................................... 22 Page 2 of 22 CY7C1327G Selection Guide 166 MHz 133 MHz Unit Maximum access time Description 3.5 4.0 ns Maximum operating current 240 225 mA Maximum CMOS standby current 40 40 mA Pin Configurations NC NC NC BYTE B VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1327G 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC BYTE A MODE A A A A A1 A0 NC/72M NC/36M VSS VDD NC/18M NC/9M A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A Figure 1. 100-pin TQFP Pinout Document Number: 38-05519 Rev. *K Page 3 of 22 CY7C1327G Pin Definitions Name I/O Description A0, A1, A InputAddress inputs used to select one of the 256 K address locations. Sampled at the rising edge of the synchronous CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0 feed the 2-bit counter. BWA, BWB InputByte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled synchronous on the rising edge of CLK. GW InputGlobal write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write synchronous is conducted (all bytes are written, regardless of the values on BW[A:B] and BWE). BWE InputByte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted synchronous LOW to conduct a byte write. CLK Inputclock Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 synchronous and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. CE3 InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE2 to select/deselect the device. CE3 is sampled only when a new external address is loaded. OE InputOutput enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputAdvance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it synchronous automatically increments the address in a burst cycle. ADSP InputAddress strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted synchronous LOW, A is captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ZZ InputZZ “sleep” input, active HIGH. This input, when High places the device in a non-time-critical “sleep” asynchronous condition with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has an internal pull-down. ADSC InputAddress strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted synchronous LOW, A is captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. DQA, DQB, DQPA, DQPB I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by “A” during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a tristate condition. VDD Power supply Power supply inputs to the core of the device. VSS Ground Ground for the device. VDDQ I/O ground MODE Inputstatic Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. – No connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M, NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the die. NC, NC/9M, NC/18M, NC/72M, NC/144M, NC/288M, NC/576M, NC/1G Ground for the I/O circuitry. Document Number: 38-05519 Rev. *K Page 4 of 22 CY7C1327G Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1327G supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the byte write enable (BWE) and byte write select (BW[A:B]) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous chip selects (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output tristate control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the write signals (GW, BWE) are all deserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the address register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the output registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tCO if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tristated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tristate immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The Write signals (GW, BWE, and BW[A:B]) and ADV inputs are ignored during this first cycle. ADSP-triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQ inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the Document Number: 38-05519 Rev. *K Write operation is controlled by BWE and BW[A:B] signals. The CY7C1327G provides byte write capability that is described in the Write Cycle Descriptions table. Asserting the byte write enable input (BWE) with the selected byte write (BW[A:B]) input, will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the write operations. Because the CY7C1327G is a common I/O device, the output enable (OE) must be deserted HIGH before presenting data to the DQ inputs. Doing so will tristate the output drivers. As a safety precaution, DQs are automatically tristated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BW[A:B]) are asserted active to conduct a write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to DQ is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1327G is a common I/O device, the output enable (OE) must be deserted HIGH before presenting data to the DQ inputs. Doing so will tristate the output drivers. As a safety precaution, DQs are automatically tristated whenever a Write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1327G provides a two-bit wraparound counter, fed by A1:A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Page 5 of 22 CY7C1327G Interleaved Burst Address Table Linear Burst Address Table (MODE = Floating or VDD) (MODE = GND) First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 00 01 10 11 00 01 10 11 01 00 11 10 01 10 11 00 10 11 00 01 10 11 00 01 11 10 01 00 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Snooze mode standby current ZZ > VDD– 0.2 V – 40 mA tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC – ns tZZI ZZ active to snooze current This parameter is sampled – 2tCYC ns tRZZI ZZ Inactive to exit snooze current This parameter is sampled 0 – ns Document Number: 38-05519 Rev. *K Page 6 of 22 CY7C1327G Truth Table The Truth Table for CY7C1327G follows. [1, 2, 3, 4, 5] OE DQ WRITE Unselected Next Cycle Add. Used None CE1 CE2 CE3 H X X ZZ L ADSP ADSC ADV X L X X Tri-state X Unselected None L X H L L X X X Tri-state X Unselected None L L X L L X X X Tri-state X Unselected None L X H L H L X X Tri-state X Unselected None L L X L H L X X Tri-state X Begin read External L H L L L X X X Tri-state X Begin read External L H L L H L X X Tri-state H Continue read Next X X X L H H L H Tri-state H Continue read Next X X X L H H L L DQ H Continue read Next H X X L X H L H Tri-state H Continue read Next H X X L X H L L DQ H Suspend read Current X X X L H H H H Tri-state H Suspend read Current X X X L H H H L DQ H Suspend read Current H X X L X H H H Tri-state H Suspend read Current H X X L X H H L DQ H Begin write Current X X X L H H H X Tri-state L Begin write Current H X X L X H H X Tri-state L Begin write External L H L L H H X X Tri-state L Continue write Next X X X L H H H X Tri-state L Continue write Next H X X L X H H X Tri-state L Suspend write Current X X X L H H H X Tri-state L Suspend write Current H X X L X H H X Tri-state L None X X X H X X X X Tri-state X ZZ “sleep” Notes 1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 2. WRITE = L when any one or more byte write enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all byte write enable signals (BWA, BWB), BWE, GW = H. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care for the remainder of the write cycle. 5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 38-05519 Rev. *K Page 7 of 22 CY7C1327G Truth Table for Read/Write The Truth Table for Read/Write follows. [6] GW BWE BWB BWA Read Function H H X X Read H L H H Write byte A – (DQA and DQPA) H L H L Write byte B – (DQB and DQPB) H L L H Write bytes B, A H L L L Write all bytes H L L L Write all bytes L X X X Note 6. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. Document Number: 38-05519 Rev. *K Page 8 of 22 CY7C1327G Maximum Ratings Operating Range Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Ambient Range Temperature Commercial 0 C to +70 C Industrial –40 C to +85 C Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied .......................................... –55 C to +125 C Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD DC voltage applied to outputs in tristate ...........................................–0.5 V to VDDQ + 0.5 V Static discharge voltage (per MIL-STD-883, method 3015) .......................... > 2001 V Latch-up current .................................................... > 200 mA VDDQ 2.5 V – 5% to VDD Neutron Soft Error Immunity Parameter Description Test Conditions Typ Max* Unit LSBU Logical single-bit upsets 25 °C 361 394 FIT/ Mb LMBU Logical multi-bit upsets 25 °C 0 0.01 FIT/ Mb Single event latch-up 85 °C 0 0.1 FIT/ Dev DC input voltage ................................. –0.5 V to VDD + 0.5 V Current into outputs (LOW) ........................................ 20 mA VDD 3.3 V– 5% / + 10% SEL * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates”. Electrical Characteristics Over the Operating Range Parameter [7, 8] Description Test Conditions Min Max Unit VDD Power supply voltage 3.135 3.6 V VDDQ I/O supply voltage 2.375 VDD V VOH Output HIGH voltage for 3.3 V I/O, IOH = –4.0 mA 2.4 – V for 2.5 V I/O, IOH = –1.0 mA 2.0 – V for 3.3 V I/O, IOL = 8.0 mA – 0.4 V for 2.5 V I/O, IOL = 1.0 mA – 0.4 V for 3.3 V I/O 2.0 VDD + 0.3 V V for 2.5 V I/O 1.7 VDD + 0.3 V V for 3.3 V I/O –0.3 0.8 V for 2.5 V I/O –0.3 0.7 V Input leakage current except ZZ GND VI VDDQ and MODE –5 5 A Input current of MODE Input = VSS –30 – A Input = VDD – 5 A Input = VSS –5 – A Input = VDD – 30 A GND VI VDDQ, output disabled –5 5 A VOL VIH VIL IX Output LOW voltage Input HIGH voltage [7] Input LOW voltage [7] Input current of ZZ IOZ Output leakage current Notes 7. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2). 8. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document Number: 38-05519 Rev. *K Page 9 of 22 CY7C1327G Electrical Characteristics (continued) Over the Operating Range Parameter [7, 8] Description IDD VDD operating supply current ISB1 Automatic CE power-down current – TTL inputs Test Conditions VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC VDD = Max, device deselected, VIN VIH or VIN VIL, f = fMAX = 1/tCYC Min Max Unit 6 ns cycle, 166 MHz – 240 mA 7.5 ns cycle, 133 MHz – 225 mA 6 ns cycle, 166 MHz – 100 mA 7.5 ns cycle, 133 MHz – 90 mA ISB2 Automatic CE power-down current – CMOS inputs VDD = Max, device deselected, All speeds VIN 0.3 V or VIN > VDDQ – 0.3 V, f=0 – 40 mA ISB3 Automatic CE power-down current – CMOS inputs VDD = Max, device deselected, 6 ns cycle, VIN 0.3 V or VIN > VDDQ – 0.3 V, 166 MHz f = fMAX = 1/tCYC 7.5 ns cycle, 133 MHz – 85 mA – 75 mA – 45 mA ISB4 Automatic CE power-down current – TTL inputs VDD = Max, device deselected, VIN VIH or VIN VIL, f = 0 All speeds Capacitance Parameter [9] Description CIN Input capacitance CCLK Clock input capacitance CI/O Input/output capacitance 100-pin TQFP Max Unit 5 pF 5 pF 5 pF Test Conditions 100-pin TQFP Package Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 30.32 °C/W 6.85 °C/W Test Conditions TA = 25 C, f = 1 MHz, VDD = 3.3 V, VDDQ = 3.3 V Thermal Resistance Parameter [9] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Note 9. Tested initially and after any design or process change that may affect these parameters. Document Number: 38-05519 Rev. *K Page 10 of 22 CY7C1327G AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms 3.3 V I/O Test Load R = 317 3.3 V OUTPUT OUTPUT RL = 50 Z0 = 50 GND 5 pF R = 351 VT = 1.5 V INCLUDING JIG AND SCOPE (a) 2.5 V I/O Test Load OUTPUT RL = 50 Z0 = 50 Document Number: 38-05519 Rev. *K INCLUDING JIG AND SCOPE 1 ns 1 ns (c) ALL INPUT PULSES VDDQ GND 5 pF R = 1538 (b) 90% 10% 90% (b) VT = 1.25 V (a) 10% R = 1667 2.5 V OUTPUT ALL INPUT PULSES VDDQ 10% 90% 10% 90% 1 ns 1 ns (c) Page 11 of 22 CY7C1327G Switching Characteristics Over the Operating Range Parameter [10, 11] tPOWER Description VDD(typical) to the first access [12] -166 -133 Unit Min Max Min Max 1 – 1 – ms Clock tCYC Clock cycle time 6.0 – 7.5 – ns tCH Clock HIGH 2.5 – 3.0 – ns tCL Clock LOW 2.5 – 3.0 – ns Output Times tCO Data output valid after CLK rise – 3.5 – 4.0 ns tDOH Data output hold after CLK rise 1.5 – 1.5 – ns 0 – 0 – ns tCLZ Clock to low Z [13, 14, 15] [13, 14, 15] tCHZ Clock to high Z tOEV OE LOW to output valid tOELZ OE LOW to output low Z [13, 14, 15] tOEHZ OE HIGH to output high Z [13, 14, 15] – 3.5 – 4.0 ns – 3.5 – 4.5 ns 0 – 0 – ns – 3.5 – 4.0 ns Set-up Times tAS Address set-up before CLK rise 1.5 – 1.5 – ns tADS ADSC, ADSP setup before CLK rise 1.5 – 1.5 – ns tADVS ADV setup before CLK rise 1.5 – 1.5 – ns tWES GW, BWE, BWX setup before CLK rise 1.5 – 1.5 – ns tDS Data input setup before CLK rise 1.5 – 1.5 – ns tCES Chip enable setup before CLK rise 1.5 – 1.5 – ns Hold Times tAH Address hold after CLK rise 0.5 – 0.5 – ns tADH ADSP, ADSC hold after CLK rise 0.5 – 0.5 – ns tADVH ADV hold after CLK rise 0.5 – 0.5 – ns tWEH GW, BWE, BWX hold after CLK rise 0.5 – 0.5 – ns tDH Data input hold after CLK rise 0.5 – 0.5 – ns tCEH Chip enable hold after CLK rise 0.5 – 0.5 – ns Notes 10. Timing references level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V on all data sheets. 11. Test conditions shown in (a) of Figure 2 on page 11 unless otherwise noted. 12. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 13. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 11. Transition is measured ±200 mV from steady-state voltage. 14. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z prior to low Z under the same system conditions. 15. This parameter is sampled and not 100% tested. Document Number: 38-05519 Rev. *K Page 12 of 22 CY7C1327G Switching Waveforms Figure 3. Read Cycle Timing [16] t CYC CLK t t CH t CL t ADH ADS ADSP t ADS tADH ADSC t AS ADDRESS tAH A1 A2 t WES A3 Burst continued with new base address tWEH GW, BWE, BW [A:B] t CES Deselect cycle tCEH CE t ADVS tADVH ADV ADV suspends burst. OE t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t OEV t CO t OELZ t DOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) t CO Single READ BURST READ DON’T CARE Burst wraps around to its initial state UNDEFINED Note 16. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document Number: 38-05519 Rev. *K Page 13 of 22 CY7C1327G Switching Waveforms (continued) Figure 4. Write Cycle Timing [17, 18] t CYC CLK tCH t ADS tCL tADH ADSP t ADS ADSC extends burst tADH t ADS tADH ADSC t AS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst t WES tWEH BWE, BW[A :B] t WES tWEH GW t CES tCEH CE t t ADVS ADVH ADV ADV suspends burst OE t DS Data In (D) High-Z t OEHZ tDH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Notes 17. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW. Document Number: 38-05519 Rev. *K Page 14 of 22 CY7C1327G Switching Waveforms (continued) Figure 5. Read/Write Cycle Timing [19, 20, 21] tCYC CLK tCL tCH t ADS tADH t AS tAH ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 t WES tWEH BWE, BW [A:B] t CES tCEH CE ADV OE t DS tCO Data In (D) t OELZ High-Z tCLZ Data Out (Q) tDH High-Z Q(A1) Back-to-Back READs tOEHZ D(A5) D(A3) Q(A2) Q(A4) Single WRITE Q(A4+1) BURST READ DON’T CARE Q(A4+2) D(A6) Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes 19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 20. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 21. GW is HIGH. Document Number: 38-05519 Rev. *K Page 15 of 22 CY7C1327G Switching Waveforms (continued) Figure 6. ZZ Mode Timing [22, 23] CLK t ZZ I t t ZZ ZZREC ZZI SUPPLY I t RZZI DDZZ ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 23. DQs are in high Z when exiting ZZ sleep mode. Document Number: 38-05519 Rev. *K Page 16 of 22 CY7C1327G Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices Speed (MHz) Package Diagram Ordering Code Package Type Operating Range 133 CY7C1327G-133AXI 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Industrial 166 CY7C1327G-166AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial Ordering Code Definitions CY 7 C 1327 G - XXX A X X Temperature range: X = C or I C = Commercial; I = Industrial Pb-free Package Type: A = 100-pin TQFP Speed Grade: XXX = 133 MHz or 166 MHz Process Technology: G 90 nm 1327 = SCD, 256 K × 18 (4 Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05519 Rev. *K Page 17 of 22 CY7C1327G Package Diagrams Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050 51-85050 *D Document Number: 38-05519 Rev. *K Page 18 of 22 CY7C1327G Acronyms Acronym Document Conventions Description Units of Measure CE chip enable CMOS complementary metal oxide semiconductor °C degree Celsius EIA electronic industries alliance MHz megahertz I/O input/output µA microampere JEDEC joint electron devices engineering council mA milliampere LMBU logical multi-bit upsets ms millisecond LSBU logical single-bit upsets mm millimeter OE output enable mV millivolt SEL single event latch-up nm nanometer SRAM static random access memory ns nanosecond TQFP thin quad flat pack ohm TTL transistor-transistor logic % percent Document Number: 38-05519 Rev. *K Symbol Unit of Measure pF picofarad V volt W watt Page 19 of 22 CY7C1327G Document History Page Document Title: CY7C1327G, 4-Mbit (256 K × 18) Pipelined Sync SRAM Document Number: 38-05519 Rev. ECN No. Submission Date Orig. of Change Description of Change ** 224367 See ECN RKF New data sheet. *A 278513 See ECN VBL Updated Ordering Information (Updated part numbers (Changed TQFP to Pb-free TQFP, added PB-free BGA packages)). *B 332895 See ECN SYT Updated Features (Removed 225 MHz, 100 MHz frequencies related information). Updated Selection Guide (Removed 225 MHz, 100 MHz frequencies related information). Updated Pin Configurations (Modified Address Expansion balls in the pinouts for 100-pin TQFP and 119-ball BGA Packages as per JEDEC standards). Updated Pin Definitions. Updated Electrical Characteristics (Removed 225 MHz, 100 MHz frequencies related information, updated Test Conditions of VOL and VOH parameters). Updated Thermal Resistance (Replaced values of JA and JC parameters from TBD to respective Thermal Values for all packages). Updated Switching Characteristics (Removed 225 MHz, 100 MHz frequencies related information). Updated Ordering Information (By shading and unshading MPNs as per availability, removed comment on the availability of BGA lead-free package). *C 351194 See ECN PCI Updated Ordering Information (Updated part numbers). *D 366728 See ECN PCI Updated Electrical Characteristics (Added test conditions for VDD and VDDQ parameters, updated Note 8 (Replaced VIH < VDD with VIH < VDD)). *E 419256 See ECN RXU Changed status from Preliminary to Final. Changed address of Cypress Semiconductor Corporation from “3901 North First Street” to “198 Champion Court”. Updated Electrical Characteristics (Changed “Input Load Current except ZZ and MODE” to “Input Leakage Current except ZZ and MODE” in the description of IX parameter). Updated Ordering Information (Updated part numbers, replaced Package Name column with Package Diagram in the Ordering Information table). Updated Package Diagrams (spec 51-85050 (changed revision from *A to *B)). *F 480124 See ECN VKN Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND). Updated Ordering Information (Updated part numbers). *G 2756340 08/26/2009 *H 3044512 10/01/2010 NJY Added Ordering Code Definitions. Updated Package Diagrams. Added Acronyms and Units of Measure. Minor edits and updated in new template. *I 3363203 09/05/2011 PRIT Updated Package Diagrams. Updated in new template. Document Number: 38-05519 Rev. *K VKN/AESA Added Neutron Soft Error Immunity. Updated Ordering Information (By including parts that are available, and modified the disclaimer for the Ordering information). Page 20 of 22 CY7C1327G Document History Page (continued) Document Title: CY7C1327G, 4-Mbit (256 K × 18) Pipelined Sync SRAM Document Number: 38-05519 Rev. ECN No. Submission Date Orig. of Change Description of Change *J 3612268 05/09/2012 PRIT Updated Features (Removed 250 MHz, 200 MHz frequencies related information, removed 119-ball BGA package related information). Updated Functional Description (Removed the Note “For best practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.” and its reference). Updated Selection Guide (Removed 250 MHz, 200 MHz frequencies related information). Updated Pin Configurations (Removed 119-ball BGA package related information). Updated Electrical Characteristics (Removed 250 MHz, 200 MHz frequencies related information). Updated Capacitance (Removed 119-ball BGA package related information). Updated Thermal Resistance (Removed 119-ball BGA package related information). Updated Switching Characteristics (Removed 250 MHz, 200 MHz frequencies related information). *K 3749841 09/20/2012 PRIT No technical updates. Completing sunset review. Document Number: 38-05519 Rev. *K Page 21 of 22 CY7C1327G Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive PSoC Solutions cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2012. The information contained herein is subject to change without notice. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05519 Rev. *K Revised September 20, 2012 Page 22 of 22 i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark of IBM Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.