CYF0018V CYF0036V CYF0072V 18/36/72-Mbit Programmable FIFOs 18/36/72-Mbit Programmable FIFOs Features Functional Description ■ Memory organization ❐ Industry’s largest first in first out (FIFO) memory densities: 18-Mbit, 36-Mbit, and 72-Mbit ❐ Selectable memory organization: × 9, × 12, × 16, × 18, × 20, × 24, × 32, × 36 ■ Up to 133-MHz clock operation ■ Unidirectional operation ■ Independent read and write ports ❐ Supports simultaneous read and write operations ❐ Reads and writes operate on independent clocks, upto a maximum ratio of two, enabling data buffering across clock domains. ❐ Supports multiple I/O voltage standard: low voltage complementary metal oxide semiconductor (LVCMOS) 3.3 V and 1.8 V voltage standards. The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 133 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 4.8 Gbps. The user-programmable registers enable user to configure the device operation as desired. The device also offers a simple and easy-to-use interface to reduce implementation and debugging efforts, improve time-to-market, and reduce engineering costs. This makes it an ideal memory choice for a wide range of applications including multiprocessor interfaces, video and image processing, networking and telecommunications, high-speed data acquisition, or any system that needs buffering at high speeds across different clock domains. ■ Input and output enable control for write mask and read skip operations ■ Mark and retransmit: resets read pointer to user marked position ■ Empty, full, half-full, and programmable almost-empty and almost-full status flags with configured offsets ■ Flow-through mailbox register to send data from input to output port, bypassing the FIFO sequence ■ Configure programmable flags and registers through serial or parallel modes ■ Separate serial clock (SCLK) input for serial programming ■ Master reset to clear entire FIFO ■ Partial reset to clear data but retain programmable settings ■ Joint test action group (JTAG) port provided for boundary scan function ■ Industrial temperature range: –40 °C to +85 °C Cypress Semiconductor Corporation Document Number: 001-53687 Rev. *M • As implied by the name, the functionality of the FIFO is such that the data is read out of the read port in the same sequence in which it was written into the write port. If writes and inputs are enabled (WEN & IE), data on the write port gets written into the device at the rising edge of write clock. Enabling reads and outputs (REN & OE) fetches data on the read port at every rising edge of read clock. Both reads and writes can occur simultaneously at different speeds provided the ratio between read and write clock is in the range of 0.5 to 2. Appropriate flags are set whenever the FIFO is empty, almost-empty, half-full, almost-full or full. The device also supports mark and retransmit of data, and a flow-through mailbox register. All product features and specs are common to all densities (CYF0072V, CYF0036V, and CYF0018V). All descriptions are given assuming the 72Mbit (CYF0072V) device is operated in × 36 mode. They are valid for other densities (CYF0036V, and CYF0018V) and all port sizes × 9, × 12, × 16, × 18, × 20, × 24 and × 32 unless otherwise specified. The only difference will be in the input and output bus width. Table 1 on page 7 shows the part of bus with valid data from D[35:0] and Q[35:0] in × 9, × 12, × 16, × 18, × 20, × 24, × 32 and × 36 modes. 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 11, 2013 CYF0018V CYF0036V CYF0072V Logic Block Diagram D[35:0] IE WEN WCLK LD INPUT REGISTER SPI_SEN SPI_SCLK CONFIGURATION REGISTERS/MAILBOX SPI_SI MB WRITE CONTROL LOGIC FF PAF WRITE POINTER FLAG LOGIC EF PAE Memory Array MRS PRS RESET POINTER DVal HF 18 Mbit 36 Mbit 72 Mbit READ POINTER TCK TRST TMS JTAG CONTROL READ CONTROL LOGIC TDO MARK, RT TDI OUTPUT REGISTER RCLK REN OE MEMORY LOGIC ORGANIZATION Q[35:0] PORTSZ[2:0] Document Number: 001-53687 Rev. *M Page 2 of 36 CYF0018V CYF0036V CYF0072V Contents Pin Diagram for CYF0XXXVXXL [1] ................................. 4 Pin Definitions .................................................................. 5 Architecture ...................................................................... 7 Reset Logic ................................................................. 7 Selecting Word Sizes .................................................. 7 Memory Organization for Different Port Sizes ............. 7 Data Valid Signal (DVal) .............................................. 8 Write Mask and Read Skip Operation ......................... 8 Flow-through Mailbox Register .................................... 8 Flag Operation ............................................................. 8 Retransmit from Mark Operation ................................. 9 Programming Flag Offsets and Configuration Registers ...................................................... 9 Width Expansion Configuration ................................. 13 Power Up ................................................................... 13 Read/Write Clock Requirements ............................... 13 JTAG Operation ........................................................ 14 Maximum Ratings ........................................................... 15 Operating Range ............................................................. 15 Recommended DC Operating Conditions .................... 15 Electrical Characteristics ............................................... 15 I/O Characteristics .......................................................... 16 Latency Table .................................................................. 16 Document Number: 001-53687 Rev. *M Switching Characteristics .............................................. 18 Switching Waveforms .................................................... 19 Ordering Information ...................................................... 28 Ordering Code Definitions ......................................... 28 Package Diagram ............................................................ 29 Acronyms ........................................................................ 30 Document Conventions ................................................. 30 Units of Measure ....................................................... 30 Appendix: Silicon Errata for the 18-Mbit, 36-Mbit, and 72-Mbit Programmable FIFO .......................................... 31 Part Numbers Affected .............................................. 31 18-Mbit, 36-Mbit, and 72-Mbit Programmable FIFO Qualification Status ........................................................... 31 18-Mbit, 36-Mbit, and 72-Mbit Programmable FIFO Errata Summary ............................................................... 31 Document History Page ................................................. 33 Sales, Solutions, and Legal Information ...................... 36 Worldwide Sales and Design Support ....................... 36 Products .................................................................... 36 PSoC Solutions ......................................................... 36 Page 3 of 36 CYF0018V CYF0036V CYF0072V Pin Diagram for CYF0XXXVXXL [1] Figure 1. 209-ball FBGA pinout (Top View) 1 2 3 4 5 6 7 8 9 10 11 A FF D0 D1 DNU PORTSZ0 PORTSZ1 DNU DNU RT Q0 Q1 B EF D2 D3 DNU DNU PORTSZ2 DNU DNU REN Q2 Q3 C D4 D5 WEN DNU VCC1 DNU VCC1 DNU RCLK Q4 Q5 D D6 D7 VSS VCC1 DNU LD DNU VCC1 Vss Q6 Q7 E D8 D9 VCC2 VCC2 VCCIO VCCIO VCCIO VCC2 VCC2 Q8 Q9 F D10 D11 VSS VSS VSS DNU VSS VSS VSS Q10 Q11 G D12 D13 VCC2 VCC2 VCCIO VCC1 VCCIO VCC2 VCC2 Q12 Q13 H D14 D15 VSS VSS VSS VCC1 VSS VSS VSS Q14 Q15 J D16 D17 VCC2 VCC2 VCCIO VCC1 VCCIO VCC2 VCC2 Q16 Q17 K DNU DNU WCLK DNU VSS IE VSS DNU VCCIO VCCIO VCCIO L D18 D19 VCC2 VCC2 VCCIO VCC1 VCCIO VCC2 VCC2 Q18 Q19 M D20 D21 VSS VSS VSS VCC1 VSS VSS VSS Q20 Q21 N D22 D23 VCC2 VCC2 VCCIO VCC1 VCCIO VCC2 VCC2 Q22 Q23 P D24 D25 VSS VSS VSS SPI_SEN VSS VSS VSS Q24 Q25 R D26 D27 VCC2 VCC2 VCCIO VCCIO VCCIO VCC2 VCC2 Q26 Q27 T D28 D29 VSS VCC1 VCC1 SPI_SI VCC1 VCC1 VSS Q28 Q29 [2] SPI_SCLK VREF OE Q30 Q31 U DVal DNU D30 D31 PRS DNU V PAF PAE D32 D33 DNU MRS MB DNU MARK Q32 Q33 W TDO HF D34 D35 TDI TRST TMS TCK DNU Q34 Q35 Notes 1. Pin Diagram for 18-Mbit, 36-Mbit & 72-Mbit; 1.8V & 3.3V IO voltage options. 2. This pin should be tied to VSS preferably or can be left floating to ensure normal operation. Document Number: 001-53687 Rev. *M Page 4 of 36 CYF0018V CYF0036V CYF0072V Pin Definitions Pin Name I/O Pin Description MRS Input Master reset: MRS initializes the internal read and write pointers to zero, resets all flags and sets the output register to all zeroes. During Master Reset, the configuration registers are set to default values. PRS Input Partial reset: PRS initializes the internal read and write pointers to zero, resets all flags and sets the output register to all zeroes. During Partial Reset, the configuration register settings are retained. PORTSZ [2:0] Input Port word size select: Port word width select pins (common for read and write ports). WCLK Input Write clock: The rising edge clocks data into the FIFO when writes are enabled (WEN asserted). Data is written into the FIFO memory when LD is high and into configuration registers when LD is low. LD Input Load: When LD is LOW, D[7:0] (Q[7:0]) are written (read) into (from) the configuration registers. When LD is HIGH, D[35:0] (Q[35:0]) are written (read) into (from) the FIFO memory. WEN Input Write enable: Control signal to enable writes to the device. When WEN is low data present on the inputs is written to the FIFO memory or configuration registers on every rising edge of WCLK. IE Input Input enable: IE is the data input enable signal that controls the enabling and disabling of the 36-bit data input pins. If it is enabled, data on the D[35:0] pins is written into the FIFO. The internal write address pointer is always incremented at rising edge of WCLK if WEN is enabled, regardless of the IE level. This is used for 'write masking' or incrementing the write pointer without writing into a location. D[35:0] Input Data inputs: Data inputs for a 36-bit bus. RCLK Input Read clock: The rising edge initiates a read from the FIFO when reads are enabled (REN asserted). Data is read from the FIFO memory when LD is high & from the configuration registers if LD is low. REN Input Read enable: Control signal to enable reads from the device. When REN is low data is read from the FIFO memory or configuration registers on every rising edge of RCLK. OE Input Output enable: When OE is LOW, FIFO data outputs are enabled; when OE is HIGH, the FIFO’s outputs are in High Z (high impedance) state. Q[35:0] Output Data outputs: Data outputs for a 36-bit bus. DVal Output Data valid: Active low data valid signal to indicate valid data on Q[35:0]. MARK Input Mark for retransmit: When this pin is asserted the memory location corresponding to the data present on the output bus is marked. Any subsequent retransmit operation resets the read pointer to this location. RT Input Retransmit: A HIGH pulse on RT resets the internal read pointer to a physical location of the FIFO which is marked by the user (using MARK pin). With every valid read cycle after retransmit, previously accessed data is read until the FIFO is empty. MB Input Mailbox: When asserted the reads and writes happen to flow-through mailbox register. EF Output Empty flag: When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. PAE Output Programmable almost-empty: When PAE is LOW, the FIFO is almost empty based on the almost-empty offset value programmed into the FIFO. It is synchronized to RCLK. HF Output Half-full flag: When HF is LOW, half of the FIFO is full. HF is synchronized to WCLK. PAF Output Programmable almost-full: When PAF is LOW, the FIFO is almost full based on the almost-full offset value programmed into the FIFO. It is synchronized to WCLK. FF Output Full flag: When FF is LOW, the FIFO is full. FF is synchronized to WCLK. SPI_SCLK Input Serial clock: A rising edge on SPI_SCLK clocks the serial data present on the SPI_SI input into the offset registers if SPI_SEN is enabled. SPI_SI Input Serial input: Serial input data in SPI mode. SPI_SEN Input Serial enable: Enables serial loading of programmable flag offsets and configuration registers. TCK Input Test clock (TCK) pin for JTAG. Document Number: 001-53687 Rev. *M Page 5 of 36 CYF0018V CYF0036V CYF0072V Pin Definitions (continued) Pin Name I/O Pin Description TRST Input Reset pin for JTAG. TMS Input Test mode select (TMS) pin for JTAG. TDI Input Test data in (TDI) pin for JTAG. TDO Output VREF Test data out (TDO) pin for JTAG. Input Reference voltage: Reference voltage (regardless of I/O standard used) Reference VCC1 Power Supply Core voltage supply 1: 1.8 V supply voltage VCC2 Power Supply Core voltage supply 2: 1.5 V supply voltage VCCIO Power Supply Supply for I/Os VSS Ground Ground DNU – Do not use: These pins need to be left floating. Document Number: 001-53687 Rev. *M Page 6 of 36 CYF0018V CYF0036V CYF0072V Architecture Reset Logic The CYF0072V, CYF0036V, and CYF0018V are memory arrays of 72-Mbit, 36-Mbit, and 18-Mbit respectively. The memory organization is user configurable and word sizes can be selected as × 9, × 12, × 16, × 18, × 20, × 24, × 32, or × 36. The logic blocks to implement the FIFO functionality and the associated features are built around these memory arrays. The FIFO can be reset in two ways: Master Reset (MRS) and Partial Reset (PRS). The MRS initializes the read and write pointers to zero and sets the output register to all zeroes. It also resets all flags & the configuration registers to their default values. The word size is configured through pins; values of the three PORTSZ pins are latched during MRS. A Master Reset is required after power-up before accessing the FIFO. The input and output data buses have a maximum width of 36 bits. The input data bus goes to an input register and the data flow from the input register to the memory is controlled by the write control logic. The inputs to the write logic block are WCLK, WEN and IE. When the writes are enabled through WEN and if the inputs are enabled by IE, then the data on the input bus is written into the memory array at the rising edge of WCLK. This also increments the write pointer. Enabling writes but disabling the data input pins through IE only increments the write pointer without doing any writes or altering the contents of the memory location. Similarly, the output register is connected to the data output bus. Transfer of contents from the memory to the output register is controlled by the read control logic. The inputs to the read control logic include RCLK, REN, OE, RT and MARK. When reads are enabled by REN and outputs are enabled using OE, the data from the memory pointed by the read pointer is transferred to the output data bus at the rising edge of RCLK along with active low DVal. If the outputs are disabled but the reads enabled, the outputs are in high impedance state, but internally the read pointer is incremented. During write operation, the number of writes performed is always an even number (i.e., minimum write burst length is two and number of writes always a multiple of two). Whereas during read operation, the number of reads performed can be even or odd (i.e., minimum read burst length is one). PRS resets the read pointer, write pointer and mark location to the first physical location in the memory array. It also resets all flags to their default values. PRS does not affect the programmed configuration register values. Any changes to configuration registers during device operation mandates a PRS cycle to guarantee accurate flag operation. Selecting Word Sizes The word sizes are configured based on the logic levels on the PORTSZ pins during the master reset (MRS) cycle only (latched on low to high edge). The port size cannot be changed during normal mode of operation and these pins are ignored. Table 1. explains the pins of D[35:0] and Q[35:0] that will have valid data in modes where the word size is less than × 36. If word size is less than × 36, the unused output pins are tri-stated by the device and unused input pins will be ignored by the internal logic. The pins with valid data input D[N:0] and output Q[N:0] is given in Table 1. Memory Organization for Different Port Sizes The 72-Mbit memory has different organization for different port sizes. Table 1 shows the depth of the FIFO for all port sizes. Note that for all port sizes, four to eight locations are not available for writing the data and are used to safeguard against false synchronization of empty and full flags. The MARK signal is used to ‘mark’ the location from which data is retransmitted when requested and RT is asserted to retransmit the data from the marked location. Table 1. Word Size Selection PORTSZ[2:0] Word Size FIFO Depth [3] Memory Size [3] Active Input Data Pins D[N:0] Active Output Data Pins Q[N:0] 000 ×9 8 Meg 72-Mbit D[8:0] Q[8:0] 001 × 12 4 Meg 48-Mbit D[11:0] Q[11:0] 010 × 16 4 Meg 64-Mbit D[15:0] Q[15:0] 011 × 18 4 Meg 72-Mbit D[17:0] Q[17:0] 100 × 20 2 Meg 40-Mbit D[19:0] Q[19:0] 101 × 24 2 Meg 48-Mbit D[23:0] Q[23:0] 110 × 32 2 Meg 64-Mbit D[31:0] Q[31:0] 111 × 36 2 Meg 72-Mbit D[35:0] Q[35:0] Note 3. For all port sizes, four to eight locations are not available for writing the data. Document Number: 001-53687 Rev. *M Page 7 of 36 CYF0018V CYF0036V CYF0072V Data Valid Signal (DVal) Data valid (DVal) is an active low signal, synchronized to RCLK and is provided to check for valid data on the output bus. When a read operation is performed, the DVal signal goes low along with output data. This helps user to capture the data without keeping track of REN to data output latency. This signal also helps when write and read operations are performed continuously at different frequencies by indicating when valid data is available at the output port Q[35:0]. case assertion latency for Full Flag is four. As the user cannot know that the FIFO is full for four clock cycles, it is possible that user continues writing data during this time. In this case, the four data words written will be stored to prevent data loss and these words have to be read back in order for full flag to get de-asserted. The minimum number of reads required to de-assert full-flag is two and the maximum number of reads required to de-assert full flag is six. The assertion and de-assertion of Full flag with associated latencies is explained in Latency Table on page 14. Write Mask and Read Skip Operation Half-Full Flag As mentioned in Architecture on page 7, enabling writes but disabling the inputs (IE HIGH) increments the write pointer without doing any write operations or altering the contents of the location. The Half-Full (HF) flag goes LOW when half of the memory array is written. HF is synchronized to WCLK. The assertion and de-assertion of Half-Full flag with associated latencies is explained in Latency Table on page 16. This feature is called Write Mask and allows user to move the write pointer without actually writing to the locations. This “write masking” ability is useful in some video applications such as Picture In Picture (PIP). Similarly, during a read operation, if the outputs are disabled by keeping the OE high, the read data does not appear on the output bus; however, the read pointer is incremented. This feature is referred to as a Read Skip Operation. Flow-through Mailbox Register This feature transfers data from input to output directly bypassing the FIFO sequence. When MB signal is asserted the data present in D[35:0] will be available at Q[35:0] after two WCLK cycles. Normal read and write operations are not allowed during flow-through mailbox operation. Before starting Flow-through mailbox operation FIFO read should be completed to make data valid DVal high in order to avoid data loss from FIFO. The width of flow-through mailbox register always corresponds to port size. Flag Operation This device provides five flag pins to indicate the condition of the FIFO. Full Flag The Full Flag (FF) operates on double word (burst length of two) boundaries and goes LOW when the device is full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN. FF is synchronized to WCLK, that is, it is exclusively updated by each rising edge of WCLK. The worst Empty Flag The Empty Flag (EF) deassertion depends on burst writes and goes LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN. EF is synchronized to RCLK, that is, it is exclusively updated by each rising edge of RCLK. The assertion and de-assertion of Empty flag with associated latencies is explained in Latency Table on page 16. Programmable Almost-Empty and Almost-Full Flags The CYF0072V includes programmable Almost-Empty and Almost-Full flags. Each flag operates on word boundaries and is programmed (see Programming Flag Offsets and Configuration Registers on page 9) a specific distance from the corresponding boundary flags (Empty or Full). (offset can range from 16 to 1023) When the FIFO contains the number of words for which the flags are programmed, the PAF or PAE is asserted, signifying that the FIFO is either almost-full or almost-empty. The default flag offset for both PAE and PAF is 127 words. These programmable flag boundaries have thresholds associated with them. Table 2 gives the assertion and de-assertion conditions for PAE & PAF flags based on these thresholds assuming default offset values. The PAF flag signal transition is caused by the rising edge of WCLK and the PAE flag transition is caused by the rising edge of RCLK. The assertion and de-assertion of these flags with associated latencies is explained in Latency Table on page 16. Table 2. Programmable Flag Assertion/De-assertion Thresholds Operation PAE offset Number of FIFO words - PAE PAF offset Number of FIFO words - PAF Assertion 127 # FIFO words <= (PAE offset + 2) i.e. # FIFO words <= 129 127 # FIFO words >= FIFO depth - (offset + 1) i.e. # FIFO words >= 2M - 128 Deassertion 127 # FIFO words > (offset) i.e. # FIFO words > 127 127 # FIFO words < FIFO depth - (offset) i.e. # FIFO words < 2M - 127 Document Number: 001-53687 Rev. *M Page 8 of 36 CYF0018V CYF0036V CYF0072V Retransmit from Mark Operation The retransmit feature is useful for transferring packets of data repeatedly. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. Initiation of a retransmit operation (using RT pin) resets the internal read pointer to a physical location of the FIFO that is marked by the user (using the MARK pin). With every valid read cycle after retransmit, data is read out starting from the marked location and the read pointer is incremented until the FIFO is empty. Data written to FIFO after initiation of a retransmit operation are also transmitted. The full depth of the FIFO can be repeatedly retransmitted. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Refer to the latency table for the associated flag update latencies after initiation of a retransmit cycle. Asserting RT initiates a retransmit operation. The retransmit feature can be used when two or more data words have been written to the FIFO. When the MARK pin is asserted, the memory location corresponding to the data present on the output bus is marked. A mark operation is mandated prior to initiating a Retransmit operation. A retransmit operation should not be initiated when reads or writes are in progress. User should wait for four RCLK cycles after disabling reads before RT is asserted to ensure that the reads are completed. On initiation of RT the ‘marked’ location becomes the new Full Boundary. If user continues to write the data after initiation of a retransmit operation, FF will be asserted when this boundary is reached i.e. FF is asserted once the write pointer reaches the marked location.This prevents overwriting and data-loss. During RT reads the full boundary remains frozen to the marked location and is released when the FIFO becomes empty. i.e. FF remains LOW until the entire FIFO is read. Full flag is released Document Number: 001-53687 Rev. *M LFF_RELEASE clocks after the EF is asserted. Full boundary is also released on a reset operation (MRS or PRS). Refer to Latency Table on page 16 for more details. Programming Flag Offsets and Configuration Registers The CYF0072V has ten 8-bit user configurable registers. These registers contain the almost-full (M) and almost-empty (N) offset values which decide when the PAF and PAE flags are asserted. These registers can be programmed in one of two ways: serial loading or parallel loading method. The loading method is selected using the SPI_SEN (Serial Enable) pin. A low on the SPI_SEN selects the serial method for writing into the registers. For serial programming, there is a separate SCLK and a Serial Input (SI). In parallel mode, a LOW on the load (LD) pin causes the write and read operation to these registers. The write and read operation happens from the first location (0x1) to the last location (0xA) in a sequence. If LD is HIGH, the writes occur to the FIFO. Register values can be read through the parallel output port regardless of the programming mode selected (serial or parallel). Register values cannot be read serially. The registers may be programmed (and reprogrammed) any time after master reset, regardless of whether serial or parallel programming is selected. Any changes to configuration registers during device operation mandates a PRS cycle to guarantee accurate flag operation. See Table 4 on page 11 and Table 5 on page 12 for access to configuration registers in serial and parallel modes. In parallel mode, the read and write operations loop back when the maximum address location of the configuration registers is reached. Simultaneous read and write operations should be avoided on the configuration registers. Any change in configuration registers will take effect after eight write clock cycles (WCLK) cycles. Page 9 of 36 CYF0018V CYF0036V CYF0072V Table 3. Configuration Registers ADDR Configuration Register Default Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] Bit [0] 0x1 Reserved 0x00 X X X X X X X X 0x2 Reserved 0x00 X X X X X X X X 0x3 Reserved 0x00 X X X X X X X X 0x4 Almost-Empty Flag generation 0x7F address - (LSB) (N) D7 D6 D5 D4 D3 D2 D1 D0 0x5 Almost-Empty Flag generation 0x00 address - (MSB) (N) X X X X X X D9 D8 0x6 Reserved 0x00 X X X X X X X X 0x7 Almost-Full Flag generation address - (LSB) (M) 0x7F D7 D6 D5 D4 D3 D2 D1 D0 0x8 Almost-Full Flag generation address - (MSB) (M) 0x00 X X X X X X D9 D8 0x9 Reserved 0x00 X X X X X X X X 0xA Fast CLK Bit Register 1XXXXXXXb Fast CLK bit X X X X X X X Document Number: 001-53687 Rev. *M Page 10 of 36 CYF0018V CYF0036V CYF0072V Table 4. Writing and Reading Configuration Registers in Parallel Mode SPI_SEN LD WEN REN WCLK RCLK SPI_SCLK 1 0 0 1 First rising edge because both LD and WEN are low X X Parallel write to first register 1 0 0 1 Second rising edge X X Parallel write to second register 1 0 0 1 Third rising edge X X Parallel write to third register 1 0 0 1 Fourth rising edge X X Parallel write to fourth register 1 0 0 1 X X 1 0 0 1 X X 1 0 0 1 X X 1 0 0 1 Tenth rising edge X X Parallel write to tenth register 1 0 0 1 Eleventh rising edge X X Parallel write to first register (roll back) 1 0 1 0 X First rising edge since both LD and REN are low X Parallel read from first register 1 0 1 0 X Second rising edge X Parallel read from second register 1 0 1 0 X Third rising edge X Parallel read from third register 1 0 1 0 X Fourth rising edge X Parallel read from fourth register 1 0 1 0 X X 1 0 1 0 X X 1 0 1 0 X X 1 0 1 0 X Tenth rising edge X Parallel read from tenth register 1 0 1 0 X Eleventh rising edge X Parallel read from first register (roll back) 1 X 1 1 X X X No operation X 1 0 X Rising edge X X Write to FIFO memory X 1 X 0 X Rising edge X Read from FIFO memory 0 0 X 1 X X X Illegal operation Document Number: 001-53687 Rev. *M Operation Page 11 of 36 CYF0018V CYF0036V CYF0072V Table 5. Writing into Configuration Registers in Serial Mode SPI_SEN LD WEN REN WCLK RCLK SCLK Operation 0 1 X X X X X 1 0 X Rising edge X X Parallel write to FIFO memory. X 1 X 0 X Rising edge X Parallel read from FIFO memory. 1 0 1 1 X X X This corresponds to parallel mode (refer to Table 4 on page 11). Rising edge Each rising of the SCLK clocks in one bit from the SI (Serial In). Any of the 10 registers can be addressed and written to, following the SPI protocol. Figure 2. Serial WRITE to Configuration Register Document Number: 001-53687 Rev. *M Page 12 of 36 CYF0018V CYF0036V CYF0072V Width Expansion Configuration The width of CYFX072V can be expanded to provide word widths greater than 36 bits. During width expansion mode, all control line inputs are common and all flags are available. Empty (Full) flags are created by ANDing the Empty (Full) flags of every FIFO; the PAE and PAF flags can be detected from any one device. This technique avoids reading data from or writing data to the FIFO that is “staggered” by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 3 demonstrates an example of 72 bit-word width by using two 36-bit word CYFX072Vs. Figure 3. Using Two CYFX072V for Width Expansion DATAIN (D) 72 36 36 READ CLOCK (RCLK) WRITE CLOCK (WCLK) READ ENABLE (REN) WRITE ENABLE (WEN) OUTPUT ENABLE(OE) PAE PAF CYFX072V CYFX072V HF EF FF FF FF EF EF 36 DATAOUT (Q) 72 36 Power Up The device becomes functional after VCC1, VCC2, VCCIO, and VREF attain minimum stable voltage required as given in Recommended DC Operating Conditions on page 15. The device can be accessed tPU time after these supplies attain the minimum required level (see Switching Characteristics on page 18). There is no specific power sequencing required for the device. Read/Write Clock Requirements For proper FIFO operation, the device must determine which of the input clocks – RCLK or WCLK – is faster. This is evaluated using counters after the MRS cycle. The device uses two 9-bit counters (one running on RCLK and other on WCLK), which count 256 cycles of read and write clocks after MRS. The clock of the counter which reaches its terminal count first is used as master clock inside the FIFO. When there is change in the relative frequency of RCLK and WCLK during normal operation of FIFO, user can specify it by using “Fast CLK bit” in the configuration register (0xA). The read and write clocks must satisfy the following requirements: “1” - indicates freq (WCLK) > freq (RCLK) ■ Both read (RCLK) and write (WCLK) clocks should be free-running. ■ The clock frequency for both clocks should be between the minimum and maximum range given in Electrical Characteristics on page 15. The result of counter evaluated frequency is available in this register bit. User can override the counter evaluated frequency for faster clock by changing this bit. ■ The WCLK to RCLK ratio should be in the range of 0.5 to 2. Document Number: 001-53687 Rev. *M “0” - indicates freq (WCLK) < freq (RCLK) Whenever there is a change in this bit value, user must wait tPLL time before issuing the next read or write to FIFO. Page 13 of 36 CYF0018V CYF0036V CYF0072V JTAG Operation CYFX072V has two devices connected internally in a JTAG chain as shown in Figure 4 Figure 4. Device Connection in a JTAG Chain TRST TM S TCK TM S TCK device1 TDI TDO TM S TRST TCK device2 TDI TDO TDI TDO Table 6 shows the IR register length and device ID Table 6. JTAG IDCODES IR Register Length 3 8 Device-1 Device-2 Device ID (HEX) “Ignore” 1E3261CF Bypass Register Length 1 1 Table 7. JTAG Instructions for Device-1 Device-1 Opcode (Binary) BYPASS 111 Table 8. JTAG Instructions for Device-2 Device-2 Opcode (HEX) EXTEST 00 HIGHZ 07 SAMPLE/PRELOAD 01 BYPASS FF IDCODE 0F Document Number: 001-53687 Rev. *M Page 14 of 36 CYF0018V CYF0036V CYF0072V Maximum Ratings Voltage applied to I/O pins ...........................–0.3 V to 3.75 V Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature (without bias) ........ –65 C to +150 C Output current into outputs (LOW) ............................. 24 mA Static discharge voltage (per MIL–STD–883, Method 3015) ......................... > 2001 V Operating Range Ambient temperature with power applied ......................................... –55 C to +125 C Range Core supply voltage 1 (VCC1) to ground potential .............................................–0.3 V to 2.5 V Ambient Temperature –40 C to +85 C Industrial Core supply voltage 2 (VCC2) to ground potential ...........................................–0.3 V to 1.65 V Latch up current ................................................ >100 mA I/O port supply voltage (VCCIO) ......................–0.3 V to 3.7 V Recommended DC Operating Conditions Parameter [4] Min Typ Max Unit VCC1 Core supply voltage 1 Description 1.70 1.80 1.90 V VCC2 Core supply voltage 2 1.425 1.5 1.575 V VREF Reference voltage (irrespective of I/O standard used) 0.7 0.75 0.8 V VCCIO I/O supply voltage, read and write banks. LVCMOS33 3.00 3.30 3.60 V LVCMOS18 1.70 1.8 1.90 V Min Typ Max Unit Electrical Characteristics Parameter ICC Description Active current Conditions VCC1 = VCC1MAX – – 300 mA VCC2 = VCC2MAX (All I/O switching, 133 MHz) – – 600 mA VCCIO = VCCIOMAX (All outputs disabled) – – 100 mA VIN = VCCIOmax to 0 V –15 – 15 µA II Input pin leakage current IOZ I/O pin leakage current VO = VCCIOmax to 0 V –15 – 15 µA CP Capacitance for TMS and TCK – – – 16 pF CPIO Capacitance for all other pins except TMS and TCK – – – 8 pF Note 4. Device operation guaranteed for a supply rate > 1 V / µs. Document Number: 001-53687 Rev. *M Page 15 of 36 CYF0018V CYF0036V CYF0072V I/O Characteristics (Over the operating range) I/O standard Nominal I/O supply voltage LVCMOS33 3.3 V LVCMOS18 1.8 V Input Voltage (V) VIL(max) Output voltage (V) VIH(min) VOL(max) 0.80 2.20 30% VCCIO 65% VCCIO Output Current (mA) VOH(min) IOL(max) IOH(max) 0.45 2.40 24 24 0.45 VCCIO – 0.45 16 16 Latency Table Latency Parameter Number of cycles Detail LFF_ASSERT Max = 4 Last data write to FF going low. LEF_ASSERT 0 Last data read to EF going low. [5] LPRS_TO_ACTIVE 32 LMAILBOX 2 Latency from write port to read port when MB = 1 (wrt WCLK). PRS deassert to normal operation. LREN_TO_DATA 4 Latency when REN is asserted low to first data output from FIFO. LREN_TO_CONFIG 4 Latency when REN is asserted along with LD to first data read from configuration registers. LWEN_TO_PAE_HI 5 [5] LWEN_TO_PAF_LO 5 [5] Write to PAF going low. LREN_TO_PAE_LO 7 [5] Read to PAE going low. Write to PAE going high. 7 [5] Read to PAF going high. LFF_DEASSERT 8 [5] Read to FF going high. LRT_TO_REN 17 First RCLK posedge after RT goes low to initiation of reads by pulling REN low. Flags update within this period after initiation of a retransmit operation. LRT_TO_DATA Max = 21 [5] First RCLK posedge after RT goes LOW to valid data on Q[35:0]. LIN Max = 26 [5] Initial latency for data read after FIFO goes empty during simultaneous read/write. LREN_TO_PAF_HI LEF_DEASSERT Max = 24 LFF_RELEASE Max = 6 [5] Write to EF going high. EF going low to FF deassert during retransmit reads. Note 5. These latency values are valid for a clock ratio of 1. Document Number: 001-53687 Rev. *M Page 16 of 36 CYF0018V CYF0036V CYF0072V Figure 5. AC Test Load Conditions 30 0.9 V (a) VCCIO = 1.8 Volt 30 (b) VCCIO = 3.3 Volt (c) All Input Pulses Document Number: 001-53687 Rev. *M Page 17 of 36 CYF0018V CYF0036V CYF0072V Switching Characteristics Parameter -133 Description Min Max Unit tPU Power-up time after all supplies reach minimum value – 2 ms tS Clock cycle frequency 3.3 V LVCMOS 24 133 MHz tS Clock cycle frequency 1.8 V LVCMOS 24 133 MHz tA Data access time – 10 ns tCLK Clock cycle time 7.5 41.67 ns tCLKH Clock high time 3.375 – ns tCLKL Clock low time 3.375 – ns tDS Data setup time 3 – ns tDH Data hold time 3 – ns tENS Enable setup time 3 – ns tENH Enable hold time 3 – ns tENS_SI Setup time for SPI_SI and SPI_SEN pins 5 – ns tENH_SI Hold time for SPI_SI and SPI_SEN pins 5 – ns tRATE_SPI Frequency of SCLK – 25 MHz tRS Reset pulse width 100 – ns tPZS Port size select to MRS seup time 25 – ns tPZH MRS to port size select hold time 25 – ns tRSF Reset to flag output time – 50 ns tPRT Retransmit pulse width 5 – RCLK cycles tOLZ Output enable to output in Low Z 4 15 ns tOE Output enable to output valid – 15 ns tOHZ Output enable to output in High Z – 15 ns tWFF Write clock to FF – 8.5 ns tREF Read clock to EF – 8.5 ns tPAF Clock to PAF flag – 17 ns tPAE Clock to PAE flag – 17 ns tHF Clock to HF flag – 17 ns tPLL Time required to synchronize PLL – 1024 cycles tRATE_JTAG JTAG TCK cycle time 100 – ns tS_JTAG Setup time for JTAG TMS,TDI 8 – ns tH_JTAG Hold time for JTAG TMS,TDI 8 – ns tCO_JTAG JTAG TCK low to TDO valid – 20 ns Document Number: 001-53687 Rev. *M Page 18 of 36 CYF0018V CYF0036V CYF0072V Switching Waveforms Figure 6. Write Cycle Timing tCLK tCLKH tCLKL WCLK tDS tDH D[35:0] tENH tENS WEN, IE NO OPERATION Figure 7. Read Cycle Timing tCLK RCLK tENS tENH REN NO OPERATION LREN_TO_DATA tA VALID DATA Q[35:0] tOLZ tOHZ OE DVal Document Number: 001-53687 Rev. *M Page 19 of 36 CYF0018V CYF0036V CYF0072V Switching Waveforms (continued) Figure 8. Reset Timing tRS MRS / PRS tRSF EF,PAE tRSF DVal, FF,PAF, HF tRSF OE=1 Q[35:0] – OE=0 Figure 9. MRS to PORTSZ[2:0] WCLK/RCLK MRS tPZS tPZH PORTSZ[2:0] Document Number: 001-53687 Rev. *M Page 20 of 36 CYF0018V CYF0036V CYF0072V Switching Waveforms (continued) Figure 10. Empty Flag Timing RCLK tREF EF EF REN REN OE OE Q[35:0] Q(Last)-3 Q(Last)-2 Q(Last)-1 Q(Last) Invalid Data DVal Figure 11. Full Flag Timing WCLK tDS D[35:0] D0 (written) D1 (written) D2 (written) D3 (not written) D4 (not written) tWFF FF WEN Document Number: 001-53687 Rev. *M Page 21 of 36 CYF0018V CYF0036V CYF0072V Switching Waveforms (continued) Figure 12. Initial Data Latency WCLK WEN D[35:0] D0 D1 D2 D3 D4 D5 D6 RCLK tA REN L IN (iNITIAL LATENCY) Q[35:0 QO Q1 Q2 Q3 Q4 Q5 Q6 DVal Figure 13. Flow-through Mailbox Operation WCLK D[35:0] REN / WEN 02 1 DO D1 2 1 3 D2 D3 D4 L MAILBOX MB Q[35:0] QO Q1 Q2 Q3 Q4 DVal0/ DVal1 DVal Document Number: 001-53687 Rev. *M Page 22 of 36 CYF0018V CYF0036V CYF0072V Switching Waveforms (continued) Figure 14. Configuration Register Write WCLK tENS WEN LD tDS D[35:0] config-reg 0 tDH config-reg 1 config-reg 2 config-reg 3 config-reg 4 config-reg 5 Figure 15. Configuration Register Read WCLK /RCLK REN LREN_TO_CONFIG tA LD Q[35:0] Reg - 1 Figure 16. Empty Flag Deassertion WCLK WEN / IE D[35:0] D0 D1 L EF_DEASSERT EF tREF RCLK REN Document Number: 001-53687 Rev. *M Page 23 of 36 CYF0018V CYF0036V CYF0072V Switching Waveforms (continued) Figure 17. Empty Flag Assertion 0 1 1 2 2 3 3 4 4 5 RCLK REN tA Q[35:0] Q LAST DVal L REN_TO_DATA EF tREF L FF_RELEASE FF Figure 18. Full Flag Assertion WCLK WEN / IE D[35:0] D 0 D 1 D x D LAST-1 D LAST NOT WRITTEN NOT WRITTEN FF Document Number: 001-53687 Rev. *M Page 24 of 36 CYF0018V CYF0036V CYF0072V Switching Waveforms (continued) Figure 19. Full Flag Deassertion 0 1 2 3 8 WCLK WEN / IE D[35:0] D LAST-5 D LAST-4 D LAST-3 D LAST-2 D LAST-1 D LAST L FF_DEASSERT FF RCLK REN Figure 20. PAE Assertion and Deassertion WCLK WEN / IE Note 6 RCLK REN L WEN_TO_PAE_HI 1 READ L REN_TO_PAE_LO PAE tPAE tPAE Note 6. Refer to Table 2 on page 8 and Latency Table on page 16 for the Programmable Flag boundaries. Document Number: 001-53687 Rev. *M Page 25 of 36 CYF0018V CYF0036V CYF0072V Switching Waveforms (continued) Figure 21. PAF Assertion and Deassertion WCLK WEN / IE Note 7 RCLK REN L WEN_TO_PAF_LO 1 READ L REN_TO_PAF_HI PAF tPAF tPAF Figure 22. HF Assertion and Deassertion WCLK WEN / IE FULL / 2 WRITE RCLK REN L WEN_TO_PAF_LO 1 READ L REN_TO_PAF_HI HF tHF tHF Note 7. Refer to Table 2 on page 8 and Latency Table on page 16 for the Programmable Flag boundaries. Document Number: 001-53687 Rev. *M Page 26 of 36 CYF0018V CYF0036V CYF0072V Switching Waveforms (continued) Figure 23. Mark RCLK tENS REN tENH MARK Q[35:0] Q (N-2) DVal Q (N-1) Q (N) Q (N+1) Q (N+2) Q (N+3) Q (N+4) Q (N+5) Q (N+6) DATA MARKED Figure 24. Retransmit RCLK REN tPRT LRT_TO_REN LRT_TO_DATA RT Q[35:0] Q (N) Q (N+1) RETRANSMIT FROM DATA MARKED DVal All Flags Document Number: 001-53687 Rev. *M FLAGS UPDATED AFTER RT Page 27 of 36 CYF0018V CYF0036V CYF0072V Ordering Information Speed (MHz) 133 Ordering Code CYF0018V33L-133BGXI Package Diagram Operating Range Package Type 51-85167 209-ball FBGA (14 × 22 × 1.76 mm) Industrial CYF0036V33L-133BGXI CYF0072V33L-133BGXI CYF0018V18L-133BGXI CYF0072V18L-133BGXI Ordering Code Definitions CY F X XXX VXX X - XXX BGXI Speed: 133 MHz I/O Standard: L = LVCMOS I/O Voltage: V18 = 1.8 V V33 = 3.3 V Density: 018 = 18M 036 = 36M 072 = 72M 0 - single-queue FIFO Cypress Document Number: 001-53687 Rev. *M Page 28 of 36 CYF0018V CYF0036V CYF0072V Package Diagram Figure 25. 209-ball FBGA (14 × 22 × 1.76 mm) BB209A Package Outline, 51-85167 51-85167 *C Document Number: 001-53687 Rev. *M Page 29 of 36 CYF0018V CYF0036V CYF0072V Acronyms Acronym Document Conventions Description Units of Measure FF Full Flag FIFO First In First Out °C degree Celsius HF Half Full MHz megahertz IE Input Enable A microampere I/O Input/Output mA milliampere FBGA Fine-Pitch Ball Grid Array mm millimeter ms millisecond ns nanosecond ohm pF picofarad V volt W watt JTAG Joint Test Action Group LSB Least Significant Bit LVCMOS Low Voltage Complementary Metal Oxide Semiconductor MB Mailbox MRS Master Reset MSB Most Significant Bit OE Output Enable PAF Programmable Almost-Full PAE Programmable Almost-Empty PRS Partial Reset RCLK Read Clock REN Read Enable RCLK Read Clock SCLK Serial Clock TCK Test Clock TDI Test Data In TDO Test Data Out TMS Test Mode Select WCLK Write Clock WEN Write Enable Document Number: 001-53687 Rev. *M Symbol Unit of Measure Page 30 of 36 CYF0018V CYF0036V CYF0072V Appendix: Silicon Errata for the 18-Mbit, 36-Mbit, and 72-Mbit Programmable FIFO This section describes the errata for the 18-Mbit, 36-Mbit, and 72-Mbit programmable FIFOs. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative or raise a technical support case at www.cypress.com/support if you have questions. Part Numbers Affected Part Number Device Characteristics CYF0018V33L-133BGXI 18-Mbit Programmable Single-Queue FIFOs (3.3-V LVCMOS) CYF0018V18L-133BGXI 18-Mbit Programmable Single-Queue FIFO (1.8-V LVCMOS) CYF0036V33L-133BGXI 36-Mbit Programmable Single-Queue FIFO (3.3-V LVCMOS) CYF0072V33L-133BGXI 72-Mbit Programmable Single-Queue FIFO (3.3-V LVCMOS) CYF0072V18L-133BGXI 72-Mbit Programmable Single-Queue FIFO (1.8-V LVCMOS) CYF2072V33L-100BGXI 72-Mbit Programmable Eight-Queue FIFO (3.3-V LVCMOS) 18-Mbit, 36-Mbit, and 72-Mbit Programmable FIFO Qualification Status Product Status: In Production 18-Mbit, 36-Mbit, and 72-Mbit Programmable FIFO Errata Summary This table defines the errata applicability to available 18-Mbit, 36-Mbit, and 72-Mbit Programmable FIFO family devices. An "X" indicates that the erratum pertains to the selected device. Note Errata items, in the following table, are hyperlinked. Click on any item entry to jump to its description. Items 1. Retransmit Issue Part Numbers Silicon Revision CYF0018V CYF0036V CYF0072V CYF2072V X Fix Status Fix in progress. Fixed devices to be available from February 04, 2013 1. Retransmit Issue ■ Problem Definition Flag Failure during Retransmit cycles: Flags (PAE, HF, PAF, and FF) are not updated during a retransmit cycle. These flags do not recover on completion of retransmit cycles. The functionality of Empty Flag (EF) and Data Valid signal (DVal) remain intact throughout device operation. ■ Parameters Affected Because flags (PAE, HF, PAF, and FF) are not updated during a retransmit cycle, their associated latencies and timing parameters are not applicable. ■ Trigger Condition Initiation of a retransmit cycle using RT signal. ■ Scope of Impact On initiation of a retransmit cycle, flags (PAE, HF, PAF, and FF) may not accurately reflect FIFO status. Customer applications relying on these flags to keep track of number of words in the FIFO during retransmit may observe errors because these flags are not updated. The failure mandates a reset cycle (Partial Reset for Single queue and Master Reset for Multi queue devices) to ensure flag recovery after a retransmit cycle, that is, to restore flag functionality and resume normal FIFO operations after completion of retransmit cycles. Document Number: 001-53687 Rev. *M Page 31 of 36 CYF0018V CYF0036V CYF0072V ■ Workaround During retransmit cycles, there is no workaround to restore PAE, HF, PAF, and FF functionalities. After completion of retransmit cycles, a reset cycle (Partial Reset for Single queue and Master Reset for Multi queue devices) can be performed to restore PAE, HF, PAF, and FF functionalities for normal FIFO operation. ■ Fix Status The fix for the retransmit issue is in progress. In devices with the design fix, the intended flag functionality will be restored during retransmit cycles. Reset will not be mandatory after a retransmit cycle to resume normal FIFO operation. Fixed devices will be available from February 04, 2013. Document Number: 001-53687 Rev. *M Page 32 of 36 CYF0018V CYF0036V CYF0072V Document History Page Document Title: CYF0018V/CYF0036V/CYF0072V, 18/36/72-Mbit Programmable FIFOs Document Number: 001-53687 Revision ECN Orig. of Change Submission Date Description of Change ** 2711566 VKN/PYRS 05/27/09 *A 2725088 NXR 06/26/2009 Included pinout, AC and DC specs, timing diagrams and package diagram *B 2839536 NXR 01/28/2010 Changed Balls B5, D5, F6, K1, K2, K4, K8 and U2 from NC to DNU, Balls C5, C7, G6, H6, J6, L6, M6, N6, T5, T7 from NC to VCC1, Balls K9, K10, K11 from NC to VCCIOR, Ball W9 from NC to Vref in pin configuration table Swapped Voltage range of VSS1 and VSS2 Updated ICC spec Removed TSKEW parameter Added Ordering Information table Added Part Numbering Nomenclature. Changed title to CYF0018V/CYF0036V/CYF0072V/CYFX144VXXX, 18/36/72-Mbit Programmable FIFOs. *C 2884377 HKV 02/25/2010 Post to external web. *D 2963225 AJU/HPV 06/28/2010 Changed frequency of operation from 250 MHz to 150 MHz Removed Depth Expansion feature and changed associated pin functionality Removed Independent Port size selectability feature Added Data Valid (DVal) signal feature Updated Logic Block Diagram to reflect above changes. Pinout changes: Balls V5, V8, A7, B7, D7, and C6 renamed DNU Ball U1 changed from RXO to DVal Ball V2 changed from WXO/HF to HF Ball A5, A6, B6 changed from WPORTSZ to PORTSZ Ball A9 changed from RT/FL to RT Renamed pwr as POWER, gnd as GND Added Table 4 Table 6 – LD changed to ‘1’ for serial writes Updated Electrical Characteristics and I/O Characteristics Switching Characteristics Table: Renamed tPC as tPU Min frequency changed from 110MH to 24MHz Changed tCLKH and tCLKL to 3.15 ns Changed All setup and hold times to 3 ns Changed tRSF to 50 ns Removed tRSR Changed All clock-to-flag timing to min = 8 ns and max = 14 ns TPLL changed to 6 ms Changed all OE-related parameters to 15 ns Scaled ICC for reduced frequency Updated all waveforms Added the following table: “Word Size Selection”. Added the sections JTAG Operation, and Latency Table Added Acronyms. *E 2994379 AJU 07/26/2010 Updated Ordering Information *F 3101023 SIVS 12/03/2010 Added supply-wise current consumption data in Electrical Characteristics. Changed initial latency LIN from 34 to 26 and added initial latency LIN for 110 MHz part in Latency Table. Added 110 MHz part information in JTAG Operation Added details for the 110 MHz part in Switching Characteristics. Added details for the 110 MHz part in Ordering Information. *G 3129722 HKV 01/06/2011 Post to external web. Document Number: 001-53687 Rev. *M New data sheet Page 33 of 36 CYF0018V CYF0036V CYF0072V Document History Page (continued) Document Title: CYF0018V/CYF0036V/CYF0072V, 18/36/72-Mbit Programmable FIFOs Document Number: 001-53687 Revision ECN Orig. of Change Submission Date *H 3197271 SIVS 03/31/2011 Removed 144 Mbit parts from the data sheet Removed multi-queue information from data sheet Removed 2.5 V and 1.5 V options Removed HSTL I/II I/O standard Added clock ratio requirement between RCLK and WCLK Removed redundant Xs from part number to improve readability Removed tie to GND option on DNU pins in pin description Added information on Flag operations to add clarity Added explanation for flow-through mailbox operation Added details on active pins in various port sizes in Table 1. Added Configuration register write to normal operation latency details. Changed configuration register definitions and default values Changed number of unusable locations to four to eight Added JTAG related operation Added latch-up current parameter in maximum operating conditions. Removed 2.5 V and 1.5 V options from DC operating condition table 6. Removed 110 MHz part details and added Cpio parameter in table 7. Removed 2.5 V and 1.5 V options from Table 8. Added latency parameters in Table 9. changed VOL(max) value of LVCMOS33 in table11 Removed 110 MHz part detail from switching characteristics Added timing waveform to improve clarity. Modified ordering information and definition. *I 3388143 AJU 09/29/2011 Updated Pin Diagram for CYF0XXXVXXL [1] (Added Note 2 and referred the same note in DNU in ball U6). Updated Programming Flag Offsets and Configuration Registers (Updated Table 4 (WCLK column in first row)). Updated Recommended DC Operating Conditions (Added Note 4 and referred the same note in Parameter column). Updated Latency Table (Changed Details for the parameters LWEN_TO_PAE_HI and LREN_TO_PAE_LO). Updated Switching Waveforms (Removed the clock cycle numbers in Figure 12, Figure 13, Figure 17, and Figure 19). Updated Package Diagram. Updated in new template. *J 3652368 ADMU 08/16/2012 Updated Pin Diagram for CYF0XXXVXXL [1] (Updated Figure 1 on page 4 (W9 ball marked as DNU)). Added Figure 5 (Test Load Conditions). Updated Switching Characteristics (Changed minimum values of tS_JTAG, tH_JTAG parameters from 5 ns to 8 ns, changed maximum value of tCO_JTAG parameter from 10 ns to 20 ns). *K 3735896 ADMU 09/07/2012 Updated package diagram 51-85167 to *C Updated “Output current into outputs (LOW)” parameter under Maximum Ratings section from 20 mA to 24 mA. Document Number: 001-53687 Rev. *M Description of Change Page 34 of 36 CYF0018V CYF0036V CYF0072V Document History Page (continued) Document Title: CYF0018V/CYF0036V/CYF0072V, 18/36/72-Mbit Programmable FIFOs Document Number: 001-53687 Revision ECN Orig. of Change Submission Date *L 3940217 ADMU 03/22/2013 Description of Change Updated Features. Updated Functional Description. Updated Logic Block Diagram. Updated Pin Diagram for CYF0XXXVXXL [1]: Added Note 1 and referred the same note in Figure 1. Updated Pin Definitions. Updated Architecture: Updated Reset Logic, Data Valid Signal (DVal), Flag Operation, Retransmit from Mark Operation, Programming Flag Offsets and Configuration Registers, Read/Write Clock Requirements. Added Table 2. Updated Latency Table. Updated Switching Waveforms: Updated Figure 12, Figure 13, Figure 17, Figure 19, Figure 20, Figure 21, Figure 22, Figure 24. Added Note 6 and referred the same note in WEN / IE in Figure 20. Added Note 7 and referred the same note in WEN / IE in Figure 21. Updated Ordering Information (Updated part numbers). *M 3997615 ADMU Document Number: 001-53687 Rev. *M 05/11/2013 Added Appendix: Silicon Errata for the 18-Mbit, 36-Mbit, and 72-Mbit Programmable FIFO. Page 35 of 36 CYF0018V CYF0036V CYF0072V Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2009-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-53687 Rev. *M Revised May 11, 2013 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 36 of 36