CYF0018V
CYF0036V
CYF0072V
18/36/72-Mbit Programmable FIFOs
8/36/72-Mbit Programmable FIFOs
Features
Functional Description
■
Memory organization
❐ Industry’s largest first in first out (FIFO) memory densities:
18-Mbit, 36-Mbit, and 72-Mbit
❐ Selectable memory organization: × 9, × 12, × 16, × 18, × 20,
× 24, × 32, × 36
■
Up to 133-MHz clock operation
■
Unidirectional operation
■
Independent read and write ports
❐ Supports simultaneous read and write operations
❐ Reads and writes operate on independent clocks, upto a
maximum ratio of two, enabling data buffering across clock
domains.
❐ Supports multiple I/O voltage standard: low voltage
complementary metal oxide semiconductor (LVCMOS) 3.3 V
and 1.8 V voltage standards.
The Cypress programmable FIFO family offers the industry’s
highest-density programmable FIFO memory device. It has
independent read and write ports, which can be clocked up to
133 MHz. User can configure input and output bus sizes. The
maximum bus size of 36 bits enables a maximum data
throughput of 4.8 Gbps. The user-programmable registers
enable user to configure the device operation as desired. The
device also offers a simple and easy-to-use interface to reduce
implementation and debugging efforts, improve time-to-market,
and reduce engineering costs. This makes it an ideal memory
choice for a wide range of applications including multiprocessor
interfaces, video and image processing, networking and
telecommunications, high-speed data acquisition, or any system
that needs buffering at high speeds across different clock
domains.
■
Input and output enable control for write mask and read skip
operations
■
Mark and retransmit: resets read pointer to user marked
position
■
Empty, full, half-full, and programmable almost-empty and
almost-full status flags with configured offsets
■
Flow-through mailbox register to send data from input to output
port, bypassing the FIFO sequence
■
Configure programmable flags and registers through serial or
parallel modes
■
Separate serial clock (SCLK) input for serial programming
■
Master reset to clear entire FIFO
■
Partial reset to clear data but retain programmable settings
■
Joint test action group (JTAG) port provided for boundary scan
function
■
Industrial temperature range: –40 °C to +85 °C
Cypress Semiconductor Corporation
Document Number: 001-53687 Rev. *Q
•
As implied by the name, the functionality of the FIFO is such that
the data is read out of the read port in the same sequence in
which it was written into the write port. If writes and inputs are
enabled (WEN & IE), data on the write port gets written into the
device at the rising edge of write clock. Enabling reads and
outputs (REN & OE) fetches data on the read port at every rising
edge of read clock. Both reads and writes can occur
simultaneously at different speeds provided the ratio between
read and write clock is in the range of 0.5 to 2. Appropriate flags
are set whenever the FIFO is empty, almost-empty, half-full,
almost-full or full.
The device also supports mark and retransmit of data, and a
flow-through mailbox register.
All product features and specs are common to all densities
(CYF0072V, CYF0036V, and CYF0018V). All descriptions are
given assuming the 72Mbit (CYF0072V) device is operated in
× 36 mode. They are valid for other densities (CYF0036V, and
CYF0018V) and all port sizes × 9, × 12, × 16, × 18, × 20, × 24
and × 32 unless otherwise specified. The only difference will be
in the input and output bus width. Table 1 on page 7 shows the
part of bus with valid data from D[35:0] and Q[35:0] in × 9, × 12,
× 16, × 18, × 20, × 24, × 32 and × 36 modes.
For a complete list of related documentation, click here.
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 28, 2016
CYF0018V
CYF0036V
CYF0072V
Logic Block Diagram
D[35:0]
IE
WEN
WCLK
LD
INPUT
REGISTER
SPI_SEN SPI_SCLK
CONFIGURATION
REGISTERS/MAILBOX
SPI_SI
MB
WRITE
CONTROL LOGIC
FF
PAF
WRITE POINTER
FLAG LOGIC
EF
PAE
Memory Array
MRS
PRS
RESET POINTER
DVal
HF
18 Mbit
36 Mbit
72 Mbit
READ POINTER
TCK
TMS
JTAG CONTROL
READ CONTROL
LOGIC
TDO
MARK, RT
TDI
OUTPUT
REGISTER
RCLK
REN
OE
MEMORY LOGIC
ORGANIZATION
Q[35:0]
PORTSZ[2:0]
Document Number: 001-53687 Rev. *Q
Page 2 of 35
CYF0018V
CYF0036V
CYF0072V
Contents
Pin Diagram for CYF0XXXVXXL [1] ................................. 4
Pin Definitions .................................................................. 5
Architecture ...................................................................... 7
Reset Logic ................................................................. 7
Selecting Word Sizes .................................................. 7
Memory Organization
for Different Port Sizes ................................................ 7
Data Valid Signal (DVal) .............................................. 8
Write Mask and Read Skip Operation ......................... 8
Flow-through Mailbox Register .................................... 8
Flag Operation ............................................................. 8
Retransmit from Mark Operation ................................. 9
Programming Flag Offsets
and Configuration Registers ........................................ 9
Width Expansion Configuration ................................. 13
Power Up ................................................................... 13
Read/Write Clock Requirements ............................... 13
JTAG Operation ........................................................ 14
Test Access Port ....................................................... 14
Tap Registers ............................................................ 14
JTAG ID Codes ......................................................... 15
OPCODES Supported ............................................... 15
JTAG Instructions ...................................................... 15
Document Number: 001-53687 Rev. *Q
Instruction Update and Bypass ................................. 15
TAP Controller State Diagram ................................... 15
Maximum Ratings ........................................................... 16
Operating Range ............................................................. 16
Recommended DC Operating Conditions .................... 16
Electrical Characteristics ............................................... 16
I/O Characteristics .......................................................... 17
Latency Table .................................................................. 17
Switching Characteristics .............................................. 19
Switching Waveforms .................................................... 20
Ordering Information ...................................................... 29
Ordering Code Definitions ......................................... 29
Package Diagram ............................................................ 30
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 35
Worldwide Sales and Design Support ....................... 35
Products .................................................................... 35
PSoC® Solutions ...................................................... 35
Cypress Developer Community ................................. 35
Technical Support ..................................................... 35
Page 3 of 35
CYF0018V
CYF0036V
CYF0072V
Pin Diagram for CYF0XXXVXXL [1]
Figure 1. 209-ball FBGA pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
A
FF
D0
D1
DNU
PORTSZ0
PORTSZ1
DNU
DNU
RT
Q0
Q1
B
EF
D2
D3
DNU
DNU
PORTSZ2
DNU
DNU
REN
Q2
Q3
C
D4
D5
WEN
DNU
VCC1
DNU
VCC1
DNU
RCLK
Q4
Q5
D
D6
D7
VSS
VCC1
DNU
LD
DNU
VCC1
Vss
Q6
Q7
E
D8
D9
VCC2
VCC2
VCCIO
VCCIO
VCCIO
VCC2
VCC2
Q8
Q9
F
D10
D11
VSS
VSS
VSS
DNU
VSS
VSS
VSS
Q10
Q11
G
D12
D13
VCC2
VCC2
VCCIO
VCC1
VCCIO
VCC2
VCC2
Q12
Q13
H
D14
D15
VSS
VSS
VSS
VCC1
VSS
VSS
VSS
Q14
Q15
J
D16
D17
VCC2
VCC2
VCCIO
VCC1
VCCIO
VCC2
VCC2
Q16
Q17
K
DNU
DNU
WCLK
DNU
VSS
IE
VSS
DNU
VCCIO
VCCIO
VCCIO
L
D18
D19
VCC2
VCC2
VCCIO
VCC1
VCCIO
VCC2
VCC2
Q18
Q19
M
D20
D21
VSS
VSS
VSS
VCC1
VSS
VSS
VSS
Q20
Q21
N
D22
D23
VCC2
VCC2
VCCIO
VCC1
VCCIO
VCC2
VCC2
Q22
Q23
P
D24
D25
VSS
VSS
VSS
SPI_SEN
VSS
VSS
VSS
Q24
Q25
R
D26
D27
VCC2
VCC2
VCCIO
VCCIO
VCCIO
VCC2
VCC2
Q26
Q27
T
D28
D29
VSS
VCC1
VCC1
SPI_SI
VCC1
VCC1
VSS
Q28
Q29
[2]
SPI_SCLK
VREF
OE
Q30
Q31
U
DVal
DNU
D30
D31
PRS
DNU
V
PAF
PAE
D32
D33
DNU
MRS
MB
DNU
MARK
Q32
Q33
W
TDO
HF
D34
D35
TDI
NC
TMS
TCK
DNU
Q34
Q35
Notes
1. Pin Diagram for 18-Mbit, 36-Mbit & 72-Mbit; 1.8V & 3.3V IO voltage options.
2. This pin should be tied to VSS preferably or can be left floating to ensure normal operation.
Document Number: 001-53687 Rev. *Q
Page 4 of 35
CYF0018V
CYF0036V
CYF0072V
Pin Definitions
Pin Name
I/O
Pin Description
MRS
Input
Master reset: MRS initializes the internal read and write pointers to zero, resets all flags and sets the
output register to all zeroes. During Master Reset, the configuration registers are set to default values.
PRS
Input
Partial reset: PRS initializes the internal read and write pointers to zero, resets all flags and sets the
output register to all zeroes. During Partial Reset, the configuration register settings are retained.
PORTSZ [2:0]
Input
Port word size select: Port word width select pins (common for read and write ports).
WCLK
Input
Write clock: The rising edge clocks data into the FIFO when writes are enabled (WEN asserted). Data
is written into the FIFO memory when LD is high and into configuration registers when LD is low.
LD
Input
Load: When LD is LOW, D[7:0] (Q[7:0]) are written (read) into (from) the configuration registers. When
LD is HIGH, D[35:0] (Q[35:0]) are written (read) into (from) the FIFO memory.
WEN
Input
Write enable: Control signal to enable writes to the device. When WEN is low data present on the inputs
is written to the FIFO memory or configuration registers on every rising edge of WCLK.
IE
Input
Input enable: IE is the data input enable signal that controls the enabling and disabling of the 36-bit data
input pins. If it is enabled, data on the D[35:0] pins is written into the FIFO. The internal write address
pointer is always incremented at rising edge of WCLK if WEN is enabled, regardless of the IE level. This
is used for 'write masking' or incrementing the write pointer without writing into a location.
D[35:0]
Input
Data inputs: Data inputs for a 36-bit bus.
RCLK
Input
Read clock: The rising edge initiates a read from the FIFO when reads are enabled (REN asserted).
Data is read from the FIFO memory when LD is high & from the configuration registers if LD is low.
REN
Input
Read enable: Control signal to enable reads from the device. When REN is low data is read from the
FIFO memory or configuration registers on every rising edge of RCLK.
OE
Input
Output enable: When OE is LOW, FIFO data outputs are enabled; when OE is HIGH, the FIFO’s outputs
are in High Z (high impedance) state.
Q[35:0]
Output
Data outputs: Data outputs for a 36-bit bus.
DVal
Output
Data valid: Active low data valid signal to indicate valid data on Q[35:0].
MARK
Input
Mark for retransmit: When this pin is asserted the memory location corresponding to the data present
on the output bus is marked. Any subsequent retransmit operation resets the read pointer to this location.
RT
Input
Retransmit: A HIGH pulse on RT resets the internal read pointer to a physical location of the FIFO which
is marked by the user (using MARK pin). With every valid read cycle after retransmit, previously accessed
data is read until the FIFO is empty.
MB
Input
Mailbox: When asserted the reads and writes happen to flow-through mailbox register.
EF
Output
Empty flag: When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
PAE
Output
Programmable almost-empty: When PAE is LOW, the FIFO is almost empty based on the almost-empty
offset value programmed into the FIFO. It is synchronized to RCLK.
HF
Output
Half-full flag: When HF is LOW, half of the FIFO is full. HF is synchronized to WCLK.
PAF
Output
Programmable almost-full: When PAF is LOW, the FIFO is almost full based on the almost-full offset
value programmed into the FIFO. It is synchronized to WCLK.
FF
Output
Full flag: When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
SPI_SCLK
Input
Serial clock: A rising edge on SPI_SCLK clocks the serial data present on the SPI_SI input into the offset
registers if SPI_SEN is enabled.
SPI_SI
Input
Serial input: Serial input data in SPI mode.
SPI_SEN
Input
Serial enable: Enables serial loading of programmable flag offsets and configuration registers.
TCK
Input
Test clock (TCK) pin for JTAG.
TMS
Input
Test mode select (TMS) pin for JTAG.
Document Number: 001-53687 Rev. *Q
Page 5 of 35
CYF0018V
CYF0036V
CYF0072V
Pin Definitions (continued)
Pin Name
I/O
TDI
Input
TDO
Output
VREF
Pin Description
Test data in (TDI) pin for JTAG.
Test data out (TDO) pin for JTAG.
Input
Reference voltage: Reference voltage (regardless of I/O standard used)
Reference
VCC1
Power
Supply
Core voltage supply 1: 1.8 V supply voltage
VCC2
Power
Supply
Core voltage supply 2: 1.5 V supply voltage
VCCIO
Power
Supply
Supply for I/Os
VSS
Ground
Ground
DNU
–
Do not use: These pins need to be left floating.
Document Number: 001-53687 Rev. *Q
Page 6 of 35
CYF0018V
CYF0036V
CYF0072V
Architecture
Reset Logic
The CYF0072V, CYF0036V, and CYF0018V are memory arrays
of 72-Mbit, 36-Mbit, and 18-Mbit respectively. The memory
organization is user configurable and word sizes can be selected
as × 9, × 12, × 16, × 18, × 20, × 24, × 32, or × 36. The logic blocks
to implement the FIFO functionality and the associated features
are built around these memory arrays.
The FIFO can be reset in two ways: Master Reset (MRS) and
Partial Reset (PRS). The MRS initializes the read and write
pointers to zero and sets the output register to all zeroes. It also
resets all flags & the configuration registers to their default
values. The word size is configured through pins; values of the
three PORTSZ pins are latched during MRS. A Master Reset is
required after power-up before accessing the FIFO.
The input and output data buses have a maximum width of
36 bits. The input data bus goes to an input register and the data
flow from the input register to the memory is controlled by the
write control logic. The inputs to the write logic block are WCLK,
WEN and IE. When the writes are enabled through WEN and if
the inputs are enabled by IE, then the data on the input bus is
written into the memory array at the rising edge of WCLK. This
also increments the write pointer. Enabling writes but disabling
the data input pins through IE only increments the write pointer
without doing any writes or altering the contents of the memory
location.
Similarly, the output register is connected to the data output bus.
Transfer of contents from the memory to the output register is
controlled by the read control logic. The inputs to the read control
logic include RCLK, REN, OE, RT and MARK. When reads are
enabled by REN and outputs are enabled using OE, the data
from the memory pointed by the read pointer is transferred to the
output data bus at the rising edge of RCLK along with active low
DVal. If the outputs are disabled but the reads enabled, the
outputs are in high impedance state, but internally the read
pointer is incremented.
During write operation, the number of writes performed is always
an even number (i.e., minimum write burst length is two and
number of writes always a multiple of two). Whereas during read
operation, the number of reads performed can be even or odd
(i.e., minimum read burst length is one).
PRS resets the read pointer, write pointer and mark location to
the first physical location in the memory array. It also resets all
flags to their default values. PRS does not affect the
programmed configuration register values. Any changes to
configuration registers during device operation mandates a PRS
cycle to guarantee accurate flag operation.
Selecting Word Sizes
The word sizes are configured based on the logic levels on the
PORTSZ pins during the master reset (MRS) cycle only (latched
on low to high edge). The port size cannot be changed during
normal mode of operation and these pins are ignored. Table 1.
explains the pins of D[35:0] and Q[35:0] that will have valid data
in modes where the word size is less than × 36. If word size is
less than × 36, the unused output pins are tri-stated by the device
and unused input pins will be ignored by the internal logic. The
pins with valid data input D[N:0] and output Q[N:0] is given in
Table 1.
Memory Organization for Different Port Sizes
The 72-Mbit memory has different organization for different port
sizes. Table 1 shows the depth of the FIFO for all port sizes.
Note that for all port sizes, four to eight locations are not available
for writing the data and are used to safeguard against false
synchronization of empty and full flags.
The MARK signal is used to ‘mark’ the location from which data
is retransmitted when requested and RT is asserted to retransmit
the data from the marked location.
Table 1. Word Size Selection
PORTSZ[2:0] Word Size
FIFO Depth [3]
Memory Size [3] Active Input Data Pins D[N:0] Active Output Data Pins Q[N:0]
000
×9
8 Meg
72-Mbit
D[8:0]
Q[8:0]
001
× 12
4 Meg
48-Mbit
D[11:0]
Q[11:0]
010
× 16
4 Meg
64-Mbit
D[15:0]
Q[15:0]
011
× 18
4 Meg
72-Mbit
D[17:0]
Q[17:0]
100
× 20
2 Meg
40-Mbit
D[19:0]
Q[19:0]
101
× 24
2 Meg
48-Mbit
D[23:0]
Q[23:0]
110
× 32
2 Meg
64-Mbit
D[31:0]
Q[31:0]
111
× 36
2 Meg
72-Mbit
D[35:0]
Q[35:0]
Note
3. For all port sizes, four to eight locations are not available for writing the data.
Document Number: 001-53687 Rev. *Q
Page 7 of 35
CYF0018V
CYF0036V
CYF0072V
Data Valid Signal (DVal)
Data valid (DVal) is an active low signal, synchronized to RCLK
and is provided to check for valid data on the output bus. When
a read operation is performed, the DVal signal goes low along
with output data. This helps user to capture the data without
keeping track of REN to data output latency. This signal also
helps when write and read operations are performed
continuously at different frequencies by indicating when valid
data is available at the output port Q[35:0].
case assertion latency for Full Flag is four. As the user cannot
know that the FIFO is full for four clock cycles, it is possible that
user continues writing data during this time. In this case, the four
data words written will be stored to prevent data loss and these
words have to be read back in order for full flag to get
de-asserted. The minimum number of reads required to
de-assert full-flag is two and the maximum number of reads
required to de-assert full flag is six. The assertion and
de-assertion of Full flag with associated latencies is explained in
Latency Table on page 14.
Write Mask and Read Skip Operation
Half-Full Flag
As mentioned in Architecture on page 7, enabling writes but
disabling the inputs (IE HIGH) increments the write pointer
without doing any write operations or altering the contents of the
location.
The Half-Full (HF) flag goes LOW when half of the memory array
is written. HF is synchronized to WCLK. The assertion and
de-assertion of Half-Full flag with associated latencies is
explained in Latency Table on page 17.
This feature is called Write Mask and allows user to move the
write pointer without actually writing to the locations. This “write
masking” ability is useful in some video applications such as
Picture In Picture (PIP).
Similarly, during a read operation, if the outputs are disabled by
keeping the OE high, the read data does not appear on the
output bus; however, the read pointer is incremented. This
feature is referred to as a Read Skip Operation.
Flow-through Mailbox Register
This feature transfers data from input to output directly bypassing
the FIFO sequence. When MB signal is asserted the data
present in D[35:0] will be available at Q[35:0] after two WCLK
cycles. Normal read and write operations are not allowed during
flow-through mailbox operation. Before starting Flow-through
mailbox operation FIFO read should be completed to make data
valid DVal high in order to avoid data loss from FIFO. The width
of flow-through mailbox register always corresponds to port size.
Flag Operation
This device provides five flag pins to indicate the condition of the
FIFO.
Full Flag
The Full Flag (FF) operates on double word (burst length of two)
boundaries and goes LOW when the device is full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, that is, it is
exclusively updated by each rising edge of WCLK. The worst
Empty Flag
The Empty Flag (EF) deassertion depends on burst writes and
goes LOW when the device is empty. Read operations are
inhibited whenever EF is LOW, regardless of the state of REN.
EF is synchronized to RCLK, that is, it is exclusively updated by
each rising edge of RCLK. The assertion and de-assertion of
Empty flag with associated latencies is explained in Latency
Table on page 17.
Programmable Almost-Empty and Almost-Full Flags
The CYF0072V includes programmable Almost-Empty and
Almost-Full flags. Each flag operates on word boundaries and is
programmed (see Programming Flag Offsets and Configuration
Registers on page 9) a specific distance from the corresponding
boundary flags (Empty or Full). (offset can range from 16 to
1023) When the FIFO contains the number of words for which
the flags are programmed, the PAF or PAE is asserted, signifying
that the FIFO is either almost-full or almost-empty. The default
flag offset for both PAE and PAF is 127 words. These programmable flag boundaries have thresholds associated with them.
Table 2 gives the assertion and de-assertion conditions for PAE
& PAF flags based on these thresholds assuming default offset
values.
The PAF flag signal transition is caused by the rising edge of
WCLK and the PAE flag transition is caused by the rising edge
of RCLK. The assertion and de-assertion of these flags with
associated latencies is explained in Latency Table on page 17.
Table 2. Programmable Flag Assertion/De-assertion Thresholds
Operation
PAE offset
Number of FIFO words - PAE
PAF offset
Number of FIFO words - PAF
Assertion
127
# FIFO words <= (PAE offset + 2)
i.e. # FIFO words <= 129
127
# FIFO words >= FIFO depth - (offset + 1)
i.e. # FIFO words >= 2M - 128
Deassertion
127
# FIFO words > (offset)
i.e. # FIFO words > 127
127
# FIFO words < FIFO depth - (offset)
i.e. # FIFO words < 2M - 127
Document Number: 001-53687 Rev. *Q
Page 8 of 35
CYF0018V
CYF0036V
CYF0072V
Retransmit from Mark Operation
The retransmit feature is useful for transferring packets of data
repeatedly. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. Initiation of a
retransmit operation (using RT pin) resets the internal read
pointer to a physical location of the FIFO that is marked by the
user (using the MARK pin). With every valid read cycle after
retransmit, data is read out starting from the marked location and
the read pointer is incremented until the FIFO is empty. Data
written to FIFO after initiation of a retransmit operation are also
transmitted. The full depth of the FIFO can be repeatedly
retransmitted.
Flags are governed by the relative locations of the read and write
pointers and are updated during a retransmit cycle. Refer to the
latency table for the associated flag update latencies after
initiation of a retransmit cycle.
Asserting RT initiates a retransmit operation. The retransmit
feature can be used when two or more data words have been
written to the FIFO. When the MARK pin is asserted, the memory
location corresponding to the data present on the output bus is
marked. A mark operation is mandated prior to initiating a
Retransmit operation.
A retransmit operation should not be initiated when reads or
writes are in progress. User should wait for four RCLK cycles
after disabling reads before RT is asserted to ensure that the
reads are completed.
On initiation of RT the ‘marked’ location becomes the new Full
Boundary. If user continues to write the data after initiation of a
retransmit operation, FF will be asserted when this boundary is
reached i.e. FF is asserted once the write pointer reaches the
marked location.This prevents overwriting and data-loss. During
RT reads the full boundary remains frozen to the marked location
and is released when the FIFO becomes empty. i.e. FF remains
LOW until the entire FIFO is read. Full flag is released
Document Number: 001-53687 Rev. *Q
LFF_RELEASE clocks after the EF is asserted. Full boundary is
also released on a reset operation (MRS or PRS).
Refer to Latency Table on page 17 for more details.
Programming Flag Offsets and Configuration
Registers
The CYF0072V has ten 8-bit user configurable registers. These
registers contain the almost-full (M) and almost-empty (N) offset
values which decide when the PAF and PAE flags are asserted.
These registers can be programmed in one of two ways: serial
loading or parallel loading method. The loading method is
selected using the SPI_SEN (Serial Enable) pin. A low on the
SPI_SEN selects the serial method for writing into the registers.
For serial programming, there is a separate SCLK and a Serial
Input (SI). In parallel mode, a LOW on the load (LD) pin causes
the write and read operation to these registers. The write and
read operation happens from the first location (0x1) to the last
location (0xA) in a sequence. If LD is HIGH, the writes occur to
the FIFO.
Register values can be read through the parallel output port
regardless of the programming mode selected (serial or parallel).
Register values cannot be read serially. The registers may be
programmed (and reprogrammed) any time after master reset,
regardless of whether serial or parallel programming is selected.
Any changes to configuration registers during device operation
mandates a PRS cycle to guarantee accurate flag operation.
See Table 4 on page 11 and Table 5 on page 12 for access to
configuration registers in serial and parallel modes.
In parallel mode, the read and write operations loop back when
the maximum address location of the configuration registers is
reached. Simultaneous read and write operations should be
avoided on the configuration registers. Any change in
configuration registers will take effect after eight write clock
cycles (WCLK) cycles.
Page 9 of 35
CYF0018V
CYF0036V
CYF0072V
Table 3. Configuration Registers
ADDR
Configuration Register
Default
Bit [7]
Bit [6]
Bit [5]
Bit [4]
Bit [3]
Bit [2]
Bit [1]
Bit [0]
0x1
Reserved
0x00
X
X
X
X
X
X
X
X
0x2
Reserved
0x00
X
X
X
X
X
X
X
X
0x3
Reserved
0x00
X
X
X
X
X
X
X
X
0x4
Almost-Empty Flag generation 0x7F
address - (LSB) (N)
D7
D6
D5
D4
D3
D2
D1
D0
0x5
Almost-Empty Flag generation 0x00
address - (MSB) (N)
X
X
X
X
X
X
D9
D8
0x6
Reserved
0x00
X
X
X
X
X
X
X
X
0x7
Almost-Full Flag generation
address - (LSB) (M)
0x7F
D7
D6
D5
D4
D3
D2
D1
D0
0x8
Almost-Full Flag generation
address - (MSB) (M)
0x00
X
X
X
X
X
X
D9
D8
0x9
Reserved
0x00
X
X
X
X
X
X
X
X
0xA
Fast CLK Bit Register
1XXXXXXXb Fast CLK
bit
X
X
X
X
X
X
X
Document Number: 001-53687 Rev. *Q
Page 10 of 35
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Table 4. Writing and Reading Configuration Registers in Parallel Mode
SPI_SEN
LD
WEN
REN
WCLK
RCLK
SPI_SCLK
1
0
0
1
First rising edge
because both LD and
WEN are low
X
X
Parallel write to first register
1
0
0
1
Second rising edge
X
X
Parallel write to second register
1
0
0
1
Third rising edge
X
X
Parallel write to third register
1
0
0
1
Fourth rising edge
X
X
Parallel write to fourth register
1
0
0
1
X
X
1
0
0
1
X
X
1
0
0
1
X
X
1
0
0
1
Tenth rising edge
X
X
Parallel write to tenth register
1
0
0
1
Eleventh rising edge
X
X
Parallel write to first register
(roll back)
1
0
1
0
X
First rising edge since
both LD and REN are
low
X
Parallel read from first register
1
0
1
0
X
Second rising edge
X
Parallel read from second
register
1
0
1
0
X
Third rising edge
X
Parallel read from third register
1
0
1
0
X
Fourth rising edge
X
Parallel read from fourth
register
1
0
1
0
X
X
1
0
1
0
X
X
1
0
1
0
X
X
1
0
1
0
X
Tenth rising edge
X
Parallel read from tenth
register
1
0
1
0
X
Eleventh rising edge
X
Parallel read from first register
(roll back)
1
X
1
1
X
X
X
No operation
X
1
0
X
Rising edge
X
X
Write to FIFO memory
X
1
X
0
X
Rising edge
X
Read from FIFO memory
0
0
X
1
X
X
X
Illegal operation
Document Number: 001-53687 Rev. *Q
Operation
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Table 5. Writing into Configuration Registers in Serial Mode
SPI_SEN
LD
WEN
REN
WCLK
RCLK
SCLK
Operation
0
1
X
X
X
X
X
1
0
X
Rising edge
X
X
Parallel write to FIFO memory.
X
1
X
0
X
Rising edge
X
Parallel read from FIFO
memory.
1
0
1
1
X
X
X
This corresponds to parallel
mode (refer to Table 4 on page
11).
Rising edge Each rising of the SCLK clocks
in one bit from the SI (Serial
In). Any of the 10 registers can
be addressed and written to,
following the SPI protocol.
Figure 2. Serial WRITE to Configuration Register
Document Number: 001-53687 Rev. *Q
Page 12 of 35
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Width Expansion Configuration
The width of CYFX072V can be expanded to provide word widths greater than 36 bits. During width expansion mode, all control line
inputs are common and all flags are available. Empty (Full) flags are created by ANDing the Empty (Full) flags of every FIFO; the PAE
and PAF flags can be detected from any one device. This technique avoids reading data from or writing data to the FIFO that is
“staggered” by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 3 demonstrates an example of
72 bit-word width by using two 36-bit word CYFX072Vs.
Figure 3. Using Two CYFX072V for Width Expansion
DATAIN (D) 72
36
36
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
WRITE ENABLE (WEN)
OUTPUT ENABLE(OE)
PAE
PAF
CYFX072V
CYFX072V
HF
EF
FF
FF
FF
EF
EF
36
DATAOUT (Q)
72
36
Power Up
The device becomes functional after VCC1, VCC2, VCCIO, and
VREF attain minimum stable voltage required as given in
Recommended DC Operating Conditions on page 16. The
device can be accessed tPU time after these supplies attain the
minimum required level (see Switching Characteristics on page
19). There is no specific power sequencing required for the
device.
Read/Write Clock Requirements
For proper FIFO operation, the device must determine which of
the input clocks – RCLK or WCLK – is faster. This is evaluated
using counters after the MRS cycle. The device uses two 9-bit
counters (one running on RCLK and other on WCLK), which
count 256 cycles of read and write clocks after MRS. The clock
of the counter which reaches its terminal count first is used as
master clock inside the FIFO.
When there is change in the relative frequency of RCLK and
WCLK during normal operation of FIFO, user can specify it by
using “Fast CLK bit” in the configuration register (0xA).
The read and write clocks must satisfy the following
requirements:
“1” - indicates freq (WCLK) > freq (RCLK)
■
Both read (RCLK) and write (WCLK) clocks should be
free-running.
■
The clock frequency for both clocks should be between the
minimum and maximum range given in Electrical
Characteristics on page 16.
The result of counter evaluated frequency is available in this
register bit. User can override the counter evaluated frequency
for faster clock by changing this bit.
■
The WCLK to RCLK ratio should be in the range of 0.5 to 2.
Document Number: 001-53687 Rev. *Q
“0” - indicates freq (WCLK) < freq (RCLK)
Whenever there is a change in this bit value, user must wait tPLL
time before issuing the next read or write to FIFO.
Page 13 of 35
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JTAG Operation
The Programmable FIFO has two devices connected internally in a JTAG chain as shown in figure Figure 4.
Figure 4. Device Connection in a JTAG Chain
Test Access Port
Tap Registers
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven on the
falling edge of TCK.
Registers are connected between the TDI and TDO pins to scan
the data in and out of the test circuitry. Only one register can be
selected at a time through the instruction registers. Data is
serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Test Mode Select (TMS)
Instruction Register
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in Figure 5. Upon power-up, the
instruction register is loaded with the IDCODE instruction. It is
also loaded with the IDCODE instruction if the controller is placed
in a Reset state.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram. TDI is internally pulled up and can be left unconnected
if the TAP is unused in an application. TDI is connected to the
most significant bit (MSB) on any of the TAP registers.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
of the TAP registers.
Note: Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the device
with minimal delay.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the device. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
device input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD instructions can be used to
capture the contents of the input and output ring. The MSB of the
register is connected to TDI and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the device and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Table 6.
Document Number: 001-53687 Rev. *Q
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JTAG ID Codes
Table 6. JTAG IDCODES
IR Register Length
3
8
Device ID (HEX)
“Ignore”
1E3261CF
Device-1
Opcode (Binary)
BYPASS
111
Device-2
BYPASS
EXTEST
HIGHZ
SAMPLE/PRELOAD
IDCODE
Device-1
Device-2
Bypass Register Length
1
1
OPCODES Supported
Table 7. OPCODES Supported
JTAG Instructions
Opcode (Binary)
11111111
00000000
00000111
00000001
00001111
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power-up or whenever the TAP controller is supplied a
Test-Logic-RST state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.
When the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
Instruction Update and Bypass
1. Every time an instruction is loaded through JTAG port, BYPASS command needs to be loaded on device 1.
For example, to push PRELOAD command, BYPASS to
device-1 “111” + PRELOAD to device-2 “00000001” needs to
be sent.
2. When both devices are put on BYPASS, any pattern sent in
should be observed on TDO after two TCK delay.
TAP Controller State Diagram
Figure 5. TAP Controller State Diagram
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required; that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
HIGHZ
The HIGHZ instruction mode is used to set all the user I/O pins
to an inactive drive state. These pins are tri-stated until a new
JATG instruction is executed. When this instruction is selected,
the bypass register is connected between the TDI and TDO
ports.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
Document Number: 001-53687 Rev. *Q
TAP controller is a Finite State Machine with 16 states as shown
in Figure 5. State change is determined by the state of TMS on
rising edge of TCK. Figure 5 shows the value of TMS for each
state transition.
Page 15 of 35
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Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature (without bias) ........ –65 C to +150 C
Voltage applied to I/O pins ...........................–0.3 V to 3.75 V
Output current into outputs (LOW) ............................. 24 mA
Static discharge voltage
(per MIL–STD–883, Method 3015) ......................... > 2001 V
Ambient temperature with
power applied ......................................... –55 C to +125 C
Operating Range
Core supply voltage 1 (VCC1) to
ground potential .............................................–0.3 V to 2.5 V
Range
Core supply voltage 2 (VCC2) to
ground potential ...........................................–0.3 V to 1.65 V
Ambient Temperature
–40 C to +85 C
Industrial
Latch up current ................................................ >100 mA
I/O port supply voltage (VCCIO) ......................–0.3 V to 3.7 V
Recommended DC Operating Conditions
Parameter [4]
Min
Typ
Max
Unit
VCC1
Core supply voltage 1
Description
1.70
1.80
1.90
V
VCC2
Core supply voltage 2
1.425
1.5
1.575
V
VREF
Reference voltage (irrespective of I/O standard used)
0.7
0.75
0.8
V
VCCIO
I/O supply voltage, read and write banks.
LVCMOS33
3.00
3.30
3.60
V
LVCMOS18
1.70
1.8
1.90
V
Min
Typ
Max
Unit
VCC1 = VCC1MAX
–
–
300
mA
VCC2 = VCC2MAX
(All I/O switching, 133 MHz)
–
–
600
mA
VCCIO = VCCIOMAX
(All outputs disabled)
–
–
100
mA
VIN = VCCIOmax to 0 V
–15
–
15
µA
Electrical Characteristics
Parameter
ICC
Description
Active current
Conditions
II
Input pin leakage current
IOZ
I/O pin leakage current
VO = VCCIOmax to 0 V
–15
–
15
µA
CP
Capacitance for TMS and TCK
–
–
–
16
pF
CPIO
Capacitance for all other pins
except TMS and TCK
–
–
–
8
pF
Note
4. Device operation guaranteed for a supply rate > 1 V / µs.
Document Number: 001-53687 Rev. *Q
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I/O Characteristics
(Over the operating range)
Nominal
I/O Standard I/O Supply
Voltage
Input Voltage (V)
VIL(max)
Output Voltage (V)
VIH(min)
VOL(max)
Output Current (mA)
VOH(min)
IOL(max)
IOH(max)
LVCMOS33
3.3 V
0.80
2.20
0.45
2.40
24
24
LVCMOS18
1.8 V
30% VCCIO
65% VCCIO
0.45
VCCIO – 0.45
16
16
Latency Table
Latency Parameter
Number of Cycles
Detail
LFF_ASSERT
Max = 4
Last data write to FF going low.
LEF_ASSERT
0
Last data read to EF going low.
[5]
LPRS_TO_ACTIVE
32
LMAILBOX
2
Latency from write port to read port when MB = 1 (wrt WCLK).
PRS deassert to normal operation.
LREN_TO_DATA
4
Latency when REN is asserted low to first data output from FIFO.
LREN_TO_CONFIG
4
Latency when REN is asserted along with LD to first data read from configuration
registers.
LWEN_TO_PAE_HI
5 [5]
LWEN_TO_PAF_LO
5
[5]
Write to PAF going low.
LREN_TO_PAE_LO
7 [5]
Read to PAE going low.
Write to PAE going high.
7
[5]
Read to PAF going high.
LFF_DEASSERT
8
[5]
Read to FF going high.
LRT_TO_REN
17
First RCLK posedge after RT goes low to initiation of reads by pulling REN low. Flags
update within this period after initiation of a retransmit operation.
LRT_TO_DATA
Max = 21 [5]
First RCLK posedge after RT goes LOW to valid data on Q[35:0].
LIN
Max = 26 [5]
Initial latency for data read after FIFO goes empty during simultaneous read/write.
LREN_TO_PAF_HI
LEF_DEASSERT
Max = 24
LFF_RELEASE
Max = 6
[5]
Write to EF going high.
EF going low to FF deassert during retransmit reads.
Note
5. These latency values are valid for a clock ratio of 1.
Document Number: 001-53687 Rev. *Q
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Figure 6. AC Test Load Conditions
30
0.9 V
(a) VCCIO = 1.8 Volt
30
(b) VCCIO = 3.3 Volt
(c) All Input Pulses
Document Number: 001-53687 Rev. *Q
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Switching Characteristics
Parameter
-133
Description
Min
Max
Unit
tPU
Power-up time after all supplies reach minimum value
–
2
ms
tS
Clock cycle frequency
3.3 V LVCMOS
24
133
MHz
tS
Clock cycle frequency
1.8 V LVCMOS
24
133
MHz
tA
Data access time
–
10
ns
tCLK
Clock cycle time
7.5
41.67
ns
tCLKH
Clock high time
3.375
–
ns
tCLKL
Clock low time
3.375
–
ns
tDS
Data setup time
3
–
ns
tDH
Data hold time
3
–
ns
tENS
Enable setup time
3
–
ns
tENH
Enable hold time
3
–
ns
tENS_SI
Setup time for SPI_SI and SPI_SEN pins
5
–
ns
tENH_SI
Hold time for SPI_SI and SPI_SEN pins
5
–
ns
tRATE_SPI
Frequency of SCLK
–
25
MHz
tRS
Reset pulse width
100
–
ns
tPZS
Port size select to MRS seup time
25
–
ns
tPZH
MRS to port size select hold time
25
–
ns
tRSF
Reset to flag output time
–
50
ns
tPRT
Retransmit pulse width
5
–
RCLK
cycles
tOLZ
Output enable to output in Low Z
4
15
ns
tOE
Output enable to output valid
–
15
ns
tOHZ
Output enable to output in High Z
–
15
ns
tWFF
Write clock to FF
–
8.5
ns
tREF
Read clock to EF
–
8.5
ns
tPAF
Clock to PAF flag
–
17
ns
tPAE
Clock to PAE flag
–
17
ns
tHF
Clock to HF flag
–
17
ns
tPLL
Time required to synchronize PLL
–
1024
cycles
tRATE_JTAG
JTAG TCK cycle time
100
–
ns
tS_JTAG
Setup time for JTAG TMS,TDI
8
–
ns
tH_JTAG
Hold time for JTAG TMS,TDI
8
–
ns
tCO_JTAG
JTAG TCK low to TDO valid
–
20
ns
Document Number: 001-53687 Rev. *Q
Page 19 of 35
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Switching Waveforms
Figure 7. Write Cycle Timing
tCLK
tCLKH
tCLKL
WCLK
tDS
tDH
D[35:0]
tENH
tENS
WEN, IE
NO OPERATION
Figure 8. Read Cycle Timing
tCLK
RCLK
tENS
tENH
REN
NO OPERATION
LREN_TO_DATA
tA
VALID DATA
Q[35:0]
tOLZ
tOHZ
OE
DVal
Document Number: 001-53687 Rev. *Q
Page 20 of 35
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Switching Waveforms (continued)
Figure 9. Reset Timing
tRS
MRS / PRS
tRSF
EF,PAE
tRSF
DVal, FF,PAF,
HF
tRSF
OE=1
Q[35:0]
–
OE=0
Figure 10. MRS to PORTSZ[2:0]
WCLK/RCLK
MRS
tPZS
tPZH
PORTSZ[2:0]
Document Number: 001-53687 Rev. *Q
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Switching Waveforms (continued)
Figure 11. Empty Flag Timing
RCLK
tREF
EF
EF
REN
REN
OE
OE
Q[35:0]
Q(Last)-3
Q(Last)-2
Q(Last)-1
Q(Last)
Invalid Data
DVal
Figure 12. Full Flag Timing
WCLK
tDS
D[35:0]
D0 (written)
D1 (written)
D2 (written)
D3 (not written)
D4 (not written)
tWFF
FF
WEN
Document Number: 001-53687 Rev. *Q
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Switching Waveforms (continued)
Figure 13. Initial Data Latency
WCLK
WEN
D[35:0]
D0
D1
D2
D3
D4
D5
D6
RCLK
tA
REN
L IN (iNITIAL LATENCY)
Q[35:0
QO
Q1
Q2
Q3
Q4
Q5
Q6
DVal
Figure 14. Flow-through Mailbox Operation
WCLK
D[35:0]
REN / WEN
02
1
DO
D1
2
1
3
D2
D3
D4
L MAILBOX
MB
Q[35:0]
QO
Q1
Q2
Q3
Q4
DVal0/
DVal1
DVal
Document Number: 001-53687 Rev. *Q
Page 23 of 35
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Switching Waveforms (continued)
Figure 15. Configuration Register Write
WCLK
tENS
WEN
LD
tDS
D[35:0]
config-reg 0
tDH
config-reg 1
config-reg 2
config-reg 3
config-reg 4
config-reg 5
Figure 16. Configuration Register Read
WCLK
/RCLK
REN
LREN_TO_CONFIG
tA
LD
Q[35:0]
Reg - 1
Figure 17. Empty Flag Deassertion
WCLK
WEN / IE
D[35:0]
D0
D1
L EF_DEASSERT
EF
tREF
RCLK
REN
Document Number: 001-53687 Rev. *Q
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Switching Waveforms (continued)
Figure 18. Empty Flag Assertion
0
1
1
2
2
3
3
4
4
5
RCLK
REN
tA
Q[35:0]
Q
LAST
DVal
L REN_TO_DATA
EF
tREF
L FF_RELEASE
FF
Figure 19. Full Flag Assertion
WCLK
WEN / IE
D[35:0]
D
0
D
1
D
x
D
LAST-1
D
LAST
NOT
WRITTEN
NOT
WRITTEN
FF
Document Number: 001-53687 Rev. *Q
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Switching Waveforms (continued)
Figure 20. Full Flag Deassertion
0
1
2
3
8
WCLK
WEN / IE
D[35:0]
D
LAST-5
D
LAST-4
D
LAST-3
D
LAST-2
D
LAST-1
D
LAST
L FF_DEASSERT
FF
RCLK
REN
Figure 21. PAE Assertion and Deassertion
WCLK
WEN / IE
Note 6
RCLK
REN
L WEN_TO_PAE_HI
1 READ
L REN_TO_PAE_LO
PAE
tPAE
tPAE
Note
6. Refer to Table 2 on page 8 and Latency Table on page 17 for the Programmable Flag boundaries.
Document Number: 001-53687 Rev. *Q
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Switching Waveforms (continued)
Figure 22. PAF Assertion and Deassertion
WCLK
WEN / IE
Note 7
RCLK
REN
L WEN_TO_PAF_LO
1 READ
L REN_TO_PAF_HI
PAF
tPAF
tPAF
Figure 23. HF Assertion and Deassertion
WCLK
WEN / IE
FULL / 2
WRITE
RCLK
REN
L WEN_TO_PAF_LO
1 READ
L REN_TO_PAF_HI
HF
tHF
tHF
Note
7. Refer to Table 2 on page 8 and Latency Table on page 17 for the Programmable Flag boundaries.
Document Number: 001-53687 Rev. *Q
Page 27 of 35
CYF0018V
CYF0036V
CYF0072V
Switching Waveforms (continued)
Figure 24. Mark
RCLK
tENS
REN
tENH
MARK
Q[35:0]
Q (N-2)
DVal
Q (N-1)
Q (N)
Q (N+1)
Q (N+2)
Q (N+3)
Q (N+4)
Q (N+5)
Q (N+6)
DATA MARKED
Figure 25. Retransmit
RCLK
REN
tPRT
LRT_TO_REN
LRT_TO_DATA
RT
Q[35:0]
Q (N)
Q (N+1)
RETRANSMIT FROM
DATA MARKED
DVal
All Flags
Document Number: 001-53687 Rev. *Q
FLAGS UPDATED AFTER RT
Page 28 of 35
CYF0018V
CYF0036V
CYF0072V
Ordering Information
Speed
(MHz)
Ordering Code
Package
Diagram
Operating
Range
Package Type
CYF0018V33L-133BGXI
CYF0036V33L-133BGXI
133
CYF0072V33L-133BGXI
51-85167 209-ball FBGA (14 × 22 × 1.76 mm)
Industrial
CYF0018V18L-133BGXI
CYF0072V18L-133BGXI
Ordering Code Definitions
CY F X XXX VXX X - XXX BGXI
Speed:
133 MHz
I/O Standard:
L = LVCMOS
I/O Voltage:
V18 = 1.8 V
V33 = 3.3 V
Density:
018 = 18M
036 = 36M
072 = 72M
0 - single-queue
FIFO
Cypress
Document Number: 001-53687 Rev. *Q
Page 29 of 35
CYF0018V
CYF0036V
CYF0072V
Package Diagram
Figure 26. 209-ball FBGA (14 × 22 × 1.76 mm) BB209A Package Outline, 51-85167
51-85167 *C
Document Number: 001-53687 Rev. *Q
Page 30 of 35
CYF0018V
CYF0036V
CYF0072V
Acronyms
Acronym
Document Conventions
Description
Units of Measure
FF
Full Flag
FIFO
First In First Out
°C
degree Celsius
HF
Half Full
MHz
megahertz
IE
Input Enable
A
microampere
I/O
Input/Output
mA
milliampere
FBGA
Fine-Pitch Ball Grid Array
mm
millimeter
ms
millisecond
ns
nanosecond
ohm
pF
picofarad
V
volt
W
watt
JTAG
Joint Test Action Group
LSB
Least Significant Bit
LVCMOS
Low Voltage Complementary Metal Oxide
Semiconductor
MB
Mailbox
MRS
Master Reset
MSB
Most Significant Bit
OE
Output Enable
PAF
Programmable Almost-Full
PAE
Programmable Almost-Empty
PRS
Partial Reset
RCLK
Read Clock
REN
Read Enable
RCLK
Read Clock
SCLK
Serial Clock
TCK
Test Clock
TDI
Test Data In
TDO
Test Data Out
TMS
Test Mode Select
WCLK
Write Clock
WEN
Write Enable
Document Number: 001-53687 Rev. *Q
Symbol
Unit of Measure
Page 31 of 35
CYF0018V
CYF0036V
CYF0072V
Document History Page
Document Title: CYF0018V/CYF0036V/CYF0072V, 18/36/72-Mbit Programmable FIFOs
Document Number: 001-53687
Revision
ECN
Orig. of
Change
Submission
Date
**
2711566
VKN /
PYRS
05/27/09
*A
2725088
NXR
06/26/2009
Included pinout, AC and DC specs, timing diagrams and package diagram
Changed Balls B5, D5, F6, K1, K2, K4, K8 and U2 from NC to DNU, Balls C5,
C7, G6, H6, J6, L6, M6, N6, T5, T7 from NC to VCC1, Balls K9, K10, K11 from
NC to VCCIOR, Ball W9 from NC to Vref in pin configuration table
Swapped Voltage range of VSS1 and VSS2
Updated ICC spec
Removed TSKEW parameter
Added Ordering Information table
Added Part Numbering Nomenclature.
Changed title to CYF0018V/CYF0036V/CYF0072V/CYFX144VXXX,
18/36/72-Mbit Programmable FIFOs.
Description of Change
New data sheet.
*B
2839536
NXR
01/28/2010
*C
2884377
HKV
02/25/2010
Post to external web.
*D
2963225
AJU / HPV
06/28/2010
Changed frequency of operation from 250 MHz to 150 MHz
Removed Depth Expansion feature and changed associated pin functionality
Removed Independent Port size selectability feature
Added Data Valid (DVal) signal feature
Updated Logic Block Diagram to reflect above changes.
Pinout changes:
Balls V5, V8, A7, B7, D7, and C6 renamed DNU
Ball U1 changed from RXO to DVal
Ball V2 changed from WXO/HF to HF
Ball A5, A6, B6 changed from WPORTSZ to PORTSZ
Ball A9 changed from RT/FL to RT
Renamed pwr as POWER, gnd as GND
Added Table 4
Table 6 – LD changed to ‘1’ for serial writes
Updated Electrical Characteristics and I/O Characteristics
Switching Characteristics Table:
Renamed tPC as tPU
Min frequency changed from 110MH to 24MHz
Changed tCLKH and tCLKL to 3.15 ns
Changed All setup and hold times to 3 ns
Changed tRSF to 50 ns
Removed tRSR
Changed All clock-to-flag timing to min = 8 ns and max = 14 ns
TPLL changed to 6 ms
Changed all OE-related parameters to 15 ns
Scaled ICC for reduced frequency
Updated all waveforms
Added the following table: “Word Size Selection”.
Added the sections JTAG Operation, and Latency Table
Added Acronyms.
*E
2994379
AJU
07/26/2010
Updated Ordering Information
*F
3101023
SIVS
12/03/2010
Added supply-wise current consumption data in Electrical Characteristics.
Changed initial latency LIN from 34 to 26 and added initial latency LIN for
110 MHz part in Latency Table.
Added 110 MHz part information in JTAG Operation
Added details for the 110 MHz part in Switching Characteristics.
Added details for the 110 MHz part in Ordering Information.
*G
3129722
HKV
01/06/2011
Post to external web.
Document Number: 001-53687 Rev. *Q
Page 32 of 35
CYF0018V
CYF0036V
CYF0072V
Document History Page (continued)
Document Title: CYF0018V/CYF0036V/CYF0072V, 18/36/72-Mbit Programmable FIFOs
Document Number: 001-53687
Revision
*H
*I
ECN
3197271
3388143
Orig. of
Change
Submission
Date
SIVS
AJU
Description of Change
03/31/2011
Removed 144 Mbit parts from the data sheet
Removed multi-queue information from data sheet
Removed 2.5 V and 1.5 V options
Removed HSTL I/II I/O standard
Added clock ratio requirement between RCLK and WCLK
Removed redundant Xs from part number to improve readability
Removed tie to GND option on DNU pins in pin description
Added information on Flag operations to add clarity
Added explanation for flow-through mailbox operation
Added details on active pins in various port sizes in Table 1.
Added Configuration register write to normal operation latency details.
Changed configuration register definitions and default values
Changed number of unusable locations to four to eight
Added JTAG related operation
Added latch-up current parameter in maximum operating conditions.
Removed 2.5 V and 1.5 V options from DC operating condition table 6.
Removed 110 MHz part details and added Cpio parameter in table 7.
Removed 2.5 V and 1.5 V options from Table 8.
Added latency parameters in Table 9.
changed VOL(max) value of LVCMOS33 in table11
Removed 110 MHz part detail from switching characteristics
Added timing waveform to improve clarity.
Modified ordering information and definition.
09/29/2011
Updated Pin Diagram for CYF0XXXVXXL [1] (Added Note 2 and referred the
same note in DNU in ball U6).
Updated Programming Flag Offsets and Configuration Registers (Updated
Table 4 (WCLK column in first row)).
Updated Recommended DC Operating Conditions (Added Note 4 and referred
the same note in Parameter column).
Updated Latency Table (Changed Details for the parameters LWEN_TO_PAE_HI
and LREN_TO_PAE_LO).
Updated Switching Waveforms (Removed the clock cycle numbers in
Figure 13, Figure 14, Figure 18, and Figure 20).
Updated Package Diagram.
Updated in new template.
*J
3652368
ADMU
08/16/2012
Updated Pin Diagram for CYF0XXXVXXL [1] (Updated Figure 1 on page 4 (W9
ball marked as DNU)).
Added Figure 6 (Test Load Conditions).
Updated Switching Characteristics (Changed minimum values of tS_JTAG,
tH_JTAG parameters from 5 ns to 8 ns, changed maximum value of tCO_JTAG
parameter from 10 ns to 20 ns).
*K
3735896
ADMU
09/07/2012
Updated package diagram 51-85167 to *C
Updated “Output current into outputs (LOW)” parameter under Maximum
Ratings section from 20 mA to 24 mA.
Document Number: 001-53687 Rev. *Q
Page 33 of 35
CYF0018V
CYF0036V
CYF0072V
Document History Page (continued)
Document Title: CYF0018V/CYF0036V/CYF0072V, 18/36/72-Mbit Programmable FIFOs
Document Number: 001-53687
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
*L
3940217
ADMU
03/22/2013
Updated Features.
Updated Functional Description.
Updated Logic Block Diagram.
Updated Pin Diagram for CYF0XXXVXXL [1]:
Added Note 1 and referred the same note in Figure 1.
Updated Pin Definitions.
Updated Architecture:
Updated Reset Logic, Data Valid Signal (DVal), Flag Operation, Retransmit
from Mark Operation, Programming Flag Offsets and Configuration Registers,
Read/Write Clock Requirements.
Added Table 2.
Updated Latency Table.
Updated Switching Waveforms:
Updated Figure 13, Figure 14, Figure 18, Figure 20, Figure 21, Figure 22,
Figure 23, Figure 25.
Added Note 6 and referred the same note in WEN / IE in Figure 21.
Added Note 7 and referred the same note in WEN / IE in Figure 22.
Updated Ordering Information (Updated part numbers).
*M
3997615
ADMU
05/11/2013
Added Errata.
*N
4078255
ADMU
07/26/2013
Added Errata footnotes (Note 4, 7, 8, 11).
Updated Architecture:
Updated Retransmit from Mark Operation:
Added Note 4 and referred the same note in 2nd paragraph and last paragraph.
Updated Latency Table:
Added Note 7 and referred the same note in “LFF_RELEASE” parameter.
Updated Switching Waveforms:
Added Note 8 and referred the same note in “LFF_RELEASE” in Figure 18.
Added Note 11 and referred the same note in “All Flags” and “FLAGS
UPDATED AFTER RT” in Figure 25.
Updated in new template.
*O
4202562
SMCH
11/27/2013
Updated Errata.
*P
4580426
SMCH
11/25/2014
Added related documentation hyperlink in page 1.
06/28/2016
Updated Logic Block Diagram.
Updated Pin Diagram for CYF0XXXVXXL [1].
Updated Pin Definitions.
Updated JTAG Operation.
Removed Errata section.
Updated CY Logo and Sales Disclaimer.
*Q
5326858
SMCH
Document Number: 001-53687 Rev. *Q
Page 34 of 35
CYF0018V
CYF0036V
CYF0072V
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
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closest to you, visit us at Cypress Locations.
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Forums | Projects | Video | Blogs | Training | Components
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© Cypress Semiconductor Corporation, 2009-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
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provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
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Document Number: 001-53687 Rev. *Q
Revised June 28, 2016
Page 35 of 35