19-5788; Rev 3; 5/12 EVALUATION KIT AVAILABLE MAX14824 IO-Link Master Transceiver General Description Features The MAX14824 is an IO-LinkM master interface that integrates an IO-Link physical layer transceiver with an auxiliary digital input and two linear regulators. High port count IO-Link master applications are supported through in-band SPI addressing, and the 12MHz SPI interface minimizes host controller access times. In-band addressing and selectable SPI addresses enable cascading up to 16 devices. S IO-Link v.1.0 and v.1.1 Physical Layer Compliant S Supports COM1, COM2, and COM3 Data Rates S Push-Pull, High-Side, or Low-Side Outputs S 300mA C/Q Output Drive S 1µF C/Q Load Drive Capability S Generates 500mA Wake-Up Pulse S Automatic Wake-Up Pulse Polarity The device supports all the IO-Link data rates and features slew-rate-controlled drivers to reduce EMI. The driver is guaranteed to drive up to 300mA (min) load currents. Internal wake-up circuitry automatically determines the correct wake-up polarity, allowing for the use of simple UARTs for wake-up pulse generation. S Auxiliary Digital Input S 5V and 3.3V Linear Regulators S SPI Interface for Configuration and Monitoring S SPI-Based Chip Addressing S EMI Emission Control Through Slew-Controlled Driver The MAX14824 is available in a 4mm x 4mm, 24-pin TQFN package with exposed pad, and operates over the extended -40NC to +105NC temperature range. S Reverse-Polarity Protection on DI S Short-Circuit Protection on C/Q Applications S High Temperature Warning and Thermal Shutdown IO-Link Master Controllers S Extensive Fault Monitoring and Reporting PLC Fieldbus Gateways S -40NC to +105NC Operating Temperature Range High Port Count IO-Link Masters S 4mm x 4mm TQFN Package 24V Digital Inputs and Outputs Ordering Information appears at end of data sheet. Typical Operating Circuits 24V 1μF 1μF 0.1μF 270pF VCC VL SPI TXQ LDO33 V5 LDOIN VCC C/Q IO-LINK CONTROLLER GPO WUEN RX RX TX TXC RTS TXEN GND C/Q 270pF MAX14824 A0 A1 A2 DI A3 GND Typical Operating Circuits continued at end of data sheet. IO-Link is a registered trademark of Profibus User Organization (PNO). For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/MAX14824.related 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX14824 IO-Link Master Transceiver Functional Diagram LDO33 V5 LDOIN UV UV MONITOR 3.3V LDO 5V LDO VL CS SDI SDO SCLK IRQ A3:A0 VCC STATUS AND CONFIGURATION RX WUEN SHORT-CIRCUIT PROTECTION FILTER C/Q C/Q LOAD WU POLARITY GENERATOR TXQ DRIVER TXC GND TXEN REVERSE POLARITY PROTECTION LI DI LOAD DI MAX14824 2 MAX14824 IO-Link Master Transceiver ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND, unless otherwise specified.) VCC.........................................................................-0.3V to +40V LDOIN.....................................................................-0.3V to +40V V5........................0.3V to the lesser of (VLDOIN + 0.3V) and +6V LDO33 ..................... -0.3V to the lesser of (V5 + 0.3V) and +6V VL..............................................................................-0.3V to +6V DI.............................................................................-40V to +40V C/Q............................................................ -0.3V to (VCC + 0.3V) Logic Inputs TXC, TXQ, TXEN, A2, CS, SDI, SCLK, WUEN... -0.3V to (VL + 0.3V) A3, A1, A0............................................................-0.3V to +6V Logic Outputs RX, LI, SDO, IRQ...................................... -0.3V to (VL + 0.3V) UV.........................................................................-0.3V to +6V Continuous Current Into Any Logic Pin ........................... Q50mA Continuous Power Dissipation TQFN (derate 27.8mW/NC above +70NC)..................2222mW Operating Temperature Range......................... -40NC to +105NC Maximum Junction Temperature......................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) TQFN Junction-to-Ambient Thermal Resistance (BJA)...........36NC/W Junction-to-Case Thermal Resistance (BJC)..................3NC/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. DC ELECTRICAL CHARACTERISTICS (VCC = 18V to 36V, VL = 2.3V to 5.5V, VGND = 0V; all logic inputs at VL or GND; TA = -40NC to +105NC, unless otherwise noted. Typical values are at VCC = 24V, VL = 3.3V, and TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS VCC Supply Voltage VCC For driver operation VCC Supply Current ICC VCC = 24V, C/Q as input, no load on V5 or LDO33, LDOIN not connected to VCC, VLDOIN = 24V VCC Undervoltage Lockout Threshold VCCUVLO VCC Undervoltage Lockout Threshold Hysteresis VCCUVLO_HYST V5 Supply Current V5 Undervoltage Lockout Threshold VL Logic-Level Supply Voltage VL Logic-Level Supply Current VL Undervoltage Threshold I5_IN V5UVLO VCC falling IL TYP MAX UNITS 36 V 1.3 2.5 mA 7.5 9 V 9 6 LDOIN shorted to V5, external 5V applied to V5, no switching, LDO33 disabled V5 falling VL VLUVLO MIN 200 mV 3 mA 2.4 V 2.3 All logic inputs at VL or GND VL falling 0.65 0.95 5.5 V 5 FA 1.3 V 36 V 5V LDO (V5) LDOIN Input Voltage Range VLDOIN 7 3 MAX14824 IO-Link Master Transceiver DC ELECTRICAL CHARACTERISTICS (continued) (VCC = 18V to 36V, VL = 2.3V to 5.5V, VGND = 0V; all logic inputs at VL or GND; TA = -40NC to +105NC, unless otherwise noted. Typical values are at VCC = 24V, VL = 3.3V, and TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER LDOIN Supply Current V5 Output Voltage Range SYMBOL ILDOIN V5 CONDITIONS MIN VLDOIN = 24V, C/Q as input, no load on V5 or LDO33 No load on V5, 7V P VLDOIN P 36V 4.75 1mA < ILOAD < 10mA, VLDOIN = 7V, 0.1FF bypass capacitor on V5 V5 Load Regulation TYP MAX UNITS 3.0 5 mA 5.00 5.25 V 0.08 % 3.3V LDO (LDO33) LDO33 Output Voltage LDO33 Undervoltage Lockout Threshold VLDO33 VLDO33UVLO LDO33 Load Regulation No load on LDO33 3.1 3.5 V VLDO33 falling 2.4 V 1mA < ILOAD < 10mA, VLDOIN = 7V 0.25 % 24V INTERFACE C/Q Output Resistance High ROH_C/Q C/Q high-side enabled, IC/Q = -200mA, 9V P VCC P 36V (Note 5) 1.8 2.9 I C/Q Output Resistance Low ROL_C/Q C/Q low-side enabled, IC/Q = +200mA, 9V P VCC P 36V (Note 5) 2.0 3.6 I C/Q Source Current Limit IOH_C/Q C/Q high-side enabled, VC/Q < (VCC 3V), 9V P VCC P 36V C/Q Sink Current Limit IOL_C/Q C/Q low-side enabled, VC/Q > 3V, 9V P VCC P 36V C/Q Input Threshold High VIH_C/Q C/Q driver disabled C/Q Input Threshold Low VIL_C/Q C/Q driver disabled VHYS_C/Q C/Q driver disabled 1.0 C/Q Input Hysteresis +500 +670 -660 mA -500 mA 10.5 13.0 V 8.0 11.5 V V DI Input Threshold High VIH_DI 6.8 8 V DI Input Threshold Low VIL_DI 5.2 6.4 V 400 FA 300 FA DI Input Hysteresis C/Q Weak Pulldown Current VHYS_DI IPDC/Q 1 C/Q driver disabled, VC/Q = VCC 100 50 DI Weak Pulldown Current IPDDI DI load disabled, VDI = VCC C/Q Input Capacitance CC/Q C/Q driver disabled DI Input Capacitance CDI V 40 pF 20 pF C/Q, DI INPUT LOAD C/Q Load Current DI Load Current ILLM_C/Q ILLM_DI C/Q load enabled (C/QLoad = 1) 0 P VC/Q P 5V 0 9V P VC/Q 5 DI load enabled (DiLoad = 1) 0 P VDI P 5V 0 9V P VDI 2 8.1 6.8 8.1 4.3 3.5 4.3 mA mA 4 MAX14824 IO-Link Master Transceiver DC ELECTRICAL CHARACTERISTICS (continued) (VCC = 18V to 36V, VL = 2.3V to 5.5V, VGND = 0V; all logic inputs at VL or GND; TA = -40°C to +105°C, unless otherwise noted. Typical values are at VCC = 24V, VL = 3.3V, and TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS (TXC, TXQ, TXEN, CS, WUEN, SDI, SCLK, A3, A2, A1, A0) Logic Input-Voltage Low VIL Logic Input-Voltage High VIH Logic Input Leakage Current ILEAK Logic Input Capacitance CIN A1 Pulldown Resistance RA1PD 0.3 x VL Logic input = GND or VL V -1 0.7 x VL V +1 FA 5 325 pF 800 kI 0.4 V LOGIC OUTPUTS (RX, LI, UV, SDO, IRQ) Logic Output-Voltage Low Logic Output-Voltage High SDO Leakage Current VOL IOUT = -5mA VOHRX, VOHWU, VOHLI, IOUT = 5mA (Note 3) VOHSDO, VOHIRQ, ILK_SDO VL 0.6 SDO disabled, SDO = GND or VL V -1 +1 FA THERMAL SHUTDOWN Thermal Warning Threshold Die temperature rising, OTemp bit is set Thermal Warning Threshold Hysteresis Die temperature falling, OTemp bit is cleared Thermal Shutdown Threshold Die temperature rising Thermal Shutdown Hysteresis +115 NC 20 NC +150 NC 20 NC AC ELECTRICAL CHARACTERISTICS (VCC = 18V to 36V, VL = 2.3V to 5.5V, VGND = 0V; all logic inputs at VL or GND; TA = -40°C to +105°C, unless otherwise noted. Typical values are at VCC = 24V, VL = 3.3V, and TA = +25oC, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS C/Q, DI INTERFACES Data Rate DR HiSlew = 1 4.8 230.4 HiSlew = 0 4.8 38.4 kbps DRIVER (C/Q) Driver Low-to-High Propagation Delay tPDLH Push-pull or high-side (PNP) configuration, Figure 1 HiSlew = 1 0.5 2 HiSlew = 0 1.6 5 Driver High-to-Low Propagation Delay tPDHL Push-pull or low-side (NPN) configuration, Figure 1 HiSlew = 1 0.5 2 HiSlew = 0 1.6 5 Fs Fs 5 MAX14824 IO-Link Master Transceiver AC ELECTRICAL CHARACTERISTICS (continued) (VCC = 18V to 36V, VL = 2.3V to 5.5V, VGND = 0V; all logic inputs at VL or GND; TA = -40oC to +105oC, unless otherwise noted. Typical values are at VCC = 24V, VL = 3.3V, and TA = +25oC, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS TYP MAX UNITS 0.1 2 Fs HiSlew = 1 0.4 0.85 HiSlew = 0 1.5 4 Push-pull or low-side (NPN) configuration, Figure 1 HiSlew = 1 0.4 0.85 HiSlew = 0 1.4 4 tENH Push-pull or high-side (PNP) configuration, Figure 3 HiSlew = 1 0.3 1.5 HiSlew = 0 0.8 7 Driver Enable Time Low tENL Push-pull or low-side (NPN) configuration, Figure 2 HiSlew = 1 0.3 1.5 HiSlew = 0 0.9 7 Driver Disable Time High tDISH Push-pull or high-side (PNP) configuration, Figure 2 (Note 4) HiSlew = 1 1.6 3 HiSlew = 0 1.6 3 Driver Disable Time Low tDISL Push-pull or low-side (NPN) configuration, Figure 3 (Note 4) HiSlew = 1 0.1 3 HiSlew = 0 0.1 3 RxFilter = 0 0.4 2 RxFilter = 1 0.2 2 RxFilter = 0 0.5 2 RxFilter = 1 0.3 2 Driver Skew tSKEW |tPDLH - tPDHL| Driver Rise Time tRISE Push-pull or high-side (PNP) configuration, Figure 1 Driver Fall Time tFALL Driver Enable Time High MIN Fs Fs Fs Fs Fs Fs RECEIVER (C/Q, DI) (Figure 4) Receiver Low-to-High Propagation Delay Receiver High-to-Low Propagation Delay tPRLH tPRHL Fs WAKE-UP GENERATION (Figure 5) Wake-Up Enable Setup Time tWUEN,S 30 ns Wake-Up Enable Hold Time tWUEN,H 30 ns Wake-Up Pulse Rise Propagation Delay t1 1.5 5 Fs Wake-Up Pulse Fall Propagation Delay t2 1.5 3 Fs SPI TIMING (CS, SCLK, SDI, SDO) (Figure 6) SCLK Clock Period tCH+CL 83.3 ns SCLK Pulse-Width High tCH 41.65 ns SCLK Pulse-Width Low tCL 41.65 ns CS Fall to SCLK Rise Time tCSS 20 ns SCLK Rise to CS Rise Hold Time tCSH 20 ns SDI Hold Time tDH 10 ns 6 MAX14824 IO-Link Master Transceiver AC ELECTRICAL CHARACTERISTICS (continued) (VCC = 18V to 36V, VL = 2.3V to 5.5V, VGND = 0V; all logic inputs at VL or GND; TA = -40oC to +105oC, unless otherwise noted. Typical values are at VCC = 24V, VL = 3.3V, and TA = +25oC, unless otherwise noted.) (Note 2) PARAMETER SYMBOL SDI Setup Time tDS Output Data Propagation Delay tDO SDO Rise and Fall Times Minimum CS Pulse CONDITIONS MIN tFT tCSW TYP MAX 10 76.8 UNITS ns 32 ns 20 ns ns Note 2: All devices are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by design. Note 3: UV is an open-drain output. Connect UV to a voltage less than 5.5V through an external pullup resistor. Note 4: Disable time measurements are load-dependent. Note 5: Guaranteed by design. Limits are not production tested. 7 MAX14824 IO-Link Master Transceiver TXEN TXC C/Q MAX14824 TXQ 3.3nF 5kΩ GND VL TXEN 0V VL TXC AND TXQ 50% 0V tPDHL tPDLH C/Q tFALL VCC 90% 50% 10% 0V tRISE Figure 1. Driver Polarity and Timing VCC 5kΩ TXEN C/Q VL MAX14824 TXC 3.3nF TXQ GND VL TXEN 0V tDISH tENL VCC C/Q 10% 10% 0V Figure 2. Driver Enable Low and Disable High Timing 8 MAX14824 IO-Link Master Transceiver TXEN C/Q MAX14824 TXC 3.3nF 5kΩ TXQ GND VL TXEN 0V tDISL tENH C/Q VCC 90% 90% 0V Figure 3. Driver Enable High and Disable Low Timing RX OR LI C/Q OR DI 15pF MAX14824 TXEN GND VCC C/Q OR DI 50% tPRLH 0V tPRHL VL RX OR LI 50% 0V Figure 4. Receiver Polarity and Timing 9 MAX14824 IO-Link Master Transceiver WUEN tWUEN, H tWUEN, S TXC AND TXQ 80µs t1 t2 C/Q X WAKE-UP PULSE Figure 5. Wake-Up Generation CS tCSS tCSH tCH tCSH tCL SCLK tDS tDH SDI tDO SDO Figure 6. SPI Timing Diagram 10 MAX14824 IO-Link Master Transceiver Typical Operating Characteristics (VCC = 24V, LDOIN = VCC, VL = LDO33, C/Q is in push-pull configuration, TA = +25NC, unless otherwise noted.) TA = -40°C 23 5 VOL_C/Q (V) TA = +85°C 21 TA = +105°C 20 19 4 TA = +105°C 3 TA = +85°C 2 1 TXEN = VL TCX = TXQ = GND 0 1.50 TA = -40°C 0 100 200 300 400 500 600 700 800 100 200 300 400 500 600 700 800 LOAD CURRENT (mA) C/Q DRIVER PROPAGATION DELAY vs. TEMPERATURE (HiSlew = 0) C/Q DRIVER PROPAGATION DELAY vs. TEMPERATURE (HiSlew = 1) TXEN = VL TXC = TXQ 1.48 0 LOAD CURRENT (mA) 0.50 MAX14824 toc03 17 TA = +25°C 1.46 MAX14824 toc04 18 TXEN = VL TXC = TXQ 0.45 0.40 1.44 1.42 tPDHL (µs) tPDHL (µs) TXEN = VL TCX = TXQ = VL 6 TA = +25°C 22 VOH_C/Q (V) 7 MAX14824 toc01 24 C/Q DRIVER OUTPUT LOW vs. LOAD CURRENT MAX14824 toc02 C/Q DRIVER OUTPUT HIGH vs. LOAD CURRENT 1.40 1.38 1.36 0.35 0.30 0.25 1.34 0.20 1.32 0.15 1.30 -45 -30 -15 0 15 30 45 60 75 -45 -30 -15 90 0 15 30 45 60 75 90 TEMPERATURE (°C) TEMPERATURE (°C) C/Q DRIVER OUTPUT SWITCHING (HiSlew = 0) C/Q DRIVER OUTPUT SWITCHING (HiSlew = 1) MAX14824 toc05 MAX14824 toc06 VTXC 2V/div VTXC 2V/div 0V Ch1 Ch2 1.593µs TXEN = VL TXC = TXQ Ch1 Ch2 1.408µs VC/Q 5V/div Ch2 RISE 1.618µs 0V Ch1 Ch2 425.9ns TXEN = VL TXC = TXQ Ch1 Ch2 381.9ns VC/Q 5V/div Ch2 RISE 365.6ns Ch2 FALL 370.4ns Ch2 FALL 1.520µs 0V 0V 2µs/div 2µs/div 11 MAX14824 IO-Link Master Transceiver Typical Operating Characteristics (continued) (VCC = 24V, LDOIN = VCC, VL = LDO33, C/Q is in push-pull configuration, TA = +25NC, unless otherwise noted.) RECEIVER PROPAGATION DELAY vs. TEMPERATURE (RxFilter = 0) 350 C/Q TO RX MAX14824 toc08 DI TO LI 450 400 350 300 tPRHL (ns) tPRHL (ns) 450 400 500 MAX14824 toc07 500 C/Q RECEIVER PROPAGATION DELAY vs. TEMPERATURE (RxFilter = 1) 250 200 300 250 200 150 150 100 100 50 50 0 DI TO LI C/Q TO RX 0 -45 -30 -15 0 15 30 45 60 75 -45 -30 -15 90 TEMPERATURE (°C) C/Q SHORT-CIRCUIT PROTECTION C/Q SHORT-CIRCUIT PROTECTION MAX14824 toc09 40µs/div 15 30 45 60 75 90 WAKE-UP GENERATION MAX14824 toc10 MAX14824 toc11 VWUEN 2V/div VC/Q 10V/div VC/Q 10V/div TXC = TXQ = GND, tSHORT = 200µs 0 TEMPERATURE (°C) 0V 0V VIRQ 2V/div VIRQ 2V/div 0V 0V ISOURCE 500mA/div 0mA ISINK 500mA/div 0mA TXC = TXQ = VL, tSHORT = 300µs 40µs/div 0V VTXC 2V/div 0V VC/Q 10V/div 0V 20µs/div 12 MAX14824 IO-Link Master Transceiver Typical Operating Characteristics (continued) (VCC = 24V, LDOIN = VCC, VL = LDO33, C/Q is in push-pull configuration, TA = +25NC, unless otherwise noted.) V5 LOAD REGULATION LDO33 LOAD REGULATION -0.2 -0.1 TA = -40°C -0.2 TA = +25°C -0.3 MAX14824 toc13 -0.1 % VOLTAGE CHANGE 0 % VOLTAGE CHANGE 0 MAX14824 toc12 0.1 TA = +85°C TA = -40°C -0.3 -0.4 TA = +25°C -0.5 -0.6 TA = +85°C -0.7 -0.8 -0.4 -0.9 -0.5 -1.0 10 20 30 40 50 0 5 10 15 20 25 30 35 40 45 50 LOAD CURRENT (mA) VCC SUPPLY CURRENT vs. VCC VOLTAGE LDOIN SUPPLY CURRENT vs. LDOIN VOLTAGE TA = -40°C TA = +25°C 1.2 TA = +85°C 2.5 ILDOIN (mA) ICC (mA) 1.4 3.0 1.0 0.8 0.6 14 TA = -40°C 1.5 VLDOIN = 7V C/Q DRIVER IS ENABLED TXC = TXQ = VL 0.2 0 9 12 15 18 21 0 24 27 30 33 36 10 VCC = 30V 8 9 12 15 18 21 VCC = 24V 4 VCC = 36V C/Q DRIVER IS ENABLED TXC = TXQ = VL 0.5 VCC VOLTAGE (V) VCC = 36V 12 6 1.0 0.4 16 TA = +25°C 2.0 VLDOIN = V5 = 5V, TXEN = VL, HiSlew = 1, NO LOAD ON C/Q, CONTINUOUS 1010 PATTERN TRANSMISSION 18 ICC (mA) 1.6 20 MAX14824 toc15 TA = +85°C VCC SUPPLY CURRENT vs. C/Q DATA RATE 3.5 MAX14824 toc14 2.0 1.8 LOAD CURRENT (mA) MAX14824 toc16 0 2 24 VLDOIN (V) 27 30 33 36 0 1 10 100 1000 C/Q DATA RATE (kbps) 13 MAX14824 IO-Link Master Transceiver Pin Configuration UV LI A2 WUEN RX TXEN TOP VIEW 18 17 16 15 14 13 DI 19 12 TXC GND 20 11 TXQ C/Q 21 10 A3 MAX14824 A1 22 VCC 23 *EP + 1 2 3 4 5 6 LDOIN V5 LDO33 IRQ SCLK CS A0 24 9 VL 8 SDI 7 SDO TQFN (4mm × 4mm) *CONNECT EXPOSED PAD TO GND. Pin Description PIN NAME 1 LDOIN 2 V5 3 LDO33 4 IRQ 5 SCLK FUNCTION 5V Linear-Regulator Input. Bypass LDOIN to GND with a 0.1FF ceramic capacitor. 5V Power-Supply Input and 5V Linear-Regulator Output. Bypass V5 to GND with a 0.1FF ceramic capacitor. See the 5V and 3.3V Linear Regulators section for more information. 3.3V Linear-Regulator Output. Bypass LDO33 to GND with a 1FF ceramic capacitor. Active-Low Interrupt Request Output. IRQ is a push-pull output referenced to VL. SPI Clock Input 6 CS 7 SDO SPI Chip-Select Input SPI Serial-Data Output Port 8 SDI SPI Serial-Data Input Port 9 VL Logic-Level Supply Input. VL defines the logic levels on all the logic inputs and outputs. Bypass VL to GND with a 0.1FF ceramic capacitor. 10 A3 Chip-Select Address Input 3. Do not leave A3 unconnected. 11 TXQ Transmit Level Input. TXQ is ANDed with TXC. Drive TXQ high if not in use. 12 TXC Transmit Communication Input. TXC is ANDed with TXQ. Drive TXC high if not in use. 13 TXEN Transmitter Enable. Driving TXEN high enables the C/Q transmitter. While the C/Q transmitter is enabled, the C/Q current sink is turned off. 14 MAX14824 IO-Link Master Transceiver Pin Description (continued) PIN NAME FUNCTION Receiver Output. RX is the inverse logic level of C/Q. RX is always high when the RxDis bit in the CQConfig register is set to 1. 14 RX 15 WUEN 16 A2 Chip-Select Address Input 2. Do not leave A2 unconnected. 17 LI Logic Output of 24V DI Logic Input. LI is the inverse logic of DI. LI is referenced to VL. 18 UV Open-Drain Undervoltage Indicator Output. UV is active high. 19 DI 24V Logic-Level Digital Input 20 GND Ground 21 C/Q SIO/IO-Link Data Input/Output. Drive TXEN high to enable the C/Q driver. The logic on the C/Q output is the inverse logic level of the signals on the TXC and TXQ inputs. Drive TXEN low to disable the C/Q driver. RX is the logic inverse of C/Q. 22 A1 Chip-Select Address Input 1. Do not leave A1 unconnected. 23 VCC 24 A0 Chip-Select Address Input 0. Do not leave A0 unconnected. — EP Exposed Pad. Connect EP to GND. Wake-Up Enable Input. Drive WUEN high to enable automatic wake-up pulse generation. Power-Supply Input. Bypass VCC to GND with a 1FF ceramic capacitor. Detailed Description The MAX14824 is an IO-LinkM master transceiver that integrates an IO-Link physical interface with an additional 24V digital input and two LDOs. A 12MHz SPIK interface allows fast programming and monitoring. The device supports COM1, COM2, and COM3 IO-Link data rates and has the option of limiting emitted EMI by selecting a lower slew rate at lower data rates. The automatic wake-up circuitry determines the correct wake-up pulse polarity, allowing the use of simple UARTs for wake-up pulse generation. The C/Q and DI inputs have selectable current sinks that can be enabled for use in actuators. The device is configured and monitored through an SPI interface. Extensive alarms are available through SPI. 24V Interface The device features an IO-Link transceiver interface capable of operating with voltages up to 36V. This includes the C/Q input/output and the logic-level digital input (DI). IO-Link is a registered trademark of Procibus User Organization (PNO). DI is reverse-polarity protected. Short-circuit protection is provided on the C/Q driver. Configurable C/Q Driver The device’s C/Q driver has a selectable push-pull, highside (PNP), or low-side (NPN) switching driver. Set the C/Q_N/P and C/Q_PP bits in the CQConfig register to select the driver mode for the C/Q driver. When configured as a push-pull output, C/Q switches between VCC and ground. Set the C/Q_PP bit to 1 to select pushpull operation. Set the C/Q_PP bit to 0 to configure the C/Q output for open-drain operation. The C/Q_N/P bit selects NPN or PNP operation when C/Q is configured as an open-drain output. C/Q Driver and Receiver The C/Q driver can be enabled through hardware (TXEN) or software (C/QDEn). Drive TXEN high to enable the C/Q driver and drive TXEN low to disable the driver. The C/Q driver can be enabled through the C/QDEn bit in the C/QConfig register. The C/Q driver on the device is specified for 300mA to drive large capacitive loads over 1FF and dynamic impedances like incandescent lamps. SPI is a trademark of Motorola Inc. 15 MAX14824 IO-Link Master Transceiver The HiSlew bit increases the slew rate of the C/Q driver output. Set HiSlew to 1 for data rates of 230kbps or higher. Set HiSlew to 0 to reduce the C/Q driver slew rate and reduce EMI emission and reflections. The C/Q receiver is always on. Disable the RX output through the RxDis bit in the CQConfig register. Set the RxDis bit to 1 to set the RX output high. Set the RxDis bit to 0 for normal receive operation. The C/Q receiver has an analog lowpass filter to reduce high-frequency noise present on the line. Set the RxFilter bit in the CQConfig register to 0 to set the filter corner frequency to 500kHz (typ). Set the RxFilter bit to 1 to set the corner frequency of the filter to 1MHz (typ). Noise filters are present on both the C/Q and DI receivers and are controlled simultaneously by the RxFilter bit. C/Q Fault Detection The device registers a C/QFault condition under either of two conditions: 1) When it detects a short circuit for longer than 160µs (typ). A short condition exists when the C/Q driver’s load current exceeds the 670mA (typ) current limit. 2) When it detects a voltage level error at the C/Q output. A voltage level error occurs when the C/Q driver is configured for open-drain operation (NPN or PNP), the driver is turned off, and the C/Q voltage is not pulled to exceed the C/Q receiver’s threshold levels (< 8V or > 13V) by the external supply. When a C/QFault error occurs, the C/QFault and C/QFaultInt bits are set, IRQ asserts, and the driver is turned off 240µs (typ) after the start of the fault condition. When a short-circuit event occurs on C/Q, the driver enters autoretry mode. In autoretry mode the device periodically checks if the short is still present and attempts to correct the driver output. Autoretry attempts last for 350µs (typ) and occur every 26ms (typ). DI Auxillary Digital Input DI is a digital input that is Type 1 and Type 3 compliant when the internal 3.5mA DI current load is enabled. If the IO-link master system does not require auxilliary digital inputs, DI can be connected to C/Q as shown in the Typical Operating Circuits. This reduces the power dissipation when C/Q is operated as a digital input, by enabling the DI current load instead of the C/Q current load. Di is tolerant to reverse polarity voltages down to -40V when not connected to C/Q. 5V and 3.3V Internal Regulators The device includes two internal current-limited regulators to generate 5V (V5) and 3.3V (LDO33). V5 is specified at 10mA. LDO33 is specified at 10mA. The input of V5, LDOIN, can be connected to VCC or to another voltage in the 7V to 36V range. V5 consitutes the supply for the logic block in the device. The device can be powered by an external 5V power supply. Disable the 5V LDO by connecting LDOIN to V5. Apply an external voltage from 4.75V to 5.25V to V5 when the LDO is disabled. Use the LDO33Dis bit in the Mode register to enable/ disable LDO33. See the Mode Register [R1, R0] = [1,1] section for more information. V5 and LDO33 are not protected against short circuits. Power-Up The C/Q driver output and the UV output are high impedance when VCC, V5, VL, and/or LDO33 voltages are below their respective undervoltage thresholds during power-up. UV goes low and the C/Q driver is enabled when all these voltages exceed their respective undervoltage lockout thresholds. The C/Q driver is automatically disabled if VCC, V5, or VL falls below its threshold. Undervoltage Detection The device monitors VCC, V5, VL, and, optionally, LDO33 for undervoltage conditions. UV is high impedance when any monitored voltage falls below its UVLO threshold. VCC, V5, and VL undervoltage detection cannot be disabled. When VCC falls below the VCCUVLO threshold, the UV24 and UV24Int bits are set, UV asserts high, and IRQ asserts low. The SPI register contents are unchanged while V5 is present, regardless of the state of VCC or LDO33. The SPI interface is not accessible and IRQ is not available when UV is asserted due to a V5 or VL undervoltage event. When the internal 3.3V LDO regulator voltage (VLDO33) falls below the LDO33 undervoltage lockout threshold, the UV33Int bit in the Status register is set and IRQ asserts. UV asserts if the UV33En bit in the Mode register is set to 1. The UV output deasserts once the undervoltage condition is removed; however, the associated interrupts bits in the Status register and the IRQ output are not cleared until the Status register has been read. 16 MAX14824 IO-Link Master Transceiver Wake-Up Generation The MAX14824 features automatic wake-up polarity generation functionality that can be initiated through hardware or software. The following conditions must be met prior to automatic wake-up polarity generation to ensure proper functionality: • WUEN is low • TXEN is low and C/QDEn = 0 • Q = 0 • TXC and TXQ are both high Drive WUEN high to enable the automatic wake-up polarity generation circuitry in the device. When WUEN is high, apply an external pulse to TXC or TXQ from high-to-low for 80Fs (typ) to generate a valid wake-up pulse. The applied pulse is independent of the logic state that the IO-Link sensor was forcing on the C/Q level (Figure 5). Drive WuEN low after the wake-up has been generated. The C/Q driver is automatically enabled while TXC/TXQ is low and C/Q is pulled either from high-to-low or from low-to-high, depending on the previous state. The C/Q driver is automatically disabled when the TXC/TXQ inputs are pulled high again. Wake-up polarity generation can also be enabled through software by setting the WuEnBit bit in the Mode register to 1. See the Mode Register [R1, R0] = [1,1] section for more information. Thermal Protection and Considerations The internal LDOs and C/Q driver can generate more power than the package for the device can safely dissipate. Ensure that the driver LDO loading is less than the package can dissipate. Total power dissipation for the device is calculated using the following equation: PTOTAL = PC/Q + P5 + PLDO33 + PQ + PCLCQ + PCLDI where PC/Q is the power generated in the C/Q driver, P5 and PLDO33 are the power generated by the LDOs, PQ is the quiescent power generated by the device, and PCLCQ and PCLDI are the power generated in the C/Q and DI current sinks. Calculate the power dissipation in the 5V LDO, V5, using the following equation: P5 = (VLDOIN - V5) × I5 where I5 includes the ILDO33 current sourced from LDO33. Calculate the power dissipated in the 3.3V LDO, LDO33, using the following equation: PLDO33 = 1.7V × ILDO33 Calculate the quiescent power dissipation in the device using the following equation: PQ = ICC × VCC If the current sinks are enabled, calculate their associated power dissipation as: PCLCQ = ILLM_C/Q × VC/Q PCLDI = ILLM_DI × VDI Overtemperature Warning Two bits in the Status and Mode registers are set when the temperature of the device exceeds +115NC (typ). The OTempInt bit in the Status register is set and IRQ asserts when the OTemp bit in the Mode register is set. Read the Status register to clear the OTempInt bit and IRQ. The OTemp bit is cleared when the die temperature falls below +95NC. The device continues to operate normally unless the die temperature reaches the +150NC thermal shutdown threshold, when the device enters thermal shutdown. Thermal Shutdown When the die temperature rises above +150NC (typ) thermal shutdown threshold, the C/Q drivers and the C/Q and DI current loads are automatically turned off. The internal 3.3V and 5V LDOs remain on during thermal shutdown, if enabled. If the internal or external V5 supply remains on during thermal shutdown (which is always true in case of the internal V5 regulator), the register contents are maintained and SPI communication available. When the die temperature falls below the thermal shutdown threshold plus hysteresis, the C/Q driver and C/Q and DI current sinks turn on automatically. Ensure that the total power dissipation is less than the limits listed in the Absolute Maximum Ratings section. Use the following to calculate the power dissipation (in mW) due to the C/Q driver: PC/Q = [IC/Q]2 x [RO] 17 MAX14824 IO-Link Master Transceiver Register Functionality The device has four 8-bit-wide registers for configuration and monitoring (Table 1). R1 and R0 are the register address. Table 1. Register Summary REGISTER R1 R0 D7 D6 D5 D4 D3 D2 D1 D0 Status 0 0 X X DiLvl UV33Int UV24Int OTempInt 0 1 RxFilter HiSlew C/Q_N/P QLvl C/Q_PP C/QFaultInt CQConfig C/QDEn Q RxDis C/QLoad DIOConfig 1 0 X X X X X X LiDis DiLoad Mode 1 1 RST WuEnBit X C/QFault UV24 OTemp UV33En LDO33Dis R1/R0 = Register address, X = Unused bits. Status Register [R1, R0] = [0,0] Bit D7 D6 D5 D4 D3 D2 D1 D0 Bit Name X X DiLvl C/QFaultInt UV33Int UV24Int OTempInt Read/Write R R R QLvl R R R R R POR State Reset Upon Read 0 0 U U 0 0 0 0 Yes Yes No No Yes Yes Yes Yes X = Unused bits. U = Unknown. These bits are dependent on the DI logic and C/Q inputs. The Status register reflects the logic levels of C/Q and DI and shows the source of interrupts that cause an IRQ hardware interrupt. The IRQ interrupt is asserted when an alarm condition (OTemp, UV33En, UV24, C/QFault) is detected. All bits in the Status register are read-only. The interrupt bits return to the default state after the Status register is read. If a C/Q fault condition persists, the C/QFaultInt bit is immediately set after the Status register is read. BIT NAME DESCRIPTION D7:D6 X D5 DiLvl DI Logic Level. The DiLvl bit mirrors the current logic level at the DI input. It is the inverse of the LI output and is always active regardless of the state of the LiDis bit (Table 2). DiLvl does not affect IRQ. DiLvl is not changed when the Status register is read. D4 QLvl C/Q Logic Level. The QLvl bit is the inverse of the logic level at C/Q. QLvl is 1 when the C/Q input level is low (< 8V) and is 0 when the C/Q logic level is high (> 13V) (Table 3). QLvl remains active when the C/Q receiver is disabled (RxDis = 1). QLvl does not affect IRQ. QLvl is not changed when the Status register is read. D3 C/QFaultInt C/Q Fault Interrupt. The C/QFaultInt interrupt bit and C/QFault bit (in the Mode register) are set when a short circuit or voltage fault occurs on the C/Q driver output (see the C/Q Fault Detection section for more information). IRQ asserts when C/QFault is 1. Read the Status register to clear the C/QFaultInt bit and deassert IRQ. Unused 18 MAX14824 IO-Link Master Transceiver BIT NAME DESCRIPTION D2 UV33Int Internal 3.3V LDO (LDO33) Undervoltage Warning. Both the UV33Int interrupt bit and the UV33En bit (in the Mode register) are set when VLDO33 falls below the 2.4V LDO33 undervoltage threshold. If UV33En is set in the Mode register, IRQ asserts low when the UV33Int bit is 1. Read the Status register to clear the UV33Int bit and deassert IRQ. Set the UV33En bit to 1 in the Mode register to enable undervoltage monitoring for UV33Int. When enabled, UV asserts high when the UV33Int bit is 1. UV deasserts when VLDO33 rises above the LDO33 undervoltage threshold. D1 UV24Int VCC Undervoltage Interrupt. The UV24Int interrupt bit and the UV24 bit (in the Mode register) are set when the VCC voltage falls below the 7.4V undervoltage threshold. IRQ asserts low when the UV24Int bit is 1. Read the Status register to clear the UV24Int bit and deassert IRQ. VCC undervoltage detection cannot be disabled. D0 OTempInt Overtemperature Warning. The OTempInt interrupt bit and the OTemp bit (in the Mode register) are set when a high-temperature condition is detected by the device. OTemp is set when the temperature of the die exceeds +115NC (typ). OTempInt is set and IRQ asserts when the OTemp bit is 1. The OTempInt bit is cleared and IRQ deasserts when the Status register is read. Once cleared, OTempInt is not reset if the die temperature remains above the thermal warning threshold and does not fall below +95°C. Table 2. DiLvl and LI Output Table 3. QLvl and RX Output VDI (V) DiLvl BIT LI OUTPUT VC/Q (V) QLvl BIT RX OUTPUT < 5.2 0 >8 1 High <8 1 High Low >13 0 Low 19 MAX14824 IO-Link Master Transceiver CQConfig Register [R1, R0] = [0,1] Bit D7 D6 D5 D4 D3 D2 D1 D0 RxFilter HiSlew C/Q_N/P C/Q_PP C/QDEn Q RxDis C/QLoad Read/Write R/W R/W R/W R/W R/W R/W R/W R/W POR State 0 0 0 0 0 0 0 0 Bit Name Use the CQConfig register to control the C/Q receiver and driver parameters. All bits in the CQConfig register are read-write and are set to 0 at power-up. BIT NAME DESCRIPTION D7 RxFilter C/Q and DI Receiver Filter Control. The C/Q and DI receivers have analog lowpass filters to reduce high-frequency noise on the receiver inputs. Set the RxFilter bit to 0 to set the filter corner frequency to 500kHz. Set the RxFilter bit to 1 to set the filter corner frequency to 1MHz (this setting is used for highspeed COM3 operation). Noise filters on C/Q and DI are controlled simultaneously by the RxFilter bit. D6 HiSlew Slew-Rate Control. The HiSlew bit increases the slew rate for the C/Q driver and is used for high-speed COM3 (230kbps) data rates. Set HiSlew to 0 for COM1 and COM2 operation. D5 C/Q_N/P C/Q Driver NPN/PNP Mode. The C/Q_N/P bit selects between low-side (NPN) and high-side (PNP) modes when the C/Q driver is configured as an opendrain output (C/Q_PP = 0). Set C/Q_N/P to 1 to configure the driver for lowside (NPN) operation. Set C/Q_N/P to 0 for high-side (PNP) operation. D4 C/Q_PP C/Q Driver Push-Pull Operation. Set C/Q_PP to 1 to enable push-pull operation on the C/Q driver. The C/Q output is open drain when C/Q_PP is 0. D3 C/QDEn C/Q Driver Enable/Disable. Set the C/QDEn bit to 1 to enable the C/Q driver. Set C/QDEn to 0 for hardware (TXEN) control. See Table 4. D2 Q C/Q Driver Output Logic. The Q bit can be used to program the C/Q output driver through software. The C/Q driver must be enabled and TXC = TXQ must be high to control the C/Q driver through the Q bit (Figure 8). C/Q has the same logic polarity as the Q bit. Set the Q bit to 0 to control the C/Q driver with TXC and TXQ. The C/Q driver output state depends on the C/Q_PP and C/Q_N/P bits as shown in Table 5. Note that Table 5 assumes that the C/Q driver is enabled (TXEN = VL or C/QDEn = 1). D1 RxDis D0 C/QLoad C/Q Receiver Enable/Disable. Set the RxDis bit to 1 to disable the C/Q receiver. The RX output is high when RxDis is 1. C/Q Current Sink Enable. Set the C/QLoad bit to 1 to enable the internal current sink at C/Q. The C/Q current sink is automatically disabled while the C/Q driver is enabled (TXEN = high or C/QDEn = 1). This saves power. 20 MAX14824 IO-Link Master Transceiver Table 4. C/QDEn and TXEN C/Q Driver Control TXQ TXC C/QDEn TXEN C/Q DRIVER 0 Low Disabled X High Enabled 1 X Enabled C/Q Q Figure 7. Equivalent C/Q Logic X = Don’t care. Table 5. C/Q Driver Output State TXC AND TXQ (SEE NOTE) Q C/Q_PP C/Q_N/P C/Q CONFIGURATION High 1 0 0 PNP, open drain On, C/Q is high High 0 0 0 PNP, open drain Off, C/Q is high impedance High 1 0 1 NPN, open drain Off, C/Q is high impedance High 0 0 1 NPN, open drain On, C/Q is low High 1 1 X Push-pull High High 0 1 X Push-pull Low C/Q STATE Note: TXC and TXQ = VL. X = Don’t care. DIOConfig Register [R1, R0] = [1,0] Bit D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X LiDis DiLoad Read/Write R/W R/W R/W R/W R/W R/W R/W R/W POR State 0 0 0 0 0 0 0 0 Bit Name X = Unused bits. Use the DIOConfig register to control the DI and DO interfaces. All bits in the DIOConfig register are read-write and are set to 0 at power-up. BIT NAME D7:D2 X D1 LiDis D0 DiLoad DESCRIPTION Unused LI Output Enable/Disable. Set the LiDis bit to 1 to disable the LI output. The LI output is low when LiDis is 1. DI Current Sink Enable. Set the DiLoad bit to 1 to enable the internal current sink at the DI input. 21 MAX14824 IO-Link Master Transceiver Mode Register [R1, R0] = [1,1] Bit D7 D6 D5 D4 D3 D2 D1 D0 Bit Name RST WuEnBit X C/QFault UV24 OTemp UV33En LDO33Dis Read/Write R/W R/W R/W R R R R/W R/W POR State 0 0 0 0 0 0 0 0 X = Unused bits. Use the Mode register to reset the device and manage the 3.3V LDO. The Mode register has bits that represent the current status of fault conditions. When writing to the Mode register, the contents of the fault indication bits (bits 2 to 4) do not change. BIT NAME DESCRIPTION D7 RST Register Reset. Set RST to 1 to reset all registers to their default power-up state. Then set RST to 0 for normal operation. The Status register is cleared and IRQ deasserts (if asserted) when RST = 1. Interrupts are not generated while RST = 1. D6 WuEnBit Auto Wake-Up Polarity Enable. Drive the WUEN input high or set the WuEnBit bit to 1 to enable wake-up generation. When auto wake-up polarity is enabled, the device samples the logic state of C/Q and uses this as the basis for determining the subsequent wake-up pulse that is initiated through a high-to-low pulse on the TXQ and TXC inputs. Set the WuEnBit to 1 before a negative-going, 80µs (typ) wake-up pulse is transmitted to ensure that the device produces the correct polarity wake-up pulse on the C/Q output. For example, if C/Q is connected to a voltage high, then it pulls the line low for the wakeup pulse duration. If C/Q is connected to a voltage low, then it pulls the line high for the wake-up pulse duration. Clear WuEnBit after the wake-up has been generated (Table 6). D5 X D4 C/QFault C/Q Fault Status. The C/QFault bit is set when a short circuit or voltage fault occurs at the C/Q driver output (see the C/Q Fault Detection section for more information). The C/QFault and C/QFaultInt bits are both set when a fault occurs on C/Q. C/QFault is cleared when the fault is removed. D3 UV24 VCC Undervoltage Condition. Both the UV24 and the UV24Int bits are set when VCC falls below VCCUVLO. UV24 is cleared when VCC rises above the VCC threshold. V5 must be present for VCC undervoltage monitoring. D2 OTemp Temperature Warning. The OTemp bit is set when a high-temperature condition occurs on the device. Both the OTempInt interrupt in the Status register and the OTemp bit are set when the junction temperature of the die rises to above +115NC (typ). The OTemp bit is cleared when the junction temperature falls below +95NC (typ). D1 UV33En LDO33 UV Enable. Set the UV33En bit to 1 to assert the UV output when LDO33 voltage falls below the 2.4V (typ) undervoltage lockout threshold. The UV33En bit does not affect the UV33Int bit in the Status register; IRQ asserts when VLDO33 falls below VLDO33UVLO regardless of the state of UV33En. D0 LDO33Dis LDO33 Enable/Disable. Set LDO33Dis to 1 to disable the 3.3V linear regulator (LDO33). Unused 22 MAX14824 IO-Link Master Transceiver Table 6. Auto Wake-Up Polarity Generation WuEnBit WUEN 0 Low Normal operation MODE 0 High Wake-up generation mode 1 Low Wake-up generation mode 1 High Wake-up generation mode for the device is 12MHz. The SPI interface complies with clock polarity CPOL = 0 and clock phase CPHA = 0 (see Figure 8 and Figure 9). SPI Interface The device communicates through an SPI-compatible 4-wire serial interface. The interface has three inputs— clock (SCLK), chip select (CS), and data in (SDI)—and one output, data out (SDO). The maximum SPI clock rate The SPI interface is not available when V5 or VL is not present. CS SCLK SDI W 0 A3 A2 A1 R1 A0 R0 D7 D6 D5 D4 D3 D2 D1 D0 A_ = DEVICE ADDRESS R_ = REGISTER ADDRESS D_ = DATA BIT = CLOCK EDGE WHEN LOGIC IS LATCHED Figure 8. SPI Write Cycle CS SCLK SDI X R 0 A3 A2 A1 A0 SDO R1 R0 X D7 D6 D5 D4 D3 D2 D1 D0 A_ = DEVICE ADDRESS R_ = REGISTER ADDRESS D_ = DATA BIT = CLOCK EDGE WHEN LOGIC IS LATCHED = CLOCK EDGE AT WHICH LOGIC IS WRITTEN Figure 9. SPI Read Cycle 23 MAX14824 IO-Link Master Transceiver Address Selection The device includes four chip-select address inputs, A0–A3, allowing up to 16 devices on a single bus. Drive the address inputs high or low to program the device address as shown in Table 7. Do not leave any address input unconnected. Table 7. Address Input Selection A3 A2 A1 A0 DEVICE ADDRESS Low Low Low Low 0x00 Low Low Low High 0x01 Low Low High Low 0x02 Low Low High High 0x03 Low High Low Low 0x04 Low High Low High 0x05 Low High High Low 0x06 Low High High High 0x07 High Low Low Low 0x08 High Low Low High 0x09 High Low High Low 0x0A High Low High High 0x0B High High Low Low 0x0C High High Low High 0x0D High High High Low 0x0E High High High High 0x0F MICROCONTROLLER MAX14824 GPO TXQ TX TXC RTS RX TXEN Applications Information UART Interfacing The logic level of the MAX14824 microcontroller’s UART interface I/Os (TXC, TXQ, TXEN, and RX) is defined by VL. The device can be interfaced to microcontrollers whose on-board UART TX output cannot be programmed as a logic output (GPO). In this case, connect the TX output of the UART to the TXC input for IO-Link communication and connect a separate GPO output on the microcontroller to TXQ for standard IO (SIO) mode operation (Figure 10). As the TXQ and TXC inputs are internally logically ANDed, the unused input (TXC or TXQ) must be held high while the other is in operation. Transient Protection Inductive load switching, surges, ESD and short circuits create high transient voltages. C/Q and DI must be protected against high overvoltage and undervoltage transients. Positive voltage transients on DI must be limited to +55V relative to GND and negative voltage transients must be limited to -55V (relative to GND) on DI. Two Schottky diodes having low forward voltage, like the DLFS240, must be connected to C/Q to clamp under- and overvoltage transients. Figure 11 shows suitable protection to meet IEC 61000-4-2 ESD testing. For reduction of bit errors induced by burst transients, enable the receiver filters and add capacitors to C/Q and DI. If surge tests need to be met, a TVS diode is recommended on VCC. 1µF 270pF DFLS240 270pF DFLS240 VCC C/Q RX MAX14824 DI Figure 10. UART Interface 1nF GND SDC36C Figure 11. MAX14824 Operating Circuit with TVS Protection 24 MAX14824 IO-Link Master Transceiver EN IN MAX17501 LX GND FB 3.3V 1μF 1μF 10kΩ VCC GPIO2 UV VL TXQ LDO33 V5 LDOIN VCC 270pF SPI C/Q GPIO1 MICROCONTROLLER GND RX WUEN TXC RTS TXEN GPIO3 LI 1 2 RX TX L+ 270pF MAX14824 DI 1nF 4 3 L- GND Figure 12. Use an External Supply to Power the MAX14824 External Power The device is powered by VCC and the 5V regulator, V5. VL is a reference voltage input to set the logic levels of the microcontroller interface. The logic and SPI interface are operational when V5 and VL are present even if VCC is not present. Connect LDOIN to V5 to power the V5 input with an external supply (Figure 12). This configuration disables operation of the internal 5V regulator and reduces power consumption. 25 MAX14824 IO-Link Master Transceiver Typical Operating Circuits (continued) IO-LINK QUAD MASTER APPLICATION MISO MOSI CONTROLLER SCLK CS1 CS2 MAX14824 RST PORT 1 RX TXC TXEN ADDR 1 VEXT MAX14824 RST CS SCLK MOSI MISO TX0 RX0 RTS0 GPIO1 GPIO5 GPIO9 MAX14830 TX3 RX3 RTS3 XIN RX TXC TXEN TX1 RX1 RTS1 TX2 RX2 RTS2 GPIO13 PORT 2 ADDR 2 MAX14824 PORT 3 RX TXC TXEN ADDR 3 XOUT MAX14824 PORT 1 RX TXC TXEN ADDR 4 26 MAX14824 IO-Link Master Transceiver Ordering Information PART TEMP RANGE PIN-PACKAGE MAX14824GTG+ -40NC to +105NC 24 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 24 TQFN-EP T2444+4 21-0139 90-0022 27 MAX14824 IO-Link Master Transceiver Revision History REVISION NUMBER REVISION DATE 0 3/11 Initial release 6/11 Changed DI threshold to accommodate all three types of industrial sensors, added 24V supply connection in Figure 13 8/11 Corrected IO-Link trademark. Corrected block description in Functional Diagram. Corrected C/Q minimum and maximum ratings in the Absolute Maximum Ratings section. Corrected ICC maximum value and shuffled row parameters in the Electrical Characteristics Table. Replaced Figures 9 and 10. Added Maxim part number for DC-DC regulator. Corrected Transient Protection section. 1, 2, 3, 23, 24 5/12 Changed temperature rating; updated Typical Operating Circuits, Functional Diagram, and Figures 9, 11, and 12; updated TOCs 1, 2, and 16; changed parameters in Electrical Characteristics; updated Detailed Description and Application Information 1-7, 11, 13-17, 20, 23, 24, 24, 25, 27 1 2 3 DESCRIPTION PAGES CHANGED — 4, 19, 25 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 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