256Mb DDR SDRAM Ordering Information EM 42 AM 16 8 4 R T A – 75 L EOREX MEMORY EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM : : : : : : Power S : Standard L : Low power 40 41 42 43 46 48 Package F : Pb-free G: Green Density 32M : 32 Mega Bits 16M : 16 Mega Bits 8M : 8 Mega Bits 4M : 4 Mega Bits 2M : 2 Mega Bits 1M : 1 Mega Bit Min Cycle Time ( Max Freq.) -5 : 5ns ( 200MHz ) -6 : 6ns ( 167MHz ) -7 : 7ns ( 143MHz ) -75 : 7.5ns ( 133MHz ) -8 : 8ns ( 125MHz ) -10 : 10ns ( 100MHz ) Organization 4: 8: 9: x4 x8 x9 16 : x16 18 : x18 32 : x32 Refresh 1 : 1K 8 : 8K 2 : 2K 6 :16K 4 : 4K Bank 2 : 2Bank 6 : 16Bank 4 : 4Bank 3 : 32Bank 8 : 8Bank Interface V : 3.3V R : 2.5V Preliminary DCC-DD041157-3 Revision A : 1st B : 2nd C : 3rd D : 4th G : for VGA version only Package C : CSP B : uBGA T : TSOP Q : TQFP P : PQFP ( QFP ) L : LQFP 1/37 256Mb DDR SDRAM 256Mb( 4Banks ) Double Data Rate SDRAM EM42AM1684RTA ( 16Mx16 ) Description The EM42AM1684RTA is a high speed synchronous graphic RAM fabricated with ultra high performance CMOS process containing 268,435,456 bits which organized as 4 Banks, each banks has 8,192 rows x 512 columns x 16 bits. The 256Mb DDR SDRAM uses a double data rate architecture to accomplish high-speed operation. The data path internally prefetches multiple bits and it transfers the data for both rising and falling edges of the system clock. It means the doubled data bandwidth can be achieved at the I /O pins. Features • Internal Double-data-rate architecture with 2 accesses per clock cycle • 4 banks operation • Bi-directional, intermittent data strobe (DQS) • All inputs except data and DM are sampled at the positive edge of the system clock. • Data Mask (DM) for write data • Auto & self refresh supported • 8K Refresh cycle / 64ms • Burst length of 2,4,8 • Sequential & Interleaved Burst type available • 2,2.5, 3 Clock read latency • Auto Precharge option for each burst accesses • DQS edge-aligned with data for Read cycles • DQS center-aligned with data for Write cycles • DLL aligns DQ & DQS transitions with CLK transition • 2.5V+/- 0.2V VDD • 2.5V SSTL-2 compatible I/O Ordering Information Part Number Max. Frequency I/O Interface Package EM42AM1684RTA-5 200 MHz SSTL-2 66 pins, TSOPII EM42AM1684RTA-6 166 MHz SSTL-2 66 pins, TSOPII EM42AM1684RTA-75 133 MHz SSTL-2 66 pins, TSOPII * EOREX reserves the right to change products or specification without notice. Preliminary DCC-DD041157-3 2/37 256Mb DDR SDRAM Pin Assignment ( Top View ) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD /QFC/NC LDM /WE /CAS /RAS /CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS 66pin TSOP-II (400mil x 875 mil) (0.65mm Pin pitch) Preliminary DCC-DD041157-3 3/37 256Mb DDR SDRAM Pin Descriptions ( Simplified ) Pin CLK, /CLK Name System Clock Pin Function Clock input active on the Positive rising edge except for DQ and DM are active on both edge of the DQS. Clock and /Clock are differential clock inputs. /CS Chip select /CS enables the command decoder when “L” and disabled the command decoder when “H”. The new commands are overlooked when the command decoder is disabled but previous operation will still continue. CKE Clock Enable Activates the CLK when “H” and deactivates when “L”. when deactivate the clock, CKE low signifies the power down or self refresh mode. A0 ~ A12 Address Row address (A0 to A12) and Column address (CA0 to CA8) are multiplexed on the same pins. CA10 defines auto precharge at Column address . BA0, BA1 Bank Address /RAS Row address strobe /CAS Column address strobe Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. /WE Write Enable Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. LDQS,UDQS Data input/output LDM,UDM Data input/output Mask /QFC Data output DQ0 ~ 15 Data input/output VDD/VSS Power supply/Ground VDD and VSS are power supply pins for internal circuits. VDDQ/VSSQ Power supply/Ground VDDQ and VSSQ are power supply pins for the output buffers. NC/ RFU VREF No connection / Reserved for Future Use Input Selects which bank is to be active. Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. Data Inputs and Outputs are synchronized with both edge of DQS. DM controls data inputs. LDM corresponds to the data on DQ0-DQ7. UDM corresponds to the data on DQ8-DQ15 FET Control : EMRS Option output during every Read and Write access. It can be used to control isolation switches on modules. Data inputs and outputs are multiplexed on the same pin. This pin is recommended to be left No Connection on the device. SSTL-2 Reference voltage for input buffer. Preliminary DCC-DD041157-3 4/37 256Mb DDR SDRAM Block Diagram Row Decoder Row Add. Buffer Write DQM Control Address Register A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BA0 BA1 DM Auto/Self Refresh Counter Memory Array Data In S/A & I/O gating DQi Col. Decoder Data Out Col. Add. Buffer Mode Register Set (Extended M-R-S) Col. Add. Counter Burst Counter Timing Register CLK /CLK CKE /CS /RAS /CAS /WE DM Preliminary DCC-DD041157-3 DQS 5/37 256Mb DDR SDRAM Simplified State Diagram Self Refresh SE LF SE Mode Register Set MRS CK CK ACT CK CK CBR (Auto) Refresh EL EH Power Down EL EH Row Active READ Write Re ad A Read h wit Wr i te BS T ad ad Read WRITE Re Re wit h Write ite Wr A READA E PR PR E WRITEA B POWER ON it Ex REF IDLE Power Down LF PRE/PALL st ur en d Precharge Manual Input Automatic Sequence Preliminary DCC-DD041157-3 6/37 256Mb DDR SDRAM Absolute Maximum Ratings Symbol Item Rating Units VIN, VOUT Input, Output Voltage -0.3 ~ 3.6 V VDD, VDDQ Power Supply Voltage -0.3 ~ 3.6 V TOP Operating Temperature 0 ~ 70 C TSTG Storage Temperature -55 ~ 150 C PD Power Dissipation 1 W IOS Short Circuit Current 50 mA Note : Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operation Conditions ( Ta = 0 ~ 70 C ) Symbol Parameter Min. Typical Max. Units VDD Power Supply Voltage 2.3 2.5 2.7 V VDDQ Power Supply Voltage (for I/O Buffer) 2.3 2.5 2.7 V VREF I/O Logic high voltage 1.15 1.25 1.35 V VTT I/O Termination voltage VREF-0.04 - VREF+0.04 V VIH Input Logic high voltage VREF+0.18 - VDDQ+0.3 V VIL Input Logic low voltage -0.3 - VREF-0.18 V Capacitance ( Vcc =2.5V, f = 1MHz, Ta = 25 C ) Symbol Parameter Min. Max. Units CCLK Clock capacitance ( CLK, /CLK ) 2.5 4.0 pF CI Input capacitance for CKE, Address, /CS, /RAS, /CAS, /WE 2.5 4.5 pF CO DM , Data & DQS Input/Output capacitance 4.0 6.5 pF Preliminary DCC-DD041157-3 7/37 256Mb DDR SDRAM Recommended DC Operating Conditions ( Ta = 0 ~ 70 C ) Parameter Symbol Speed Test condition -5 -6 -75 110 95 85 Units Notes Operating current IDD1 Burst length = 2, tRC ≥ tRC (min), IOL = 0 mA, One bank active Precharge standby current in power down mode IDD2P CKE ≤ VIL (max.), tCk = min 4.5 mA Precharge standby current in non-power down mode IDD2N CKE ≥ VIH (min.), tCK = min, /CS ≥ VIH (min.) Input signals are changed one time during 2clks 40 mA Active standby current in power down mode IDD3P CKE ≤ VIL(max.), tCK = min 15 mA Active standby current in non-power down mode IDD3N CKE ≥ VIH(min), tCK = min, / CS ≥ VIH(min) Input signals are changed one time during 2clks 45 mA Operating current ( Burst mode ) IDD4 tCK ≥ tCK(min.), IOL = 0 mA All banks active Refresh current IDD5 tRC ≥ tRFC(min.), All banks active Self Refresh current IDD6 CKE ≤ 0.2V READ 100 WRITE 110 160 2 2 mA 1 mA 1 mA 2 mA Note : 1. IDD1 and IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. 2. Min. of tRFC ( Auto Refresh Row Cycle Times ) is shown at AC Characteristics. Preliminary DCC-DD041157-3 8/37 256Mb DDR SDRAM Recommended DC Operating Conditions ( Continued ) Parameter Symbol Min. Max. Unit Note Input leakage current ILI -5 5 uA 1 Output leakage current ILO -5 5 uA 2 High level output voltage VOH VTT + 0.76 - V IOH=-15.2mA Low level output voltage VOL - VTT - 0.76 V IOH=-15.2mA Note : 1. VIN= 0 to 3.6V All other pins are not tested under VIN= 0V. 2. DOUT is disabled, VIN= 0 to 2.7V. Preliminary DCC-DD041157-3 9/37 256Mb DDR SDRAM Operating AC Characteristics ( VDD = 2.5V +/- 0.2 V, Ta = 0 ~ 70 C ) -5 -6 -75 Parameter Symbol DQ output access from CLK, /CLK tDQCK -0. 5 +0. 5 -0.7 +0.7 -0.75 +0.75 ns DQS output access from CLK, /CLK tDQSCK -0. 5 +0. 5 -0.6 +0.6 -0.75 +0.75 ns CK low / high level width tCL,tCH 0.45 0.55 0.45 0.55 0.45 0.55 Clock cycle time Min. Max. Min. Max. Min. Max. Units tCK CL=2 7.5 12 6 12 7.5 12 ns CL=2.5 6 12 6 12 7.5 12 ns tCK DQ and DM hold / setup time tDH,tDS 0.4 0.45 0.5 ns DQ and DM input pulse width for each input tDIPW 1.75 1.75 1.75 ns Data out high / low impedance time from CLK, /CLK tHZ, tLZ -0.7 -0.7 +0.7 -0.75 +0.75 ns DQS-DQ skew for associated DQ signal tDQSQ Write command to first latching DQS transition tDQSS DQS input valid window tDSL, tDSH 0.35 0.35 0.35 tCK Mode Register Set command cycle time tMRD 2 2 2 tCK Write Preamble setup time tWPRES 0 0 0 ns Write Postamble tWPST Address /control input hold / setup time tIH,tIS Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK Active to Precharge command period tRAS 40 70K 42 70K 45 70K ns Active to Active command period tRC 55 60 65 ns Auto Refresh Row Cycle Time tRFC 70 72 75 ns Active to Read or write delay tRCD 15 18 20 ns Precharge command period tRP 15 18 20 ns Active bank A to B command period tRRD 10 12 15 ns Column address to column address delay tCCD 1 1 1 tCK +0.7 0.4 0.7 0.5 0.45 ns 1.25 0.75 1.25 0.75 1.25 0.4 0.6 0.4 0.7 0.6 0.4 0.8 Preliminary DCC-DD041157-3 0.6 1.0 tCK tCK ns 10/37 256Mb DDR SDRAM Operating AC Characteristics ( Continued ) ( VDD = 2.5V +/- 0.2 V, Ta = 0 ~ 70 C ) -75 -8 -10 Parameter Symbol Last data in to Read command tCDLR Last data in to Write command tCDLW 0 0 0 tCK Last data in to Precharge Command tDPL 2 2 2 tCK Exit self Refresh to non-read command tXSNR 75 75 75 ns Exit self Refresh to read command tXSRD 200 200 200 ns Average periodic refresh interval tREFI /QFC preamble during reads tQPRE 0.9 1.1 0.9 1.1 /QFC postamble during reads tQPST 0.4 0.6 0.4 0.6 /QFC output access time from CK/ /CK tQCK /QFC output hold time tQOH Min. Max. Min. Max. Min. Max. 2.5tCK-tDQSS 2.5tCK-tDQSS 2.5tCK-tDQSS 15.6 15.6 0 0.4 0.4 us 0.9 1.1 tCK 0.4 0.6 tCK Preliminary DCC-DD041157-3 0 0.6 tCK 15.6 0 0.6 Units 0.4 ns 0.6 tCK 11/37 256Mb DDR SDRAM Truth Table 1. Command Truth Table Command Symbol Ignore Command No operation Burst stop Read Read with auto pre-charge Write Write with auto pre-charge Bank activate Pre-charge select bank Pre-charge all banks Mode register set CKE /CS /RAS /CAS /WE BA0, A10 BA1 A12 ~A0 n-1 n DESL H X H X X X X X X NOP H X L H H H X X X BSTH H X L H H L X X X READ H X L H L H V L V READA H X L H L H V H V WRIT H X L H L L V L V WRITA H X L H L L V H V ACT H X L L H H V V V PRE H X L L H L V L X PALL H X L L H L X H X MRS H X L L L L L L V Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 2. CKE Truth Table Command Idle Idle Command Symbol CKE n-1 n /CS /RAS /CAS /WE Addr. CBR refresh command REF H H L L L H X Self refresh entry SELF H L L L L H X L H L H H H X L H H X X X X Self refresh Self refresh exit Idle Power down Power down entry H L X X X X X Power down exit L H X X X X X Remark H = High level, L = Low level, X = High or Low level ( Don't care ) Preliminary DCC-DD041157-3 12/37 256Mb DDR SDRAM 3. Operative Command Table Current state Idle Row active /CS /R /C /W Command Action Notes H X X X X DESEL NOP L H H H X NOP NOP L H H L X TERM NOP L H L X BA/CA/A10 READ/WRIT/BW L L H H BA/RA ACT L L H L BA/A10 PRE/PREA NOP 3 L L L H X REFA Auto refresh 4 L L L L Op-Code, Mode-Add MRS Mode register 5 ILLEGAL X X X X DESEL NOP L H H H X NOP NOP L H H L X TERM NOP L H L H BA/CA/A10 READ/READA Begin Read, Latch CA, Determine auto-precharge L H L L BA/CA/A10 WRITE/WRITEA Begin Write, Latch CA, Determine auto-precharge L L H H BA/RA ACT L L H L BA/A10 PRE/PREA L L L H X REFA ILLEGAL L Op-Code, Mode-Add MRS ILLEGAL L L ILLEGAL X X X X DESEL NOP ( Continue burst to end ) L H H H X NOP NOP ( Continue burst to end ) L H H L X TERM L H L H BA/CA/A10 READ/READA L H L L L L H H BA/RA ACT L L H L BA/A10 PRE/PREA L L L H X REFA ILLEGAL L Op-Code, Mode-Add MRS ILLEGAL L L 1 Precharge / Precharge all H L 1 Bank active , Latch RA H L Read Addr. Terminal burst Terminal burst. Latch CA,Begin new read, Determine Auto-precharge ILLEGAL 1 Terminate burst, Precharge Remark: H =High Level, L=Low level, X=High or Low level ( Don’t care ), AP= Auto Precharge Preliminary DCC-DD041157-3 13/37 256Mb DDR SDRAM Current state Write Read with Autoprecharge Write with Autoprecharge /CS /R /C /W Addr. Command Action H X X X X DESEL NOP ( Continue burst to end ) L H H H X NOP NOP ( Continue burst to end ) L H H L X TERM L H L H BA/CA/A10 READ/READA L H L L BA/CA/A10 WRITE/WRITEA L L H H BA/RA ACT L L H L BA/A10 PRE/PREA L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL Notes ILLEGAL Terminate burst with DM=“H”, Latch CA , Begin read,Determine auto-precharge 5 2 Terminate burst , Latch CA ,Begin new write, Determine auto-precharge 5 2 ILLEGAL 1 Terminate burst with DM=“H”, Precharge 5 H X X X X DESEL NOP ( Continue burst to end ) L H H H X NOP NOP ( Continue burst to end ) L H H L BA/CA/A10 TERM ILLEGAL L H L X BA/RA READ/WRITE ILLEGAL 1 L L H H BA/A10 ACT ILLEGAL 1 L L H L X PRE/PREA ILLEGAL 1 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Continue burst to end ) L H H H X NOP NOP (Continue burst to end ) L H H L X TERM ILLEGAL L H L X BA/CA/A10 READ/WRITE ILLEGAL L L H H BA/RA ACT ILLEGAL 1 1 L L H L BA/A10 PRE/PREA ILLEGAL 1 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL Remark: H =High Level, L=Low level, X=High or Low level ( Don’t care ), AP= Auto Precharge Preliminary DCC-DD041157-3 14/37 256Mb DDR SDRAM Current state Write recovering Refreshing /CS /R /C /W Row activating Command Action Notes H X X X X DESEL NOP L H H H X NOP NOP L H H L X TERM NOP L H L H BA/CA/A10 READ ILLEGAL 1 L L H L L H L H BA/CA/A10 BA/RA WRITE/WRITEA ACT New write, Determine AP ILLEGAL 1 L L H L BA/A10 PRE/PREA ILLEGAL 1 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP ( ldle after tRP) L H H H X NOP NOP ( ldle after tRP) L H H L X TERM L H L X BA/CA/A10 READ/WRITE ILLEGAL L L H H BA/RA ACT ILLEGAL L L H L BA/A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL L Op-Code, Mode-Add MRS ILLEGAL L Precharging Addr. L L NOP H X X X X DESEL NOP ( Idle after tRP ) L H H H X NOP NOP ( Idle after tRP ) L H H L X TERM L H L X BA/CA/A10 READ/WRITE ILLEGAL 1 L L H H BA/RA ACT ILLEGAL 1 L L H L BA/A10 PRE/PREA NOP( Idle after tRP ) 3 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL NOP H X X X X DESEL NOP (Row active after tRCD) L H H H X NOP NOP (Row active after tRCD) L H H L X TERM L H L X BA/CA/A10 READ/WRITE ILLEGAL L L H H BA/RA ACT ILLEGAL 1 1 L L H L BA/A10 PRE/PREA ILLEGAL 1 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL NOP Remark: H =High Level, L=Low level, X=High or Low level ( Don’t care ), AP= Auto Precharge Note 1. ILLEGAL to bank in specified state: → Function may be legal in the Bank indicated by Bans Address (BA), depending on the state of the bank. 2. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 3. NOP to bank precharging or in idle sate. May precharge bank indicated by BA. 4. ILLEGAL of any bank is not idle. Preliminary DCC-DD041157-3 15/37 256Mb DDR SDRAM 4. Command Truth Table for CKE Current state Self refreshing Both bank precharge power down All Banks Idle Any state other than listed above CKE /CS /R /C /W Addr. Action Notes n-1 n H X X X X X X INVALID L H H X X X X Exist Self-Refresh 1 L H L H H H X Exist Self-Refresh 1 L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP ( Maintain Self-refresh ) H X X X X X X INVALID L H H X X X X Exist Power down 2 L H L H H H X Exist Power down 2 L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP ( Maintain Power down ) H H X X X X X Refer to function true table H L H X X X X Enter power down 3 H L L H H H X Enter power down 3 H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L H H RA H L L L L H X H L L L L L OP Code Mode register access Special mode register access Row active / Bank active Enter self-refresh H L L L L L Op-Code L X X X X X X Refer to current state H H X X X X X Refer to command truth table 3 Remark : H = High level, L = Low level, X = High or Low level (Don't care) Notes 1. After CKE’s low to high transition to exist self refresh mode. And a time of tRC (min) has to be elapse after CKE’s low to high transition to issue a new command. 2. CKE low to high transition is asynchronous as if restarts internal clock. 3. Power down and self refresh can be entered only from the idle state of all blanks. Preliminary DCC-DD041157-3 16/37 256Mb DDR SDRAM Mode Register Definition Mode Register Set The mode register stores the data for controlling the various operating modes of DDR SDRAM which contains addressing mode, burst length, /CAS latency, test mode, DLL reset and various vendor’s specific opinions. The defaults values of the register is not defined, so the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE and BA0 ( The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register. ) The state of the address pins A0-A12 in the same cycle as /CS, /RAS, /CAS, /WE and BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operating as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0-A2, addressing mode uses A3, /CAS latency ( read latency from column address ) uses A4-A6. A7 is used for test mode. A8 is used for DDR reset. A7 must be set to low for normal MRS operation. MRS Cycle 0 1 2 3 4 NOP Precharge All Banks NOP MRS NOP 5 6 7 8 CLK, /CLK Command tRP Any Command NOP NOP NOP 2 CLK Preliminary DCC-DD041157-3 17/37 256Mb DDR SDRAM Address Input for Mode Register Set BA1 BA0 A12/11 A10 A9 A8 RFU TM A8 0 1 BA0 0 1 A7 A6 A5 A4 A3 CAS Latency BT Sequential Reserved 2 4 8 Reserved Reserved Reserved Reserved DLL Reset No Yes An – A0 MRS Cycle EMRS A7 0 1 A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A1 A0 Burst Length Burst Length Interleave A2 Reserved 0 2 0 4 0 8 0 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Burst Type Sequential Interleave CAS Latency Reserved Reserved 2 Reserved Reserved Reserved 2.5 Reserved A2 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 A3 0 1 A4 0 1 0 1 0 1 0 1 Operation Mode Normal Test Preliminary DCC-DD041157-3 18/37 256Mb DDR SDRAM Burst Type ( A3 ) Burst Length 2 4 8 A2 A1 A0 XX0 XX1 X00 X01 X10 X11 000 001 010 011 100 101 110 111 Sequential Addressing 01 10 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456 Interleave Addressing 01 10 0123 1032 2301 3210 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210 * Page length is a function of I/O organization and column addressing DLL Enable / Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disable the DLL for the purpose of debug or evaluation ( upon existing Self Refresh Mode, the DLL is enable automatically. ) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Output Drive Strength The normal drive strength got all outputs is specified to be SSTL-2, Class II. Some vendors might also support a weak drive strength option, intended for lighter load and/or point to point environments. Preliminary DCC-DD041157-3 19/37 256Mb DDR SDRAM Extended Mode Register Set ( EMRS ) The Extended mode register stores the data enabling or disabling DLL. The value of the extended mode register is not defined, so the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA0 ( The DDR SDRAM should be in all bank precharge with CKE already prior to writing into the extended mode register. ) The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE going low is written in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. High on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. BA1 BA0 RFU A12/11 A10 A9 1 A8 A7 A6 A5 A4 RFU : Must be set as 0 A3 A2 An – A0 MRS Cycle EMRS A0 /QFC D.I.C DLL A0 0 1 BA0 0 1 A1 DLL Enable Enable Disable Output Driver Impedance Control Normal 0 Weak 1 QFC Control Disable 0 Enable 1 Preliminary DCC-DD041157-3 20/37 256Mb DDR SDRAM /QFC Function /QFC Definition When drive low in reads coincident with the start of DQS, this DRAM output signal says that one cycle later there will be the first valid DQS output and returned on Hi-Z after this finishing a burst operation. It is also driven low shortly after a write command is received and returned to Hi-Z shortly after the last data strobe transition is received. Whenever the device is in standby, the signal is Hi-Z. DQS is intended to enable an external data switch. QFC can be enabled or disabled through EMRS control. /QFC Timing or Read Operation QFC on reads is enabled coincident with the start of DQS preamble, and disabled coincident with the end of DQS postamble 0 1 2 3 4 5 6 7 8 CLK, /CLK Command Read DQS Dout0 DQS Dout1 Hi-Z tQPRE /QFC tQPST CL=2. BL=2 Preliminary DCC-DD041157-3 21/37 256Mb DDR SDRAM /QFC Timing on Write Operation with tDQSSmax /QFC on writes is enabled as soon as possible after the clock edge of write command and disabled as soon as possible after the last DQS-in low going edge. 0 1 2 3 4 5 6 7 8 CLK, /CLK Write Command DQS@tDQSmax DQS@tDQSSmax Dout0 Dout1 Hi-Z /QFC tQCK tQOH BL=2 Preliminary DCC-DD041157-3 22/37 256Mb DDR SDRAM /QFC Timing on Write Operation with tDQSSmin /QFC on writes is enabled as soon as possible after the clock edge of write command and disabled as soon as possible after the last DQS-in low going edge. 0 1 2 3 4 5 6 7 8 CLK, /CLK Write Command DQS@tDQSmin DQS@tDQSSmin Dout0 Dout1 Hi-Z /QFC tQCK tQOH BL=2 Preliminary DCC-DD041157-3 23/37 256Mb DDR SDRAM Package Dimension 1.20 MAX 0.047 11.76 +/- 0.20 1.00+/- 0.10 0.039+/- 0.004 0.05 MIN 0.002 0.30 +0.08 / -0.08 0.012+0.003 / -0.003 PIN #1 0.125 +0.075 / -0.035 0.005+0.003 / -0.001 10.16 0.400 0 – 8’ 0.50 0.020 0.45 – 0.75 0.018 – 0.030 0.25 TYP 0.010 0.10 MAX 0.004 0.71 0.028 0.65 0.0256 22.22+/- 0.10 0.875+/- 0.004 22.62 MAX 0.891 0.21+/- 0.05 0.008+/- 0.002 0.463 +/- 0.008 * EOREX reserves the right to change products or specification without notice. Preliminary DCC-DD041157-3 24/37