EM42CM1684RTA Revision History Revision 0.1 (Jan. 2012) - First release. Jan. 2012 www.eorex.com 1/22 EM42CM1684RTA 1Gb (16M×4Bank×16) Double DATA RATE SDRAM Features Description • Internal Double-Date-Rate architecture with twice accesses per clock cycle. • Single 2.5V ±0.2V Power Supply • 2.5V SSTL-2 compatible I/O • Burst Length (B/L) of 2, 4, 8 • CAS Latency: 3 • Bi-directional data strobe (DQS) for input and output data, active by both edges • Data Mask (DM) for write data • Sequential & Interleaved Burst type available • Auto precharge option for each burst accesses • DQS edge-aligned with data for Read cycles • DQS center-aligned with data for Write cycles • DLL aligns DQ & DQS transitions with CLK transition • Auto Refresh and Self Refresh • 8,192 Refresh Cycles / 64ms The EM42CM1684RTA is high speed Synchronous graphic RAM performance fabricated CMOS with ultra process high containing 1,073,741,824 bits which organized as 16Meg words x 4 banks by 16 bits. The 1Gb DDR SDRAM uses double data rate architecture to accomplish high-speed operation. The data path internally prefetches multiple bits and transfers the data for both rising and falling edges of the system clock. It means the doubled data bandwidth can be achieved at the I/O pins. Available package: TSOPII 66P 400mil. Ordering Information Package Grade Pb EM42CM1684RTA-75F Part No Organization 64M X 16 133MHz @CL3-3-3 Max. Freq 66pin TSOP(ll) Commercial Free EM42CM1684RTA-6F 64M X 16 166MHz @CL3-3-3 66pin TSOP(ll) Commercial Free * EOREX reserves the right to change products or specification without notice. Jan. 2012 www.eorex.com 2/22 EM42CM1684RTA Pin Assignment 66pin TSOP-II Jan. 2012 www.eorex.com 3/22 EM42CM1684RTA Pin Description (Simplified) Pin Name 45,46 CLK,/CLK 24 /CS 44 CKE 29~32,35~40 ,28,41,42,17 A0~A13 26, 27 BA0, BA1 23 /RAS 22 /CAS 21 /WE 16/51 LDQS/UDQS 20/47 LDM/UDM 2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65 1,18,33/ 34,48,66 3, 9, 15, 55.61/ 6, 12, 52, 58,64 14,19,25,43, 50,53 49 DQ0~DQ15 VDD/VSS VDDQ/VSSQ NC/RFU VREF Function (System Clock) Clock input active on the Positive rising edge except for DQ and DM are active on both edge of the DQS. CLK and /CLK are differential clock inputs. (Chip Select) /CS enables the command decoder when”L” and disable the command decoder when “H”. The new command are overLooked when the command decoder is disabled but previous operation will still continue. (Clock Enable) Activates the CLK when “H” and deactivates when “L”. When deactivate the clock, CKE low signifies the power down or self refresh mode. (Address) Row address (A0 to A13) and Column Address (CA0 to CA9) are multiplexed on the same pin. CA10 defines auto precharge at Column Address. (Bank Address) Selects which bank is to be active. (Row Address Strobe) Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. (Column Address Strobe) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Write Enable) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Data Input/Output) Data Inputs and Outputs are synchronized with both edge of DQS. (Data Input/Output Mask) DM controls data inputs. LDM corresponds to the data on DQ0~DQ7.UDM corresponds to the data on DQ8~DQ15. (Data Input/Output) Data inputs and outputs are multiplexed on the same pin. (Power Supply/Ground) VDD and VSS are power supply pins for internal circuits. (Power Supply/Ground) VDDQ and VSSQ are power supply pins for the output buffers. (No Connection/Reserved for Future Use) This pin is recommended to be left No Connection on the device. (Input) SSTL-2 Reference voltage for input buffer. Jan. 2012 www.eorex.com 4/22 EM42CM1684RTA Absolute Maximum Rating Symbol VIN, VOUT VIN VDD, VDDQ Item Input, Output (I/O) Voltage Rating Units -0.5 ~ VDDQ + 0.5 V Input Voltage -1.0 ~ +3.6 Power Supply Voltage -1.0 ~ +3.6 TOP Operating Temperature Range TSTG Storage Temperature Range Commercial V °C 0 ~ +70 -55 ~ +150 °C PD Power Dissipation 1.6 W IOS Short Circuit Current 50 mA Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA=-0°C ~+70°C) Symbol Parameter Min. Typ. Max. Units VDD Power Supply Voltage 2.3 2.5 2.7 V VDDQ Power Supply Voltage (for I/O Buffer) 2.3 2.5 2.7 V VREF I/O Logic high Voltage 0.49*VDDQ 0.5*VDDQ 0.51*VDDQ V VTT I/O Termination Voltage VREF-0.04 - VREF+0.04 V VIH Input Logic High Voltage VREF+0.15 - VDDQ+0.3 V VIL Input Logic Low Voltage -0.3 - VREF-0.15 V Jan. 2012 www.eorex.com 5/22 EM42CM1684RTA Recommended DC Operating Conditions (VDD=2.5V±0.2V) Symbol Parameter Max. Test Conditions (Note 1) Units -6 -75 Burst length=2, tRC≥tRC(min.), IOL=0mA, One bank active 195 180 mA IDD1 Operating Current IDD2P Precharge Standby Current in Power Down Mode CKE≤VIL(max.), tCK=min 15 15 mA IDD2N Precharge Standby Current in Non-power Down Mode (All banks idle) CKE≥VIH(min.), tCK=min, /CS≥VIH(min.), VIN=VREF Input signals are changed once per clock cycle 65 60 mA IDD3P Active Standby Current in Power Down Mode CKE≤VIL(max.), tCK=min One bank active, VIN=VREF 35 30 mA IDD3N Active Standby Current in Non-power Down Mode CKE≥VIH(min.), tCK=min, /CS≥VIH(min.) Input signals are changed once per clock cycle 65 65 mA IDD4 Operating Current READ 220 200 WRITE 230 210 IDD5 Refresh Current 340 330 mA IDD6 Self Refresh Current CKE≤0.2V 9 9 mA IDD7 Operating current (Four Banks) Four Banks interleaving, BL=4 525 485 mA tCK ≥ tCK(min.), IOL=0mA, One banks active, BL=2 (Note 2) (Note 3) tRC≥ tRFC (min.), All banks active mA *All voltages referenced to VSS. Note 1: IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 2: IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 3: Min. of tRFC (Auto refresh Row Cycle Times) is shown at AC Characteristics. Recommended DC Operating Conditions (Continued) Symbol Parameter Test Conditions Min. Max. Units IIL Input Leakage Current 0≤VI≤VDDQ, VDDQ=VDD All other pins not under test=0V -2 +2 uA IOL Output Leakage Current 0≤VO≤VDDQ, DOUT is disabled -5 +5 uA VOH High Level Output Voltage IOUT = -16.8mA 1.95 - mA VOL Low Level Output Voltage IOUT = +16.8mA - 0.35 mA Jan. 2012 www.eorex.com 6/22 EM42CM1684RTA Block Diagram Auto/ Self Refresh Counter A0 A1 DM A2 A5 A6 A7 A8 A9 Address Register A4 Row Decoder Row Add. Buffer A3 Memory Array Write DQM Control Data In DOi S/ A & I/ O Gating A10 A11 Data Out Col. Decoder A12 BA0 BA1 Col. Add. Buffer Mode Register Set Col Add. Counter Burst Counter Timing Register /CK CK CKE /CS / RAS / CAS Jan. 2012 /WE DM DQS www.eorex.com 7/22 EM42CM1684RTA AC Operating Test Conditions 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input low (high) level. AC Input Operating Conditions Symbol Parameter Min. Typ. Max. Units VIH (AC) Input (DQ,DQS &DM) High Voltage VREF+0.31 - - V VIL (AC) Input (DQ,DQS &DM) Low Voltage - - VREF-0.31 V VID (AC) Input Differential (CK & /CK) Voltage 0.7 - VDDQ+0.6 V VIX (AC) Input Crossing Point (CK & /CK) 0.5*VDDQ-0.2 - 0.5*VDDQ+0.2 V Jan. 2012 www.eorex.com 8/22 EM42CM1684RTA AC Operating Test Characteristics (VDD=2.5V±0.2V) Symbol -6 Parameter -75 tDQCK DQ output access from CLK,/CLK tDQSCK DQS output access from CLK,/CLK -0.6 0.6 -0.75 0.75 ns tCL,tCH CL low/high level width 0.45 0.55 0.45 0.55 tCK 6 12 7.5 12 ns DQ and DM hold/setup time 0.45 - 0.5 - ns tDIPW DQ and DM input pulse width for each input 1.75 - 1.75 - ns tHZ,tLZ Data out high/low impedance time from CLK,/CLK -0.7 0.7 -0.75 0.75 ns tDQSQ DQS-DQ skew for associated DQ signal - 0.4 - 0.5 ns tDQSS Write command to first latching DQS transition 0.75 1.25 0.75 1.25 tCK DQS input valid window 0.35 - 0.35 - tCK Mode Register Set command cycle time 2 - 2 - tCK tWPRES Write Preamble setup time 0 - 0 - ns tWPST Write Postamble 0.4 0.6 0.4 0.6 tCK Address/control input hold/setup time (Slow) 0.8 - 1 - ns Address/control input hold/setup time (Fast) 0.75 - 0.9 - ns tRPRE Read Preamble 0.9 1.1 0.9 1.1 tCK tDSH DQS falling edge from CLK rising, hold time 0.2 - 0.2 - tCK tDSS DQS falling edge to CLK rising, setup time 0.2 - 0.2 - tCK tCK tDH,tDS tDSL,tDSH tMRD tIH,tIS Clock Cycle Time CL=3 Jan. 2012 Max. 0.7 Min. -0.75 Max. 0.75 Units Min. -0.7 ns www.eorex.com 9/22 EM42CM1684RTA AC Operating Test Characteristics (Continued) (VDD=2.5V±0.2V) Symbol -6 Parameter Min. 0.4 Max. 0.6 -75 Min. Max. 0.4 0.6 Units tRPST Read Postamble tCK tRAS Active to Precharge command period 42 70k 45 120k ns tRC Active to Active command period 60 - 65 - ns tRFC Auto Refresh Row Cycle Time 72 - 75 - ns tRCD Active to Read or Write delay 18 - 20 - ns tRP Precharge command period 18 - 20 - ns tRRD Active bank A to B command period 12 - 15 - ns tRAP tWPRE Active to READ with Auto Precharge command DQS write Preamble 18 0.25 - 20 0.25 - ns tCK tWR Write Recovery time 15 - 15 - ns tWTR Internal WRITE to READ command delay 1 - 1 - tCK tXSNR Exit self Refresh to non-read command 75 - 75 - ns tXSRD Exit self Refresh to read command 200 - 200 - tCK tREFI Average periodic refresh interval - 7.8 - 7.8 us Jan. 2012 www.eorex.com 10/22 EM42CM1684RTA Simplified State Diagram Jan. 2012 www.eorex.com 11/22 EM42CM1684RTA 1. Command Truth Table CKE Command Symbol n1 /CS /RAS /CAS /WE BA0, BA1 N A10 A12~A0 Ignore Command DESL H X H X X X X X X No Operation NOP H X L H H H X X X Burst Stop BSTH H X L H H L X X X Read READ H X L H L H V L V Read with Auto READ H X L H L H V H V WRIT H X L H L L V L V WRITA H X L H L L V H V ACT H X L L H H V V V PRE H X L L H L V L X PALL H X L L H L X H X MRS H X L L L L OP Code EMRS H X L L L L OP Code Pre-charge A Write Write with Auto Pre-charge Bank Activate Pre-charge Select Bank Pre-charge All Banks Mode Register Set Extended MRS H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 2. CKE Truth Table Item Command Symbol CKE n-1 n /CS /RAS /CAS /WE Addr. Idle CBR Refresh Command REF H H L L L H X Idle Self Refresh Entry SELF H L L L L H X Self Refresh Self Refresh Exit - L H L H H H X - L H H X X X X - H L X X X X X L H X X X X X Idle Power Down Power Down Entry Power Down Exit - H = High level, L = Low level, X = High or Low level (Don't care) Jan. 2012 www.eorex.com 12/22 EM42CM1684RTA 3. Operative Command Table Current State Idle Row Active /CS /R /C /W Addr. Command Action H X X X X DESL NOP L H H H X NOP NOP L H H L X TERM NOP ILLEGAL (Note 1) L H L X BA/CA/A10 READ/WRIT/BW L L H H BA/RA ACT L L H L BA, A10 PRE/PREA L L L H REFA Auto refresh(Note 4) L L L L MRS Mode register H L X H X H X H X Op-Code, Mode-Add X X DESL NOP L H H L BA/CA/A10 READ/READA NOP NOP Begin read,Latch CA, Determine auto-precharge L H L L BA/CA/A10 WRIT/WRITA L L H H BA/RA ACT L L H L BA/A10 PRE/PREA L L L H X REFA ILLEGAL L L L L H L L X H H X H H L H L Bank active,Latch RA NOP(Note 3) Begin write,Latch CA, Determine auto-precharge ILLEGAL (Note 1) Precharge/Precharge all MRS ILLEGAL X H L Op-Code, Mode-Add X X X DESL NOP TERM L H BA/CA/A10 READ/READA NOP(Continue burst to end) NOP(Continue burst to end) Terminal burst Terminate burst,Latch CA, Begin new read, Determine Auto-precharge L H H BA/RA ACT L L H L BA, A10 PRE/PREA L L L H REFA ILLEGAL L L L L MRS ILLEGAL H L L X H H X H H X H L X Op-Code, Mode-Add X X X DESL NOP TERM L H L H BA/CA/A10 READ/READA NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL Terminate burst with DM=”H”,Latch CA,Begin read,Determine auto-precharge (Note 2) L H L L BA/CA/A10 WRIT/WRITA Terminate burst,Latch CA,Begin new write, Determine auto-precharge (Note 2) L L H H BA/RA ACT ILLEGAL (Note 1) L L H L BA, A10 PRE/PREA L L L L L L H L X Op-Code, REFA MRS Read Write Jan. 2012 ILLEGAL (Note 1) Terminate burst, PrecharE Terminate burst with DM=”H”, Precharge ILLEGAL ILLEGAL www.eorex.com 13/22 EM42CM1684RTA 3. Operative Command Table (Continued) Current State Read with AP Write with AP Pre-charging Row Activating /CS /R /C /W Addr. Command Action H X X X X DESL NOP(Continue burst to end) L H H H X NOP NOP(Continue burst to end) L H H L BA/CA/A10 TERM H L X BA/RA READ/WRITE ILLEGAL ILLEGAL (Note 1) L L L H H BA/A10 ACT ILLEGAL (Note 1) L L H L X PRE/PREA ILLEGAL (Note 1) L L L H REFA ILLEGAL L L L L MRS ILLEGAL H L L X H H X H H X H L X Op-Code, Mode-Add X X X DESL NOP TERM L H L X BA/CA/A10 READ/WRITE L L H H BA/RA ACT ILLEGAL (Note 1) L L H L BA/A10 PRE/PREA ILLEGAL (Note 1) L L L H REFA ILLEGAL L L L L MRS ILLEGAL H L L X H H X H H X H L X Op-Code, Mode-Add X X X DESL NOP TERM L H L X BA/CA/A10 READ/WRITE L L H H BA/RA ACT L L L L H L L H PRE/PREA REFA L L L L H L L X H H X H H X H L BA/A10 X Op-Code, Mode-Add X X X DESL NOP TERM L H L X BA/CA/A10 READ/WRITE L L H H BA/RA ACT ILLEGAL (Note 1) L L H L BA/A10 PRE/PREA ILLEGAL (Note 1) L L L H REFA ILLEGAL L L L L X Op-Code, Mode-Add MRS ILLEGAL MRS NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL ILLEGAL (Note 1) NOP(idle after tRP) NOP(idle after tRP) NOP ILLEGAL (Note 1) ILLEGAL (Note 1) NOP(idle after tRP) (Note 3) ILLEGAL ILLEGAL NOP(Row active after tRCD) NOP(Row active after tRCD) NOP ILLEGAL (Note 1) H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Jan. 2012 www.eorex.com 14/22 EM42CM1684RTA 3. Operative Command Table (Continued) Current State Write Recovering Refreshing /CS /R /C /W Addr. Command Action H X X X X DESL NOP L H H H X NOP NOP L H H L X TERM H L H BA/CA/A10 READ NOP ILLEGAL(Note 1) L L H L L BA/CA/A10 WRIT/WRITA L L H H BA/RA L L H L BA/A10 PRE/PREA L L L H REFA ILLEGAL L L L L MRS ILLEGAL H L L L L L L X H H H L L L X H H L H H L X H L X H L H L L L L X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add ACT DESL NOP TERM READ/WRIT ACT PRE/PREA REFA MRS New write, Determine AP ILLEGAL (Note 1) ILLEGAL (Note 1) NOP(idle after tRP) NOP(idle after tRP) NOP ILLEGAL ILLEGAL NOP(idle after tRP) ILLEGAL ILLEGAL H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Note 1: ILLEGAL to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. Note 2: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Note 3: NOP to bank precharging or in idle state.May precharge bank indicated by BA. Note 4: ILLEGAL of any bank is not idle. Jan. 2012 www.eorex.com 15/22 EM42CM1684RTA 4. Command Truth Table for CKE Current State Self Refresh Both bank precharge power down All Banks Idle Any State Other than Listed above CKE n-1 n /CS /R /C /W Addr. Action INVALID Exist Self-Refresh Exist Self-Refresh ILLEGAL ILLEGAL ILLEGAL NOP(Maintain self refresh) INVALID Exist Power down Exist Power down ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Power down) Refer to function true table (Note 3) Enter power down mode (Note 3) Enter power down mode ILLEGAL ILLEGAL Row active/Bank active (Note 3) Enter self-refresh Mode register access Special mode register access H L L L L L L H L L L L L L H H X H H H H H L X H H H H H L H L X H L L L L X X H L L L L X X H X X H H H L X X X H H H L X X X X X H H L X X X X H H L X X X X X X H L X X X X X H L X X X X X X X X X X X X X X X X X X X X X H H H H H H H L L L L L L L L L L L L L L H H H L L L L H H L H L L L H L X H H L L X X X RA X Op-Code Op-Code L X X X X X X Refer to current state H H X X X X X Refer to command truth table H = High level, L = Low level, X = High or Low level (Don't care) Notes 1: After CKE’s low to high transition to exist self refresh mode. And a time of tRC (min) has to be elapse after CKE’s low to high transition to issue a new command. Notes 2: CKE low to high transition is asynchronous as if restarts internal clock. Notes 3: Power down and self refresh can be entered only from the idle state of all banks. Jan. 2012 www.eorex.com 16/22 EM42CM1684RTA The Sequence of Power-Up and Initialization The following sequence is required for Power-Up and Initialization. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & VREF. 2. Start clock and maintain stable condition for a minimum of 200us. 3. The minimum of 200us after stable power and clock (CLK, CLK), apply NOP & take CKE high. 4. Precharge all banks. 5. Issue EMRS to enable DLL.(To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to all of the rest address pins, A1~A11 and BA1) 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL. (To issue DLL reset command, provide “High” to A8 and “Low” to BA0) 7. Issue precharge commands for all banks of the device. 8. Issue 2 or more auto-refresh commands. 9. Issue a mode register set command to initialize device operation. Note1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL. Jan. 2012 www.eorex.com 17/22 EM42CM1684RTA Mode Register Definition Mode Register Set The mode register stores the data for controlling the various operating modes of DDR SDRAM which contains addressing mode, burst length, /CAS latency, test mode, DLL reset and various vendor’s specific opinions. The defaults value of the register is not defined, so the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE and BA0 ( The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register. ) The state of the address pins A0-A12 in the same cycle as /CS, /RAS, /CAS, /WE and BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operating as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0-A2, addressing mode uses A3, /CAS latency (read latency from column address) uses A4-A6. A7 is used for test mode. A8 is used for DDR reset. A7 must be set to low for normal MRS operation. Jan. 2012 www.eorex.com 18/22 EM42CM1684RTA Address input for Mode Register Set BA1 BA0 0 MRS A12 A11 A10 A9 RFU* A8 A7 DLL TM A6 A5 A4 CAS Latency A3 A2 BT A1 A0 Bust Length *RFU: Reserved for Future Use An ~ A0 BA0 DLL Rest A8 Mode A7 Burst Type A3 MRS cycle 0 No 0 Normal 0 Sequential 0 EMRS 1 Yes 1 Test 1 Interleave 1 Burst Latency A2 A1 A0 Reserve 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 Reserve 1 0 0 Reserve 1 0 1 Reserve 1 1 0 Reserve 1 1 1 CAS Latency A6 A5 A4 Reserved 0 0 0 Reserved 0 0 1 Reserved 0 1 0 3 0 1 1 Reserve 1 0 0 Reserve 1 0 1 Reserve 1 1 0 Reserve 1 1 1 Jan. 2012 www.eorex.com 19/22 EM42CM1684RTA Burst Type (A3) Burst Length 2 4 8 A2 A1 A0 Sequential Addressing Interleave Addressing X X 0 01 01 X X 0 10 10 X 0 0 0123 0123 X 0 1 1230 1032 X 1 0 2301 2301 X 1 1 3012 3210 0 0 0 01234567 01234567 0 0 1 12345670 10325476 0 1 0 23456701 23016745 0 1 1 34567012 32107654 1 0 0 45670123 45670123 1 0 1 56701234 54761032 1 1 0 67012345 67452301 1 1 1 70123456 *Page length is a function of I/O organization and column addressing 76543210 DLL Enable / Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disable the DLL for the purpose of debug or evaluation ( upon existing Self Refresh Mode, the DLL is enable automatically. ) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Output Drive Strength The normal drive strength got all outputs is specified to be SSTL-2, Class II. Some vendors might also support a weak drive strength option, intended for lighter load and/or point to point environments. Jan. 2012 www.eorex.com 20/22 EM42CM1684RTA Extended Mode Register Set ( EMRS ) The Extended mode register stores the data enabling or disabling DLL. The value of the extended mode register is not defined, so the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA0 ( The DDR SDRAM should be in all bank precharge with CKE already prior to writing into the extended mode register. ) The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE going low is written in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. High on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. BA1 BA0 0 MRS A12 A11 A10 A9 A8 A7 A6 A5 A4 RFU* A3 A2 A1 A0 0 I/O DLL *RFU: Reserved for Future Use Must be set to “0” An ~ A0 BA0 I/O Strength A1 DLL Enable A0 MRS cycle 0 Full 0 Enable 0 EMRS 1 Half 1 Disable 1 Jan. 2012 www.eorex.com 21/22 EM42CM1684RTA Package Description 66-Pin Plastic TSOP-II (400mil) Dimension(mm) Dimension(inch) Symbol A Symbol MIN NOM MAX θ 0 - 8 MIN NOM MAX MIN NOM MAX - - 1.2 - - 0.047 θ1 0 - - 10 15 20 10 15 20 A1 0.05 0.10 0.15 0.002 0.004 0.006 θ2 A2 0.95 1.00 1.05 0.037 0.039 0.041 θ3 b 0.22 - 0.38 0.009 - 0.015 b1 0.22 0.30 0.33 0.009 0.012 0.013 c 0.12 - 0.21 0.005 - 0.008 c1 0.10 0.127 0.16 0.004 0.005 0.006 D 22.22BSC 0.875BSC 0.71REF 0.028REF E 11.76BSC 0.463BSC E1 10.16BSC 0.400BSC ZD L 0.40 L1 0.50 0.60 0.016 0.020 0.80REF 0.031REF 0.65BSC 0.026BSC 0.024 R1 0.12 - - 0.005 - - R2 0.12 - 0.25 0.005 - 0.010 Jan. 2012 www.eorex.com 22/22