FMP0417CAx-W70E CMOS LPRAM FMP0417CAx-W70E Customer • Do not leave this document unattended. • All information contained within this document is covered by the non-discloser agreement. • Do not reproduce this document. • This document is Fidelix Co., Ltd. property and it can be required to be returned at any time. Fidelix Co., Ltd. 1 Revision 0.0 Feb. 2008 FMP0417CAx-W70E CMOS LPRAM Document Title 256K x 16 bit Super Low Power and Low Voltage Full CMOS RAM Revision History Revision No. 0.0 History Generated new datasheet 2 Draft date Remark Feb.21st, 2008 Preliminary Revision 0.0 Feb. 2008 FMP0417CAx-W70E CMOS LPRAM 256K x 16 bit Super Low Power and Low Voltage Full CMOS RAM FEATURES • Process Technology : Full CMOS • Low Power & Page Modes FMP0417CA1 : support the PASR/DPD function FMP0417CA2 : support the Direct DPD function FMP0417CA4 : support the PASR/DPD/PAGE function FMP0417CA5 : support the Direct DPD/PAGE function • Organization : 256K x 16 • Power Supply Voltage : 2.7~3.3V • Three state output and TTL Compatible • Separated I/O power(VCCQ) & Core power(VCC) • Automatic power-down when deselected • Page read/write operation by 16 words (FMP0417CA4, FMP0417CA5) • DPD mode by using MRS only (FMP0417CA1, FMP0417CA4) • Direct DPD mode when /ZZ goes low (FMP0417CA2, FMP0417CA5) PRODUCT FAMILY Product Family Operating Temperature Power Dissipation Operating Voltage (V) Speed FMP0417CAx-W70E ICC2 f = 1MHz Min. Typ. Max. Extended (-25~85’C) ICC1 2.7 3.0 3.3 70ns f = fmax ISB1 (CMOS Standby Current) Typ. Max. Typ. Max. Typ. Max. 1.5mA 3mA 15mA 25mA 30uA 70uA 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C. 2. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM Name Function Name Function /ZZ Low Power Modes VCC Core Power /CS Chip Select Input VCCQ I/O Power /OE Output Enable Input VSS Ground /WE Write Enable Input /UB Upper Byte(I/O9~16) A0~A17 Address Inputs /LB Lower Byte(I/O 1~8) I/O1~I/O16 Data Inputs/Outputs DNU Do Not Use Clk gen. Precharge circuit. VCC VSS Row Addresses I/O1~I/O8 Row select Data cont Memory array I/O Circuit Column select Data cont I/O9~I/O16 Data cont Column Addresses /CS /ZZ /OE /WE Control Logic /UB /LB 3 Revision 0.0 Feb. 2008 FMP0417CAx-W70E CMOS LPRAM PRODUCT LIST Extended Temperature Products(-25~85’C) Part Name Function FMP0417CAx-W70E Wafer, 70ns, VCC=3.0V, VCCQ=3.0V 1. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER FUNCTIONAL DESCRIPTION /CS /ZZ /OE /WE /LB /UB I/O1-8 I/O9-16 Mode Power H H X1) X1) X1) X1) High-Z High-Z Deselected Standby X1) L X1) X1) X1) X1) High-Z High-Z Deselected Direct DPD2) H L X1) X1) X1) X1) High-Z High-Z Deselected Low Power Modes3) H X1) X1) H H High-Z High-Z Deselected Standby High-Z High-Z Output Disabled Active High-Z High-Z Output Disabled Active X1) H H H L X1) H H H X1) L L H Dout High-Z Lower Byte Read Active L H H L High-Z Dout Upper Byte Read Active L L Dout Dout Word Read Active L H Din High-Z Lower Byte Write Active H L High-Z Din Upper Byte Write Active L L Din Din Word Write Active L L H X1) L 1. X means don’t care.(Must be low or high state) 2. In case of FMP0417CA2 & FMP0417CA5 product 3. In case of FMP0417CA1 & FMP0417CA4 product ABSOLUTE MAXIMUM RATINGS1) Item Symbol Ratings Unit VIN, VOUT -0.2 to Vcc+0.3V V Voltage on Vcc supply relative to Vss Vcc -0.2 to 3.6 V Power Dissipation PD 1.0 W TSTG -65 to 150 ’C TA -25 to 85 ’C Voltage on any pin relative to Vss Storage temperature Operating Temperature 1 . S t re s s e s gr e a t e r t h a n t h o s e l i st e d u n d e r “A b s olute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for Industrial periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS1) FMP0417CAx Item Supply voltage Symbol Unit Min Max VCC 2.7 3.3 V VCCQ 2.7 3.3 V Ground VSS 0 0 V Input high voltage VIH 0.8VCCQ VCC+0.22) V VIL -0.23) 0.2VCCQ V I/O operating voltage Input low voltage Note : 1.TA=-25 to 85’C, otherwise specified. 2. Overshoot : Vcc+1.0V in case of pulse width≤20ns. 3. Undershoot : -1.0V in case of pulse width≤20ns. 4. Overshoot and undershoot are sampled, not 100% tested. 4 Revision 0.0 Feb. 2008 FMP0417CAx-W70E CAPACITANCE1) CMOS LPRAM (f=1MHz , TA=25’C) Symbol Test Condition Min Max Unit Input capacitance Item CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 8 pF 1. Capacitance is sampled, not 100% tested. DC AND OPERATING CHARACTERISTICS Item Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIN=VSS to VCC -1 - 1 uA Output leakage current ILO /CS=VIH, /ZZ=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC -1 - 1 uA ICC1 Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, /ZZ=VIH, VIN≤0.2V or VIN≥VCC-0.2V - 1.5 3 mA ICC2 Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, /ZZ=VIH, VIN=VIL or VIH - 15 25 mA Output low voltage VOL IOL=0.5mA 0.2VCCQ V Output high voltage VOH IOH=-0.5mA Standby Current(TTL) ISB /CS=VIH, /ZZ=VIH, Other inputs=VIH or VIL - - 0.3 mA Standby Current(CMOS) ISB1 /CS≥VCC-0.2V, /ZZ≥VCC-0.2V, Other inputs=0~VCC - - 70 uA uA Average operating current 0.8VCCQ V ISB0 /ZZ≤0.2V, Other inputs=0~VCC, No refresh(DPD) - - 10 ISB0a /ZZ≤0.2V, Other inputs=0~VCC, ¼ refresh area selection - - 55 uA ISB0b /ZZ≤0.2V, Other inputs=0~VCC, ½ refresh area selection - - 60 uA ISB0c /ZZ≤0.2V, Other inputs=0~VCC, All refresh area selection - - 70 uA Low Power Modes AC Input/Output Reference Waveform VCCQ Input1 VCCQ/2 2 VCCQ/23 Output Test Points VSS NOTE: 1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Input timing begins at VCCQ/2. 3. Output timing ends at VCCQ/2. AC Output Load Circuit Test Point 50Ω DUT VCCQ/2 30pF 5 Revision 0.0 Feb. 2008 FMP0417CAx-W70E CMOS LPRAM AC CHARACTERISTICS(VCC=2.7V~3.3V, Extended product : TA=-25 to 85’C) Parameter List 70ns Symbol Units Min Max tRC 70 20K ns tAA - 70 ns Chip Select to Output tCO - 70 ns Output Enable to Valid Output tOE - 25 ns /UB, /LB Access Time tBA - 70 ns Read Cycle Time Address Access Time tLZ 10 - ns /UB, /LB Enable to Low-Z Output Chip Select to Low-Z Output tBLZ 10 - ns Output Enable to Low-Z Output tOLZ 5 - ns Chip Disable to High- Z Output tHZ 0 5 ns /UB, /LB Disable to High- Z Output tBHZ 0 5 ns Output Disable to High- Z Output tOHZ 0 5 ns Output Hold from Address Change tOH 5 - ns Write Cycle Time tWC 70 20K ns Read Write Chip Select to End of Write tCW 60 - ns Address Set-up Time tAS 0 - ns Address Valid to End of Write tAW 60 - ns /UB, /LB Valid to End of Write tBW 60 - ns Write Pulse Width tWP 50 - ns Write Recovery Time tWR 0 - ns Write to Output High-Z tWHZ 0 5 ns Data to Write Time Overlap tDW 20 - ns Data Hold from Write Time tDH 0 - ns End Write to Output Low-Z tOW 5 - ns Page Mode Cycle Time Page tPC 25 - ns Page Mode Address Access Time tPAA - 25 ns Maximum Cycle Time tMRC - 20k ns tCP 10 - ns /CS High Pulse Width1) 1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High. 6 Revision 0.0 Feb. 2008 FMP0417CAx-W70E CMOS LPRAM Power Up Sequence 1. Apply Power 2. Maintain stable power for a minimum of 200us with /CS=VIH Standby Mode State Machines Power On /CS=VIH Wait 200us /CS=VIH, /ZZ=VIH Initial State /CS=VIL, /ZZ=VIH /UB or/and /LB=VIL /CS=VIH, /ZZ=VIL Active Mode /CS=VIL /ZZ=VIH /CS=VIH /ZZ=VIL /CS=VIH (or/and /UB=/LB=VIH) /ZZ=VIH /CS=VIH, /ZZ=VIL Standby Mode /CS=VIL /ZZ=VIH Low Power Modes 1 (4M/2M/1M bits) Low Power Modes 2 (Data Invalid) /CS=VIH, /ZZ=VIL Standby Mode Characteristics Mode Memory Cell Data Standby Current(uA) Wait Time(us) Standby Valid 70 (ISB1) 0 Invalid 10 (ISB0) 200 ¼ valid 55 (ISB0a) 0 ½ valid 60 (ISB0b) 0 valid 70 (ISB0c) 0 Low Power Modes 7 Revision 0.0 Feb. 2008 FMP0417CAx-W70E READ CYCLE (1) CMOS LPRAM (Address controlled,/CS=/OE=VIL, /ZZ=/WE=VIH, /UB or/and /LB=VIL) tRC Address tAA tOH Data Out READ CYCLE (2) Previous Data Valid Data Valid (/ZZ=/WE=VIH) tRC Address tOH tAA tCO /CS tHZ tBA /UB, /LB tBHZ tOE /OE tOLZ Data Out tOHZ tBLZ tLZ High-Z Data Valid 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. PAGE READ CYCLE (/ZZ=/WE=VIH, 16 words access) tMRC tRC tPC tPC tPC tPC tPC tPC tPC A0~A3 tAA A4~A17 tOH tCO /CS tHZ tBA /UB, /LB tBHZ tOE /OE tOLZ tBLZ Data Out High-Z tPAA tPAA Data Valid Data Valid tPAA tPAA tPAA tPAA tPAA tOHZ tLZ Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 4. In case page address skew is over 3ns, tPAA will be out of spec. 8 Revision 0.0 Feb. 2008 FMP0417CAx-W70E WRITE CYCLE (1) CMOS LPRAM (/WE controlled, /ZZ=VIH) tWC Address tCW(2) tWR(4) /CS tAW tBW /UB, /LB tWP(1) /WE tAS(3) tDW Data in tWHZ Data Out WRITE CYCLE (2) tDH Data Valid High-Z High-Z tOW Data Undefined (/CS controlled, /ZZ=VIH) tWC Address tAS(3) tWR(4) tCW(2) /CS tAW tBW /UB, /LB tWP(1) /WE tDW Data in Data Out WRITE CYCLE (3) tDH Data Valid High-Z High-Z (/UB, /LB controlled, /ZZ=VIH) tWC Address tWR(4) tCW(2) /CS tAW tBW /UB, /LB tAS(3) tWP(1) /WE tDW Data in Data Out tDH Data Valid High-Z High-Z 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 9 Revision 0.0 Feb. 2008 FMP0417CAx-W70E PAGE WRITE CYCLE CMOS LPRAM (Address controlled, /ZZ=VIH) tMRC tPC tWC tPC tPC tPC tPC tPC tPC A0~A3 A4~A17 /CS /UB, /LB tAS(3) /WE tDW Data in High-Z tDH Data Valid tDW tDH Data Valid tDW Data Valid tWHZ Data Out tDH tDW tDH Data Valid tDW tDH Data Valid tDW tDH Data Valid tDW tDH Data Valid tDW tDH Data Valid High-Z tOW Data Undefined 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 6. In case page address is over 3ns, write to the invalid address can occur. 10 Revision 0.0 Feb. 2008 FMP0417CAx-W70E CMOS LPRAM LOW POWER MODES 1. Mode Register Set A17 ~ A5 0 A4 A3 A2 ZZ Array On/Off on /ZZ Half Selection Enable/Disable /ZZ Enable/Disable A1 A0 Array Refresh Area Array On/Off on /ZZ A4 Type A3 Type 0 Deep Power Down Enable 0 Partial Array Refresh Mode (Default) 1 DPD Disable (Default) 1 Reduced Memory Size Mode Note: If the register is written to enable the Deep Power Down, the part will go into Deep Power Down during the following time that /ZZ is driven low and there is no MRS update. When /ZZ is driven high, all of the register settings will return to default state for the part (i.e. full array refresh, Deep Power Down Disabled). Half Selection (Top / Bottom) Note: The RMS(Reduced Memory Size) mode is enabled after /ZZ goes high and remains enabled after /ZZ goes high. To change to a different mode, the mode register will have to be rewritten. Array Refresh Area A2 Type A1 A0 Type 0 Bottom (Default) 0 0 Full Array (Default) 1 Top 0 1 RFU 1 0 ½ Array 1 1 ¼ Array 2. MRS Update tWC Address tAS(3) tCW(2) tWR(4) /CS tAW tBW /UB, /LB tWP(1) /WE /ZZ tZZWE Register Write Start Register Write Complete Register Update Complete The register update take place on the rising edge of /ZZ. Once the register is updated, the next time /ZZ goes low, without any updates to the register starting within the tZZWE max time of 1us, the part will refresh the array selected. The data bus is a don’t care When /ZZ is low during the register updates. 11 Revision 0.0 Feb. 2008 FMP0417CAx-W70E CMOS LPRAM 3. Deep Power Down Mode Entry/Exit tWC A4 tAS(3) tWR(4) tCW(2) /CS tAW /UB, /LB tBW tWP(1) /WE tZZWE tR Next Cycle tZZmin /ZZ Register Write(DPD) Deep Power down exit Deep Power down start Parameter Description Min Max Units tZZWE ZZ low to Write Enable Low 0 1 us tR(Deep Power Down Mode only) Operation Recovery Time 200 - us tZZmin Low Power Mode Time 10 - us 4. Address Information Partial Array Refresh Mode (A3=0, A4=1) A2 A1,A0 Refresh Section Address Size Density 0 11 1/4 00000h-0FFFFh 64Kbx16 1Mb 0 10 1/2 00000h-1FFFFh 128Kbx16 2Mb X 00 Full 00000h-3FFFFh 256Kbx16 4Mb 1 11 1/4 30000h-3FFFFh 64Kbx16 1Mb 1 10 1/2 20000h-3FFFFh 128Kbx16 2Mb Reduced Memory Size Mode (A3=1, A4=1) A2 A1,A0 Refresh Section Address Size Density 0 11 1/4 00000h-0FFFFh 64Kbx16 1Mb 0 10 1/2 00000h-1FFFFh 128Kbx16 2Mb 1 11 1/4 30000h-3FFFFh 64Kbx16 1Mb 1 10 1/2 20000h-3FFFFh 128Kbx16 2Mb 12 Revision 0.0 Feb. 2008