CY7C1484BV33 72-Mbit (2 M × 36) Pipelined DCD Sync SRAM 72-Mbit (2 M × 36) Pipelined DCD Sync SRAM Features Functional Description ■ Supports bus operation up to 250 MHz ■ Available speed grade is 250 MHz ■ Registered inputs and outputs for pipelined operation ■ Optimal for performance (double cycle deselect) ■ Depth expansion without wait state ■ 3.3 V core power supply (VDD) ■ 2.5 V and 3.3 V I/O operation ■ Fast clock to output times ❐ 3.0 ns (for 250 MHz device) ■ Provide high performance 3-1-1-1 access rate ■ User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self timed writes ■ Asynchronous output enable ■ CY7C1484BV33 available in Pb-free 165-ball FBGA package ■ IEEE 1149.1 JTAG compatible boundary scan ■ “ZZ” sleep mode option The CY7C1484BV33 SRAM integrates 2 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining Chip Enable (CE1), depth expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self timed write cycle. This part supports byte write operations (see Pin Definitions on page 5 and Truth Table on page 8 for more information). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register, which delays turning off the output buffers an additional cycle when a deselect is executed. This feature allows depth expansion without penalizing system performance. The CY7C1484BV33 operates from a +3.3 V core power supply while all outputs operate with a +3.3 V or a +2.5 V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. Selection Guide Description 250 MHz Unit Maximum Access Time 3.0 ns Maximum Operating Current 500 mA Maximum CMOS Standby Current 120 mA Cypress Semiconductor Corporation Document Number: 001-75351 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 9, 2013 CY7C1484BV33 Logic Block Diagram – CY7C1484BV33 ADDRESS REGISTER A 0,A1,A 2 A[1:0] MODE ADV CLK BURST Q1 COUNTER AND LOGIC CLR Q0 ADSC ADSP BW D DQ D, DQP D BYTE WRITE REGISTER DQ D, DQP D BYTE WRITE DRIVER BW C DQ c,DQP C BYTE WRITE REGISTER DQ c,DQP C BYTE WRITE DRIVER DQ B ,DQP B BYTE WRITE REGISTER DQ B ,DQP B BYTE WRITE DRIVER BW B BW A BWE GW CE 1 CE 2 CE 3 OE ZZ SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS DQs DQP A DQP B DQP C DQP D E DQ A, DQP A BYTE WRITE DRIVER DQ A, DQP A BYTE WRITE REGISTER ENABLE REGISTER MEMORY ARRAY PIPELINED ENABLE INPUT REGISTERS SLEEP CONTROL Document Number: 001-75351 Rev. *B Page 2 of 30 CY7C1484BV33 Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 5 Functional Overview ........................................................ 6 Single Read Accesses ................................................ 6 Single Write Accesses Initiated by ADSP ................... 6 Single Write Accesses Initiated by ADSC ................... 6 Burst Sequences ......................................................... 7 Sleep Mode ................................................................. 7 Interleaved Burst Address Table (MODE = Floating or VDD) .................................................. 7 Linear Burst Address Table (MODE = GND) ............... 7 ZZ Mode Electrical Characteristics .............................. 7 Truth Table ........................................................................ 8 Truth Table for Read/Write .............................................. 9 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 10 Disabling the JTAG Feature ...................................... 10 Test Access Port (TAP) ............................................. 10 PERFORMING A TAP RESET .................................. 10 TAP REGISTERS ...................................................... 10 TAP Instruction Set ................................................... 10 TAP Controller State Diagram ....................................... 12 TAP Controller Block Diagram ...................................... 13 TAP Timing ...................................................................... 13 TAP AC Switching Characteristics ............................... 14 3.3 V TAP AC Test Conditions ....................................... 15 3.3 V TAP AC Output Load Equivalent ......................... 15 2.5 V TAP AC Test Conditions ....................................... 15 2.5 V TAP AC Output Load Equivalent ......................... 15 Document Number: 001-75351 Rev. *B TAP DC Electrical Characteristics and Operating Conditions ..................................................... 15 Identification Register Definitions ................................ 16 Scan Register Sizes ....................................................... 16 Identification Codes ....................................................... 16 Boundary Scan Exit Order ............................................. 17 Maximum Ratings ........................................................... 18 Operating Range ............................................................. 18 Electrical Characteristics ............................................... 18 Capacitance .................................................................... 19 Thermal Resistance ........................................................ 19 AC Test Loads and Waveforms ..................................... 20 Switching Characteristics .............................................. 21 Switching Waveforms .................................................... 22 Ordering Information ...................................................... 26 Ordering Code Definitions ......................................... 26 Package Diagrams .......................................................... 27 Acronyms ........................................................................ 28 Document Conventions ................................................. 28 Units of Measure ....................................................... 28 Document History Page ................................................. 29 Sales, Solutions, and Legal Information ...................... 30 Worldwide Sales and Design Support ....................... 30 Products .................................................................... 30 PSoC Solutions ......................................................... 30 Page 3 of 30 CY7C1484BV33 Pin Configurations Figure 1. 165-ball FBGA (15 × 17 × 1.4 mm) pinout CY7C1484BV33 (2 M × 36) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC/288M A CE1 BWC BWB CE3 BWE ADSC ADV A NC NC/144M A CE2 BWD BWA CLK NC/576M VDDQ VDDQ VSS VDD VSS VSS VSS VSS OE VSS VDD A NC DQC GW VSS VSS ADSP DQPC DQC VDDQ VDDQ NC/1G DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC NC DQD DQC NC DQD VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ DQB NC DQA DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS A VSS NC VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC A A A TDI A1 TDO A A A A R MODE A A A TMS A0 TCK A A A A Document Number: 001-75351 Rev. *B Page 4 of 30 CY7C1484BV33 Pin Definitions Pin Name A0, A1, A I/O Description InputAddress Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the 2-bit counter. InputByte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. BWA, BWB BWC, BWD Synchronous Sampled on the rising edge of CLK. GW InputGlobal Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write Synchronous is conducted (ALL bytes are written, regardless of the values on BWX and BWE). BWE InputByte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted Synchronous LOW to conduct a byte write. CLK InputClock Clock Input. Capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW during a burst operation. CE1 InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. CE3 InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded. OE InputOutput Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW, Asynchronous the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputAdvance Input Signal, Sampled on the Rising Edge of CLK, Active LOW. When asserted, it Synchronous automatically increments the address in a burst cycle. ADSP InputAddress Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputAddress Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ InputZZ “Sleep” Input, Active HIGH. When asserted HIGH, places the device in a non time-critical “sleep” Asynchronous condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull down. DQs, DQPs I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. VDD Power Supply Power Supply Inputs to the Core of the Device. Ground Ground for the Core of the Device. VDDQ I/O Power Supply Power Supply for the I/O Circuitry. MODE InputStatic VSS TDO Selects Burst Order. When tied to GND, selects linear burst sequence. When tied to VDD or left floating, selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode Pin has an internal pull up. JTAG Serial Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not used, this pin must be disconnected. Output Synchronous Document Number: 001-75351 Rev. *B Page 5 of 30 CY7C1484BV33 Pin Definitions (continued) Pin Name I/O Description TDI JTAG Serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used, this pin can be disconnected or connected to VDD. Input Synchronous TMS JTAG Serial Serial Data-in to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used, Input this pin can be disconnected or connected to VDD. Synchronous TCK JTAG Clock Clock Input to the JTAG Circuitry. If the JTAG feature is not used, this pin must be connected to VSS. NC – No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. Functional Overview ADSP or ADSC signals, its output tri-states immediately after the next clock rise. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Single Write Accesses Initiated by ADSP The CY7C1484BV33 supports secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable and is determined by sampling the MODE input. Accesses are initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self timed write circuitry. Synchronous Chip Selects CE1, CE2, CE3, and an asynchronous Output Enable (OE) provide easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the address register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the output registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tCO if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state; its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the OE signal controls the outputs. Consecutive single read cycles are supported. The CY7C1484BV33 is a double cycle deselect part. After the SRAM is deselected at clock rise by the chip select and either Document Number: 001-75351 Rev. *B This access is initiated when both the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH, then the BWE and BWX signals control the write operation. The CY7C1484BV33 provides byte write capability that is described in the Truth Table on page 8. Asserting the Byte Write Enable input (BWE) with the selected byte write input selectively writes to only the desired bytes. Bytes not selected during a byte write operation remain unaltered. A synchronous self timed write mechanism is provided to simplify the write operations. Because the CY7C1484BV33 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so tri-states the output drivers. As a safety precaution, DQ are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWX) are asserted active to conduct a write to the desired bytes. ADSC triggered write accesses require a single clock cycle to complete. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQX is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation remain unaltered. A synchronous self timed write mechanism is provided to simplify the write operations. Page 6 of 30 CY7C1484BV33 Because the CY7C1484BV33 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQX inputs. Doing so tri-states the output drivers. As a safety precaution, DQX are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) The CY7C1484BV33 provides a 2-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Both read and write burst operations are supported. Asserting ADV LOW at clock rise automatically increments the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) Sleep Mode The ZZ input pin is asynchronous. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the “sleep” mode. CEs, ADSP, and First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 120 mA tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC – ns tZZI ZZ Active to sleep current This parameter is sampled – 2tCYC ns tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 – ns Document Number: 001-75351 Rev. *B Page 7 of 30 CY7C1484BV33 Truth Table The truth table for CY7C1484BV33 follows. [1, 2, 3, 4, 5] Operation Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Power Down None H X X L X L X X X L–H Tri-State Deselect Cycle, Power Down None L L X L L X X X X L–H Tri-State Deselect Cycle, Power Down None L X H L L X X X X L–H Tri-State Deselect Cycle, Power Down None L L X L H L X X X L–H Tri-State Deselect Cycle, Power Down None L X H L H L X X X L–H Tri-State Sleep Mode, Power Down None X X X H X X X X X X Tri-State Read Cycle, Begin Burst External L H L L L X X X L L–H Q Read Cycle, Begin Burst External L H L L L X X X H L–H Tri-State Write Cycle, Begin Burst External L H L L H L X L X L–H D Read Cycle, Begin Burst External L H L L H L X H L L–H Q Read Cycle, Begin Burst External L H L L H L X H H L–H Tri-State Read Cycle, Continue Burst Next X X X L H H L H L L–H Read Cycle, Continue Burst Next X X X L H H L H H L–H Tri-State Read Cycle, Continue Burst Next H X X L X H L H L L–H Read Cycle, Continue Burst Next H X X L X H L H H L–H Tri-State Write Cycle, Continue Burst Next X X X L H H L L X L–H D Write Cycle, Continue Burst Next H X X L X H L L X L–H D Read Cycle, Suspend Burst Current X X X L H H H H L L–H Q Read Cycle, Suspend Burst Current X X X L H H H H H L–H Tri-State Read Cycle, Suspend Burst Current H X X L X H H H L L–H Read Cycle, Suspend Burst Current H X X L X H H H H L–H Tri-State Write Cycle, Suspend Burst Current X X X L H H H L X L–H D Write Cycle, Suspend Burst Current H X X L X H H L X L–H D Q Q Q Notes 1. X = Don’t Care, H = Logic HIGH, L = Logic LOW. 2. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes can occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a don’t care for the remainder of the write cycle. 5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 001-75351 Rev. *B Page 8 of 30 CY7C1484BV33 Truth Table for Read/Write The read/write truth table for CY7C1484BV33 and follows. [6, 7] Function (CY7C1484BV33) GW BWE BWD BWC BWB BWA Read H H X X X X Read H L H H H H Write Byte A – (DQA and DQPA) H L H H H L Write Byte B – (DQB and DQPB) H L H H L H Write Bytes B, A H L H H L L Write Byte C – (DQC and DQPC) H L H L H H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – (DQD and DQPD) H L L H H H Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, C H L L L H H Write Bytes D, C, A H L L L H L Write Bytes D, C, B H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Notes 6. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 7. Table includes only a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is based on which byte write is active. Document Number: 001-75351 Rev. *B Page 9 of 30 CY7C1484BV33 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1484BV33 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3 V or 2.5 V I/O logic levels. The CY7C1484BV33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, tie TCK LOW (VSS) to prevent device clocking. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO must be left unconnected. During power up, the device comes up in a reset state, which does not interfere with the operation of the device. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input gives commands to the TAP controller and is sampled on the rising edge of TCK. it is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram on page 12. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. Test Data-Out (TDO) The TDO output ball serially clocks data-out from the registers. Whether the output is active depends on the current state of the TAP state machine (see Identification Codes on page 16). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset Perform a RESET by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. During power up, the TAP is reset internally to ensure that TDO comes up in a High Z state. Document Number: 001-75351 Rev. *B TAP Registers Registers are connected between the TDI and TDO balls to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions are serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls, as shown in the TAP Controller Block Diagram on page 13. During power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to enable fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single bit register that is placed between the TDI and TDO balls. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The x36 configuration has a 73-bit long register and the x18 configuration has a 54-bit long register. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller moves to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions are used to capture the contents of the I/O ring. The Boundary Scan Exit Order on page 17 show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 16. TAP Instruction Set Overview Eight different instructions are possible with the 3-bit instruction register. All combinations are listed in Identification Codes on page 16. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail in this section. Page 10 of 30 CY7C1484BV33 The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction that is executed whenever the instruction register is loaded with all zeros. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-zero instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction is loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High Z state. IDCODE The IDCODE instruction loads a vendor specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO balls and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is in a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. Be aware that the TAP controller clock only operates at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that may be captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. After the data is captured, shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. Note that because the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document Number: 001-75351 Rev. *B Page 11 of 30 CY7C1484BV33 TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCA N 1 SELECT IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-IR 0 1 0 PAUSE-DR 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR 1 0 1 EXIT1-DR 0 1 0 UPDATE-IR 1 0 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Document Number: 001-75351 Rev. *B Page 12 of 30 CY7C1484BV33 TAP Controller Block Diagram 0 Bypass Register 2 1 0 TDI Selection Circuitry Selection Circuitry Instruction Register TDO 31 30 29 . . . 2 1 0 Identification Register x . . . . . 2 1 0 Boundary Scan Register TCK TAP CONTROLLER TM S TAP Timing Figure 2. TAP Timing 1 2 Test Clock (TCK ) 3 t TH t TM SS t TM SH t TDIS t TDIH t TL 4 5 6 t CY C Test M ode Select (TM S) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CA RE Document Number: 001-75351 Rev. *B UNDEFINED Page 13 of 30 CY7C1484BV33 TAP AC Switching Characteristics Over the Operating Range Parameter [8, 9] Clock tTCYC tTF tTH tTL Output Times tTDOV tTDOX Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH Description Min Max Unit TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH Time TCK Clock LOW Time 50 – 20 20 – 20 – – ns MHz ns ns TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid – 0 10 – ns ns TMS Setup to TCK Clock Rise TDI Setup to TCK Clock Rise Capture Setup to TCK Rise 5 5 5 – – – ns ns ns TMS hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 – – – ns ns ns Notes 8. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 9. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document Number: 001-75351 Rev. *B Page 14 of 30 CY7C1484BV33 3.3 V TAP AC Test Conditions 2.5 V TAP AC Test Conditions Input pulse levels ...............................................VSS to 3.3 V Input pulse levels ............................................... VSS to 2.5 V Input rise and fall times ...................................................1 ns Input rise and fall time ....................................................1 ns Input timing reference levels ......................................... 1.5 V Input timing reference levels ....................................... 1.25 V Output reference levels ................................................ 1.5 V Output reference levels .............................................. 1.25 V Test load termination supply voltage ............................ 1.5 V Test load termination supply voltage .......................... 1.25 V 3.3 V TAP AC Output Load Equivalent 2.5 V TAP AC Output Load Equivalent 1.25V 1.5V 50Ω 50Ω TDO TDO Z O= 50Ω Z O= 50Ω 20pF 20pF TAP DC Electrical Characteristics and Operating Conditions (0 °C < TA < +70 °C; VDD = 3.135 V to 3.6 V unless otherwise noted) Parameter [11] VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Test Conditions Min Max Unit IOH = –4.0 mA, VDDQ = 3.3 V 2.4 – V IOH = –1.0 mA, VDDQ = 2.5 V 2.0 – V IOH = –100 µA VDDQ = 3.3 V 2.9 – V VDDQ = 2.5 V 2.1 – V IOL = 8.0 mA, VDDQ = 3.3 V – 0.4 V IOL = 1.0 mA, VDDQ = 2.5 V – 0.4 V IOL = 100 µA VDDQ = 3.3 V – 0.2 V VDDQ = 2.5 V – 0.2 V VDDQ = 3.3 V 2.0 VDD + 0.3 V VDDQ = 2.5 V 1.7 VDD + 0.3 V VDDQ = 3.3 V –0.5 0.7 V VDDQ = 2.5 V –0.3 0.7 V –5 5 µA GND < VIN < VDDQ Note 11. All voltages refer to VSS (GND). Document Number: 001-75351 Rev. *B Page 15 of 30 CY7C1484BV33 Identification Register Definitions Bit# 24 is “1” in the ID Register definitions for both 2.5 V and 3.3 V versions of the device. CY7C1484BV33 (2 M × 36) Instruction Field Revision Number (31:29) 000 Description Describes the version number Device Depth (28:24) 01011 Reserved for internal use Architecture/Memory Type(23:18) 000110 Defines memory type and architecture 100100 Defines width and density Bus Width/Density (17:12) Cypress JEDEC ID Code (11:1) 00000110100 ID Register Presence Indicator (0) 1 Enables unique identification of SRAM vendor Indicates the presence of an ID register Scan Register Sizes Register Name Bit Size (× 36) Instruction 3 Bypass 1 ID 32 Boundary Scan Order – 165-ball FBGA 73 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document Number: 001-75351 Rev. *B Page 16 of 30 CY7C1484BV33 Boundary Scan Exit Order (2 M × 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1 C1 21 R3 2 D1 22 P2 41 L10 61 B8 42 K11 62 A7 3 E1 23 R4 43 J11 63 B7 4 D2 24 P6 44 K10 64 B6 5 E2 25 R6 45 J10 65 A6 6 F1 26 N6 46 H11 66 B5 7 G1 27 P11 47 G11 67 A5 8 F2 28 R8 48 F11 68 A4 9 G2 29 P3 49 E11 69 B4 10 J1 30 P4 50 D10 70 B3 11 K1 31 P8 51 D11 71 A3 12 L1 32 P9 52 C11 72 A2 13 J2 33 P10 53 G10 73 B2 14 M1 34 R9 54 F10 15 N1 35 R10 55 E10 16 K2 36 R11 56 A10 17 L2 37 N11 57 B10 18 M2 38 M11 58 A9 19 R1 39 L11 59 B9 20 R2 40 M10 60 A8 Document Number: 001-75351 Rev. *B Page 17 of 30 CY7C1484BV33 Maximum Ratings DC Input Voltage ................................ –0.5 V to VDD + 0.5 V Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied ......................................... –55 C to +125 C Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, Method 3015) .................................. >2001 V Latch Up Current .................................................... >200 mA Operating Range Supply Voltage on VDD Relative to GND .....–0.5 V to +4.6 V Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD Range Ambient Temperature DC Voltage Applied to Outputs in Tri-State ........................................–0.5 V to VDDQ + 0.5 V Commercial 0 °C to +70 °C Industrial –40 °C to +85 °C VDD VDDQ 3.3 V– 5% / 2.5 V – 5% to + 10% VDD Electrical Characteristics Over the Operating Range Parameter [12, 13] Description Test Conditions Min Max Unit VDD Power Supply Voltage 3.135 3.6 V VDDQ I/O Supply Voltage For 3.3 V I/O 3.135 VDD V For 2.5 V I/O 2.375 2.625 V VOH Output HIGH Voltage For 3.3 V I/O, IOH = –4.0 mA 2.4 – V For 2.5 V I/O, IOH = –1.0 mA 2.0 – V For 3.3 V I/O, IOL = 8.0 mA – 0.4 V For 2.5 V I/O, IOL = 1.0 mA – 0.4 V 2.0 VDD + 0.3 V V For 2.5 V I/O 1.7 VDD + 0.3 V V For 3.3 V I/O –0.3 0.8 V For 2.5 V I/O VOL Output LOW Voltage [12] VIH Input HIGH Voltage VIL Input LOW Voltage [12] –0.3 0.7 V IX Input Leakage Current Except ZZ GND VI VDDQ and MODE –5 5 A Input Current of MODE Input = VSS –30 – A Input = VDD – 5 A Input = VSS –5 – A Input = VDD – 30 A Output Leakage Current GND VI VDDQ, Output Disabled –5 5 A VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 4 ns cycle, 250 MHz – 500 mA ISB1 Automatic CE Power Down Current – TTL Inputs VDD = Max, Device Deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC 4 ns cycle, 250 MHz – 245 mA ISB2 Automatic CE Power Down Current – CMOS Inputs VDD = Max, Device Deselected, 4 ns cycle, VIN 0.3V or VIN > VDDQ – 0.3V, 250 MHz f=0 – 120 mA Input Current of ZZ IOZ IDD [14] For 3.3 V I/O Notes 12. Overshoot: VIH(AC) < VDD +1.5 V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2). 13. Power up: assumes a linear ramp from 0 V to VDD(minimum) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 14. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-75351 Rev. *B Page 18 of 30 CY7C1484BV33 Electrical Characteristics (continued) Over the Operating Range Parameter [12, 13] Test Conditions Min Max Unit ISB3 Automatic CE Power Down Current – CMOS Inputs Description VDD = Max, Device Deselected, 4 ns cycle, VIN 0.3 V or VIN > VDDQ – 0.3 V, 250 MHz f = fMAX = 1/tCYC – 245 mA ISB4 Automatic CE Power Down Current – TTL Inputs VDD = Max, Device Deselected, VIN VIH or VIN VIL, f = 0 4 ns cycle, 250 MHz – 135 mA Capacitance Parameter [15] Description CADDRESS Address Input Capacitance CDATA CCTRL Test Conditions TA = 25 C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V 165-ball FBGA Unit Package 6 pF Data Input Capacitance 5 pF Control Input Capacitance 8 pF CCLK Clock Input Capacitance 6 pF CIO Input/Output Capacitance 5 pF Thermal Resistance Parameter [15] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 165-ball FBGA Unit Package 16.3 C/W 2.1 C/W Note 15. Tested initially and after any design or process change that may affect these parameters. Document Number: 001-75351 Rev. *B Page 19 of 30 CY7C1484BV33 AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms 3.3 V I/O Test Load R = 317 3.3V OUTPUT OUTPUT RL = 50 Z0 = 50 GND 5 pF R = 351 VL = 1.5V INCLUDING JIG AND SCOPE (a) 2.5 V I/O Test Load OUTPUT RL = 50 Z0 = 50 Document Number: 001-75351 Rev. *B INCLUDING JIG AND SCOPE 1 ns 1 ns (c) ALL INPUT PULSES VDDQ GND 5 pF R = 1538 (b) 90% 10% 90% (b) VL = 1.25V (a) 10% R = 1667 2.5V OUTPUT ALL INPUT PULSES VDDQ 10% 90% 10% 90% 1 ns 1 ns (c) Page 20 of 30 CY7C1484BV33 Switching Characteristics Over the Operating Range Parameter [16, 17] Description 250 MHz Unit Min Max VDD(typical) to the First Access [18] 1 – ms tCYC Clock Cycle Time 4 – ns tCH Clock HIGH 2.0 – ns tCL Clock LOW 2.0 – ns tPOWER Clock Output Times tCO Data Output Valid After CLK Rise – 3.0 ns tDOH Data Output Hold After CLK Rise 1.3 – ns Clock to Low Z [19, 20, 21] 1.3 – ns tCHZ Clock to High Z [19, 20, 21] – 3.0 ns tOEV OE LOW to Output Valid – 3.0 ns 0 – ns – 3.0 ns tCLZ tOELZ tOEHZ OE LOW to Output Low Z [19, 20, 21] OE HIGH to Output High Z [19, 20, 21] Setup Times tAS Address Setup Before CLK Rise 1.4 – ns tADS ADSC, ADSP Setup Before CLK Rise 1.4 – ns tADVS ADV Setup Before CLK Rise 1.4 – ns tWES GW, BWE, BWX Setup Before CLK Rise 1.4 – ns tDS Data Input Setup Before CLK Rise 1.4 – ns tCES Chip Enable Setup Before CLK Rise 1.4 – ns tAH Address Hold After CLK Rise 0.4 – ns tADH ADSP, ADSC Hold After CLK Rise 0.4 – ns tADVH ADV Hold After CLK Rise 0.4 – ns tWEH GW, BWE, BWX Hold After CLK Rise 0.4 – ns tDH Data Input Hold After CLK Rise 0.4 – ns tCEH Chip Enable Hold After CLK Rise 0.4 – ns Hold Times Notes 16. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 17. Test conditions shown in (a) of Figure 3 on page 20 unless otherwise noted. 18. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD(minimum) initially before a read or write operation can be initiated. 19. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 3 on page 20. Transition is measured ±200 mV from steady-state voltage. 20. At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z before Low Z under the same system conditions. 21. This parameter is sampled and not 100% tested. Document Number: 001-75351 Rev. *B Page 21 of 30 CY7C1484BV33 Switching Waveforms Figure 4. Read Cycle Timing [22] tCYC CLK tCH t ADS tCL tADH ADSP t ADS tADH ADSC t AS ADDRESS tAH A1 A2 t WES GW, BWE,BW A3 Burst continued with new base address tWEH X t CES Deselect cycle tCEH CE t ADVS tADVH ADV ADV suspends burst OE t Data Out (DQ) High-Z CLZ t OEHZ Q(A1) t OEV t CO t OELZ t DOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A3) t CO Single READ BURST READ DON’T CARE Burst wraps around to its initial state UNDEFINED Note 22. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH. Document Number: 001-75351 Rev. *B Page 22 of 30 CY7C1484BV33 Switching Waveforms (continued) Figure 5. Write Cycle Timing [23, 24] t CYC CLK tCH t ADS tCL tADH ADSP t ADS ADSC extends burst tADH t ADS tADH ADSC t AS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst t WES tWEH BWE, BWX t WES tWEH GW t CES tCEH CE t ADVS tADVH ADV ADV suspends burst OE t Data in (D) High-Z t OEHZ DS t DH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ BURST WRITE Single WRITE DON’T CARE Extended BURST WRITE UNDEFINED Notes 23. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH. 24. Full width write is initiated by either GW LOW; or by GW HIGH, BWE LOW, and BWX LOW. Document Number: 001-75351 Rev. *B Page 23 of 30 CY7C1484BV33 Switching Waveforms (continued) Figure 6. Read/Write Cycle Timing [25, 26, 27] t CYC CLK tCL tCH t ADS tADH t AS tAH ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 t WES tWEH BWE, BW X t CES tCEH CE ADV OE t DS tCO Data In (D) t OELZ High-Z tOEHZ tCLZ Data Out (Q) tDH High-Z Q(A1) Q(A2) Back-to-Back READs D(A5) D(A3) Q(A4) BURST READ Single WRITE DON’T CARE Q(A4+1) Q(A4+2) D(A6) Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes 25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH. 26. The data bus (Q) remains in High Z following a write cycle unless a new read access is initiated by ADSP or ADSC. 27. GW is HIGH. Document Number: 001-75351 Rev. *B Page 24 of 30 CY7C1484BV33 Switching Waveforms (continued) Figure 7. ZZ Mode Timing [28, 29] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 28. Device must be deselected when entering ZZ mode. See Truth Table on page 8 for all possible signal conditions to deselect the device. 29. DQs are in High Z when exiting ZZ sleep mode. Document Number: 001-75351 Rev. *B Page 25 of 30 CY7C1484BV33 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 250 Package Diagram Ordering Code CY7C1484BV33-250BZXC Part and Package Type 51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free Operating Range Commercial Ordering Code Definitions CY 7 C 1484 B V33 - 250 BZ X C Temperature range: C = Commercial = 0 °C to +70 °C X = Pb-free Package Type: BZ = 165-ball FBGA Speed Grade: 250 MHz V33 = 3.3 V Process Technology: B errata fix PCN084636 Part Identifier: 1484 = DCD, 2 M × 36 (72 Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-75351 Rev. *B Page 26 of 30 CY7C1484BV33 Package Diagrams Figure 8. 165-ball FBGA (15 × 17 × 1.40 mm) (0.45 Ball Diameter) Package Outline, 51-85165 51-85165 *D Document Number: 001-75351 Rev. *B Page 27 of 30 CY7C1484BV33 Acronyms Acronym Document Conventions Description Units of Measure CE chip enable CMOS complementary metal-oxide-semiconductor °C degree Celsius EIA electronic industries alliance MHz megahertz FBGA fine-pitch ball grid array µA microampere I/O input/output mA milliampere JEDEC joint electron devices engineering council mm millimeter JTAG joint test action group ms millisecond LSB least significant bit mV millivolt MSB most significant bit ns nanosecond OE output enable ohm SRAM static random access memory % percent TAP test access port pF picofarad TCK test clock V volt TDI test data-in W watt TDO test data-out TMS test mode select TTL transistor-transistor logic Document Number: 001-75351 Rev. *B Symbol Unit of Measure Page 28 of 30 CY7C1484BV33 Document History Page Document Title: CY7C1484BV33, 72-Mbit (2 M × 36) Pipelined DCD Sync SRAM Document Number: 001-75351 Rev. ECN No. Issue Date Orig. of Change ** 3478707 01/17/2012 GOPA Description of Change New data sheet. *A 3508646 01/25/2012 GOPA Changed status from Preliminary to Final. *B 3862706 01/09/2013 PRIT No technical updates. Completing Sunset review. Document Number: 001-75351 Rev. *B Page 29 of 30 CY7C1484BV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2012-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-75351 Rev. *B Revised January 9, 2013 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 30 of 30