CY7C1481BV33 72-Mbit (2 M × 36) Flow-Through SRAM 72-Mbit (2 M × 36) Flow-Through SRAM Features Functional Description ■ Supports 133 MHz bus operations ■ 2 M × 36 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O supply (VDDQ) ■ Fast clock to output time ❐ 6.5 ns (133 MHz version) ■ Provide high performance 2-1-1-1 access rate ■ User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self timed write ■ Asynchronous output enable ■ CY7C1481BV33 available in JEDEC standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package. ■ IEEE 1149.1 JTAG compatible boundary scan ■ ZZ sleep mode option The CY7C1481BV33 is a 3.3 V, 2 M × 36 synchronous flow through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining Chip Enable (CE1), depth expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1481BV33 enables either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses are initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1481BV33 operates from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. Selection Guide Description 133 MHz Unit Maximum Access Time 6.5 ns Maximum Operating Current 335 mA Maximum CMOS Standby Current 150 mA Cypress Semiconductor Corporation Document Number: 001-74857 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 9, 2013 CY7C1481BV33 Logic Block Diagram – CY7C1481BV33 ADDRESS REGISTER A 0, A1, A A [1:0] MODE BURST Q1 COUNTER AND LOGIC Q0 CLR ADV CLK ADSC ADSP DQ D , DQP D BW D BYTE WRITE REGISTER DQ C, DQP C BW C BYTE WRITE REGISTER DQ D , DQP D BYTE WRITE REGISTER DQ C, DQP C BYTE WRITE REGISTER DQ B , DQP B BW B DQ B , DQP B BYTE BYTE WRITE REGISTER MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQ s DQP A DQP B DQP C DQP D WRITE REGISTER DQ A , DQP A BW A BWE DQ A , DQPA BYTE BYTE WRITE REGISTER WRITE REGISTER GW ENABLE REGISTER CE1 CE2 INPUT REGISTERS CE3 OE ZZ SLEEP CONTROL Document Number: 001-74857 Rev. *B Page 2 of 32 CY7C1481BV33 Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 6 Functional Overview ........................................................ 8 Single Read Accesses ................................................ 8 Single Write Accesses Initiated by ADSP ................... 8 Single Write Accesses Initiated by ADSC ................... 8 Burst Sequences ......................................................... 8 Sleep Mode ................................................................. 8 Interleaved Burst Address Table (MODE = Floating or VDD) .................................................. 8 Linear Burst Address Table (MODE = GND) ............... 8 ZZ Mode Electrical Characteristics .............................. 9 Truth Table ........................................................................ 9 Truth Table for Read/Write ............................................ 10 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11 Disabling the JTAG Feature ...................................... 11 Test Access Port (TAP) ............................................. 11 PERFORMING A TAP RESET .................................. 11 TAP REGISTERS ...................................................... 11 TAP Instruction Set ................................................... 11 TAP Controller State Diagram ....................................... 13 TAP Controller Block Diagram ...................................... 14 TAP Timing ...................................................................... 15 TAP AC Switching Characteristics ............................... 15 3.3 V TAP AC Test Conditions ....................................... 16 3.3 V TAP AC Output Load Equivalent ......................... 16 2.5 V TAP AC Test Conditions ....................................... 16 2.5 V TAP AC Output Load Equivalent ......................... 16 Document Number: 001-74857 Rev. *B TAP DC Electrical Characteristics and Operating Conditions ..................................................... 16 Identification Register Definitions ................................ 17 Scan Register Sizes ....................................................... 17 Identification Codes ....................................................... 17 Boundary Scan Exit Order ............................................. 18 Maximum Ratings ........................................................... 19 Operating Range ............................................................. 19 Electrical Characteristics ............................................... 19 Capacitance .................................................................... 20 Thermal Resistance ........................................................ 20 AC Test Loads and Waveforms ..................................... 21 Switching Characteristics .............................................. 22 Timing Diagrams ............................................................ 23 Ordering Information ...................................................... 27 Ordering Code Definitions ......................................... 27 Package Diagrams .......................................................... 28 Acronyms ........................................................................ 30 Document Conventions ................................................. 30 Units of Measure ....................................................... 30 Document History Page ................................................. 31 Sales, Solutions, and Legal Information ...................... 32 Worldwide Sales and Design Support ....................... 32 Products .................................................................... 32 PSoC Solutions ......................................................... 32 Page 3 of 32 CY7C1481BV33 Pin Configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1481BV33 (2 M × 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA MODE A A A A A1 A0 A A VSS VDD A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout Document Number: 001-74857 Rev. *B Page 4 of 32 CY7C1481BV33 Pin Configurations (continued) Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinout CY7C1481BV33 (2 M × 36) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC/288M A CE1 BWC BWB CE3 BWE ADSC ADV A NC NC/144M A CE2 BWD BWA CLK GW OE ADSP A NC/576M DQPC DQC NC DQC VDDQ VDDQ VSS VDD VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ NC/1G DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC NC DQD DQC VDD VDD VDD VDD VDDQ VDDQ NC VDDQ DQB VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VSS DQC NC DQD VDDQ VDDQ NC VDDQ DQB NC DQA DQB DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC A A A TDI A A1 VSS NC TDO A A A A R MODE A A A TMS A0 TCK A A A A Document Number: 001-74857 Rev. *B Page 5 of 32 CY7C1481BV33 Pin Definitions Pin Name A0, A1, A I/O Description InputAddress Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. InputByte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. BWA, BWB, BWC, BWD Synchronous Sampled on the rising edge of CLK. GW CLK InputGlobal Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write Synchronous is conducted (ALL bytes are written, regardless of the values on BWX and BWE). InputClock Clock Input. Captures all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW during a burst operation. CE1 InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. CE3 InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded. OE InputOutput Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW, Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputAdvance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically Synchronous increments the address in a burst cycle. ADSP InputAddress Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputAddress Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. BWE InputByte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted Synchronous LOW to conduct a byte write. ZZ InputZZ “Sleep” Input, Active HIGH. When asserted HIGH, places the device in a non time-critical “sleep” Asynchronous condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull down. DQs I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPX I/OBidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write Synchronous sequences, DQPx is controlled by BWX correspondingly. MODE Input-Static Selects Burst Order. When tied to GND, selects linear burst sequence. When tied to VDD or left floating, selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode Pin has an internal pull up. Document Number: 001-74857 Rev. *B Page 6 of 32 CY7C1481BV33 Pin Definitions (continued) Pin Name VDD VDDQ VSS VSSQ[1] I/O Description Power Supply Power Supply Inputs to the Core of the Device. I/O Power Supply Power Supply for the I/O Circuitry. Ground Ground for the Core of the Device. I/O Ground Ground for the I/O Circuitry. TDO JTAG Serial Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG feature is Output not used, this pin must be left unconnected. This pin is not available on TQFP packages. Synchronous TDI JTAG Serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on Input Synchronous TQFP packages. TMS JTAG Serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used, Input this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. Synchronous TCK JTAG Clock Clock Input to the JTAG Circuit. If the JTAG feature is not used, this pin must be connected to VSS. This pin is not available on TQFP packages. NC – No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. Note 1. Applicable for TQFP package. For BGA package VSS serves as ground for the core and the I/O circuitry. Document Number: 001-74857 Rev. *B Page 7 of 32 CY7C1481BV33 Functional Overview HIGH, and (4) the write input signals (GW, BWE, and BWX) indicate a write access. ADSC is ignored if ADSP is active LOW. All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV) is 6.5 ns (133 MHz device). The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQs is written into the specified address location. The device allows byte writes. All I/Os are tri-stated when a write is detected, even a byte write. Because this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated before the data is presented to DQs. As a safety precaution, the data lines are tri-stated after a write cycle is detected, regardless of the state of OE. The CY7C1481BV33 supports secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable and is determined by sampling the MODE input. Accesses are initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic. It is then presented to the memory core. If the OE input is asserted LOW, the requested data is available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BWX) are ignored during this first clock cycle. If the write inputs are asserted active (see Truth Table for Read/Write on page 10 for appropriate states that indicate a write) on the next clock rise, the appropriate data is latched and written into the device. The device allows byte writes. All I/Os are tri-stated during a byte write. Because this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated after a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1481BV33 provides an on-chip 2-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE selects a linear burst sequence. A HIGH on MODE selects an interleaved burst order. Leaving MODE unconnected causes the device to default to an interleaved burst sequence. Sleep Mode The ZZ input pin is asynchronous. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 00 01 10 11 Single Write Accesses Initiated by ADSC 01 10 11 00 This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted 10 11 00 01 11 00 01 10 Document Number: 001-74857 Rev. *B Page 8 of 32 CY7C1481BV33 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 150 mA tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC – ns tZZI ZZ active to sleep current This parameter is sampled – 2tCYC ns tRZZI ZZ inactive to exit sleep current This parameter is sampled 0 – ns Truth Table The truth table for CY7C1481BV33 follows. [2, 3, 4, 5, 6] Cycle Description Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle, Power Down None H X X L X L X X X L–H Tri-State Deselected Cycle, Power Down None L L X L L X X X X L–H Tri-State Deselected Cycle, Power Down None L X H L L X X X X L–H Tri-State Deselected Cycle, Power Down None L L X L H L X X X L–H Tri-State Deselected Cycle, Power Down None X X X L H L X X X L–H Tri-State Sleep Mode, Power Down None X X X H X X X X X X Tri-State Read Cycle, Begin Burst External L H L L L X X X L L–H Q Read Cycle, Begin Burst External L H L L L X X X H L–H Tri-State Write Cycle, Begin Burst External L H L L H L X L X L–H D Read Cycle, Begin Burst External L H L L H L X H L L–H Q Read Cycle, Begin Burst External L H L L H L X H H L–H Tri-State Next X X X L H H L H L L–H Read Cycle, Continue Burst Q Read Cycle, Continue Burst Next X X X L H H L H H L–H Tri-State Read Cycle, Continue Burst Next H X X L X H L H L L–H Read Cycle, Continue Burst Next H X X L X H L H H L–H Tri-State Write Cycle, Continue Burst Next X X X L H H L L X L–H Write Cycle, Continue Burst Next H X X L X H L L X L–H D Read Cycle, Suspend Burst Current X X X L H H H H L L–H Q Read Cycle, Suspend Burst Current X X X L H H H H H L–H Tri-State Read Cycle, Suspend Burst Current H X X L X H H H L L–H Read Cycle, Suspend Burst Current H X X L X H H H H L–H Tri-State Write Cycle, Suspend Burst Current X X X L H H H L X L–H D Write Cycle, Suspend Burst Current H X X L X H H L X L–H D Q D Q Notes 2. X = Do Not Care, H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a do not care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as outputs when OE is active (LOW). Document Number: 001-74857 Rev. *B Page 9 of 32 CY7C1481BV33 Truth Table for Read/Write The read-write truth table for CY7C1481BV33 follows. [7, 8] Function (CY7C1481BV33) GW BWE BWD BWC BWB BWA Read H H X X X X Read H L H H H H Write Byte A (DQA, DQPA) H L H H H L Write Byte B(DQB, DQPB) H L H H L H Write Bytes A, B (DQA, DQB, DQPA, DQPB) H L H H L L Write Byte C (DQC, DQPC) H L H L H H Write Bytes C, A (DQC, DQA, DQPC, DQPA) H L H L H L Write Bytes C, B (DQC, DQB, DQPC, DQPB) H L H L L H Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB, DQPA) H L H L L L Write Byte D (DQD, DQPD) H L L H H H Write Bytes D, A (DQD, DQA, DQPD, DQPA) H L L H H L Write Bytes D, B (DQD, DQA, DQPD, DQPA) H L L H L H Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) H L L H L L Write Bytes D, B (DQD, DQB, DQPD, DQPB) H L L L H H Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC, DQPA) H L L L H L Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Notes 7. X = Do Not Care, H = Logic HIGH, L = Logic LOW. 8. Table only includes a partial listing of the byte write combinations. Any combination of BWX is valid. An appropriate write is performed based on which byte write is active. Document Number: 001-74857 Rev. *B Page 10 of 32 CY7C1481BV33 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1481BV33 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3 V or 2.5 V I/O logic levels. The CY7C1481BV33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, tie TCK LOW (VSS) to prevent device clocking. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO must be left unconnected. At power up, the device comes up in a reset state, which does not interfere with the operation of the device. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input gives commands to the TAP controller and is sampled on the rising edge of TCK. You can leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram on page 13. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. Test Data-Out (TDO) TAP Registers Registers are connected between the TDI and TDO balls to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls, as shown in the TAP Controller Block Diagram on page 14. At power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to enable fault isolation of the board level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that is placed between the TDI and TDO balls. This shifts the data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The × 36 configuration has a 73-bit long register. The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions are used to capture the contents of the I/O ring. The Boundary Scan Exit Order on page 18 show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 17. The TDO output ball serially clocks data-out from the registers. Whether the output is active depends on the current state of the TAP state machine (see Identification Codes on page 17). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. TAP Instruction Set Performing a TAP Reset Overview To perform a RESET, force TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Identification Codes on page 17. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in this section in detail. At power up, the TAP is reset internally to ensure that TDO comes up in a High Z state. Document Number: 001-74857 Rev. *B Page 11 of 32 CY7C1481BV33 The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction that is executed whenever the instruction register is loaded with all zeros. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-zero instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction is loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High Z state. IDCODE The IDCODE instruction loads a vendor specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO balls and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is in a test logic reset state. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. Be aware that the TAP controller clock only operates at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that may be captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. Note that because the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document Number: 001-74857 Rev. *B Page 12 of 32 CY7C1481BV33 TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCA N 1 SELECT IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-IR 0 1 0 PAUSE-DR 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR 1 0 1 EXIT1-DR 0 1 0 UPDATE-IR 1 0 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Document Number: 001-74857 Rev. *B Page 13 of 32 CY7C1481BV33 TAP Controller Block Diagram 0 Bypass Register 2 1 0 TDI Selection Circuitry Instruction Register Selection Circuitry TDO 31 30 29 . . . 2 1 0 Identification Register x . . . . . 2 1 0 Boundary Scan Register TCK TM S Document Number: 001-74857 Rev. *B TAP CONTROLLER Page 14 of 32 CY7C1481BV33 TAP Timing Figure 3 shows the TAP timing diagram. Figure 3. TAP Timing 1 2 3 4 5 6 Test Clock (TCK ) t TH t TM SS t TM SH t TDIS t TDIH t TL t CY C Test M ode Select (TM S) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CA RE UNDEFINED TAP AC Switching Characteristics Over the Operating Range Parameter [9, 10] Description Min Max Unit Clock tTCYC TCK Clock Cycle Time 50 – ns tTF TCK Clock Frequency – 20 MHz tTH TCK Clock HIGH Time 20 – ns tTL TCK Clock LOW Time 20 – ns tTDOV TCK Clock LOW to TDO Valid – 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 – ns tTMSS TMS Setup to TCK Clock Rise 5 – ns tTDIS TDI Setup to TCK Clock Rise 5 – ns tCS Capture Setup to TCK Rise 5 – ns Output Times Setup Times Hold Times tTMSH TMS hold after TCK Clock Rise 5 – ns tTDIH TDI Hold after Clock Rise 5 – ns tCH Capture Hold after Clock Rise 5 – ns Notes 9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document Number: 001-74857 Rev. *B Page 15 of 32 CY7C1481BV33 3.3 V TAP AC Test Conditions 2.5 V TAP AC Test Conditions Input pulse levels ...............................................VSS to 3.3 V Input pulse levels ............................................... VSS to 2.5 V Input rise and fall times ...................................................1 ns Input rise and fall time ....................................................1 ns Input timing reference levels ......................................... 1.5 V Input timing reference levels ....................................... 1.25 V Output reference levels ................................................ 1.5 V Output reference levels .............................................. 1.25 V Test load termination supply voltage ............................ 1.5 V Test load termination supply voltage .......................... 1.25 V 3.3 V TAP AC Output Load Equivalent 2.5 V TAP AC Output Load Equivalent 1.25V 1.5V 50Ω TDO 50Ω TDO Z O= 50Ω Z O= 50Ω 20pF 20pF TAP DC Electrical Characteristics and Operating Conditions (0 °C < TA < +70 °C; VDD = 3.135 V to 3.6 V unless otherwise noted) Parameter [11] Description Min Max Unit IOH = –4.0 mA VDDQ = 3.3 V Conditions 2.4 – V IOH = –1.0 mA VDDQ = 2.5 V 2.0 – V IOH = –100 µA VDDQ = 3.3 V 2.9 – V VDDQ = 2.5 V 2.1 – V VDDQ = 3.3 V – 0.4 V IOL = 1.0 mA VDDQ = 2.5 V – 0.4 V IOL = 100 µA VDDQ = 3.3 V – 0.2 V – 0.2 V 2.0 VDD + 0.3 V VOH1 Output HIGH Voltage VOH2 Output HIGH Voltage VOL1 Output LOW Voltage IOL = 8.0 mA VOL2 Output LOW Voltage VDDQ = 2.5 V VIH Input HIGH Voltage VDDQ = 3.3 V VDDQ = 2.5 V 1.7 VDD + 0.3 V VIL Input LOW Voltage VDDQ = 3.3 V –0.3 0.8 V VDDQ = 2.5 V –0.3 0.7 V IX Input Load Current –5 5 µA GND < VIN < VDDQ Note 11. All voltages refer to VSS (GND). Document Number: 001-74857 Rev. *B Page 16 of 32 CY7C1481BV33 Identification Register Definitions Bit# 24 is “1” in the ID Register definitions for both 2.5 V and 3.3 V versions of the device. CY7C1481BV33 (2 M × 36) Instruction Field Revision Number (31:29) 000 Device Depth (28:24) 01011 Description Describes the version number Reserved for internal use Architecture/Memory Type (23:18) 000001 Defines memory type and architecture Bus Width/Density (17:12) 100100 Defines width and density Cypress JEDEC ID Code (11:1) 00000110100 ID Register Presence Indicator (0) 1 Enables unique identification of SRAM vendor Indicates the presence of an ID register Scan Register Sizes Register Name Bit Size (× 36) Instruction Bypass 3 Bypass 1 ID 32 Boundary Scan Order – 165-ball FBGA 73 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document Number: 001-74857 Rev. *B Page 17 of 32 CY7C1481BV33 Boundary Scan Exit Order (2 M × 36) Bit # 165-ball ID Bit # 165-ball ID Bit # 165-ball ID Bit # 165-ball ID 1 C1 21 R3 2 D1 22 P2 41 L10 61 B8 42 K11 62 A7 3 E1 23 R4 43 J11 63 B7 4 D2 24 P6 44 K10 64 B6 5 E2 25 R6 45 J10 65 A6 6 F1 26 N6 46 H11 66 B5 7 G1 27 P11 47 G11 67 A5 8 F2 28 R8 48 F11 68 A4 9 G2 29 P3 49 E11 69 B4 10 J1 30 P4 50 D10 70 B3 11 K1 31 P8 51 D11 71 A3 12 L1 32 P9 52 C11 72 A2 13 J2 33 P10 53 G10 73 B2 14 M1 34 R9 54 F10 15 N1 35 R10 55 E10 16 K2 36 R11 56 A10 17 L2 37 N11 57 B10 18 M2 38 M11 58 A9 19 R1 39 L11 59 B9 20 R2 40 M10 60 A8 Document Number: 001-74857 Rev. *B Page 18 of 32 CY7C1481BV33 Maximum Ratings DC Input Voltage ................................ –0.5 V to VDD + 0.5 V Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied ......................................... –55 C to +125 C Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD DC Voltage Applied to Outputs in Tri-State ........................................–0.5 V to VDDQ + 0.5 V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, Method 3015) ................................. >2001 V Latch Up Current ................................................... >200 mA Operating Range Ambient Temperature Commercial 0 °C to +70 °C Industrial –40 °C to +85 °C Range VDD VDDQ 3.3 V– 5% / 2.5 V – 5% to + 10% VDD Electrical Characteristics Over the Operating Range Parameter [12, 13] Description VDD Power Supply Voltage VDDQ IO Supply Voltage VOH VOL VIH VIL IX Test Conditions For 3.3 V I/O For 2.5 V I/O Output HIGH Voltage For 3.3 V I/O, IOH = –4.0 mA For 2.5 V I/O, IOH = –1.0 mA Output LOW Voltage For 3.3 V I/O, IOL = 8.0 mA For 2.5 V I/O, IOL = 1.0 mA Input HIGH Voltage[12] For 3.3 V I/O For 2.5 V I/O [12] Input LOW Voltage For 3.3 V I/O For 2.5 V I/O Input Leakage Current Except ZZ GND VI VDDQ and MODE Input Current of MODE Input = VSS Input Current of ZZ IOZ IDD [14] Output Leakage Current VDD Operating Supply Current ISB1 Automatic CE Power Down Current – TTL Inputs ISB2 Automatic CE Power Down Current – CMOS Inputs ISB3 Automatic CE Power Down Current – CMOS Inputs ISB4 Automatic CE Power Down Current – TTL Inputs Input = VDD Input = VSS Input = VDD GND VI VDD, Output Disabled VDD = Max, IOUT = 0 mA, 7.5 ns cycle, f = fMAX = 1/tCYC 133 MHz Max VDD, Device Deselected, 7.5 ns cycle, VIN VIH or VIN VIL, f = fMAX, 133 MHz inputs switching Max VDD, Device Deselected, 7.5 ns cycle, VIN VDD – 0.3 V or VIN 0.3 V, 133 MHz f = 0, inputs static Max VDD, Device Deselected, 7.5 ns cycle, VIN VDDQ – 0.3 V or VIN 0.3 V, 133 MHz f = fMAX, inputs switching Max VDD, Device Deselected, 7.5 ns cycle, VIN VDD – 0.3 V or VIN 0.3 V, 133 MHz f = 0, inputs static Min 3.135 3.135 2.375 2.4 2.0 – – 2.0 1.7 –0.3 –0.3 –5 Max Unit 3.6 V VDD V 2.625 V – V – V 0.4 V 0.4 V VDD + 0.3 V V VDD + 0.3 V V 0.8 V 0.7 V 5 A –30 – –5 – –5 – – 5 – 30 5 335 A A A A A mA – 200 mA – 150 mA – 200 mA – 165 mA Notes 12. Overshoot: VIH(AC) < VDD +1.5 V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2). 13. TPower-up: assumes a linear ramp from 0 V to VDD(minimum) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 14. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-74857 Rev. *B Page 19 of 32 CY7C1481BV33 Capacitance Parameter [15] Description Test Conditions TA = 25 C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V 100-pin TQFP 165-ball FBGA Unit Max Max CADDRESS Address Input Capacitance CDATA Data Input Capacitance CCTRL Control Input Capacitance 8 8 pF CCLK Clock Input Capacitance 6 6 pF CIO Input/Output Capacitance 5 5 pF 6 6 pF 5 5 pF Thermal Resistance Parameter [15] Description JA Thermal Resistance (Junction to Ambient) JC Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 100-pin TQFP 165-ball FBGA Unit Package Package 24.63 16.3 C/W 2.28 2.1 C/W Note 15. Tested initially and after any design or process change that may affect these parameters. Document Number: 001-74857 Rev. *B Page 20 of 32 CY7C1481BV33 AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms 3.3V IO Test Load R = 317 3.3V OUTPUT OUTPUT RL = 50 Z0 = 50 GND 5 pF R = 351 VL = 1.5V INCLUDING JIG AND SCOPE (a) ALL INPUT PULSES VDDQ 10% 90% 10% 90% 1 ns 1 ns (c) (b) 2.5V IO Test Load R = 1667 2.5V OUTPUT OUTPUT RL = 50 Z0 = 50 GND 5 pF R = 1538 VL = 1.25V (a) Document Number: 001-74857 Rev. *B ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE (b) 10% 90% 10% 90% 1 ns 1 ns (c) Page 21 of 32 CY7C1481BV33 Switching Characteristics Over the Operating Range Parameter [16, 17] tPOWER Description VDD(typical) to the First Access [18] 133 MHz Unit Min Max 1 – ms Clock tCYC Clock Cycle Time 7.5 – ns tCH Clock HIGH 2.5 – ns tCL Clock LOW 2.5 – ns Output Times tCDV Data Output Valid After CLK Rise – 6.5 ns tDOH Data Output Hold After CLK Rise 2.5 – ns 3.0 – ns – 3.8 ns – 3.0 ns 0 – ns – 3.0 ns [19, 20, 21] tCLZ Clock to Low Z tCHZ Clock to High Z [19, 20, 21] tOEV OE LOW to Output Valid tOELZ tOEHZ OE LOW to Output Low Z [19, 20, 21] OE HIGH to Output High Z [19, 20, 21] Setup Times tAS Address Setup Before CLK Rise 1.5 – ns tADS ADSP, ADSC Setup Before CLK Rise 1.5 – ns tADVS ADV Setup Before CLK Rise 1.5 – ns tWES GW, BWE, BWX Setup Before CLK Rise 1.5 – ns tDS Data Input Setup Before CLK Rise 1.5 – ns tCES Chip Enable Setup 1.5 – ns tAH Address Hold After CLK Rise 0.5 – ns tADH ADSP, ADSC Hold After CLK Rise 0.5 – ns tWEH GW, BWE, BWX Hold After CLK Rise 0.5 – ns Hold Times tADVH ADV Hold After CLK Rise 0.5 – ns tDH Data Input Hold After CLK Rise 0.5 – ns tCEH Chip Enable Hold After CLK Rise 0.5 – ns Notes 16. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 17. Test conditions shown in (a) of Figure 4 on page 21 unless otherwise noted. 18. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD(minimum) initially, before a read or write operation can be initiated. 19. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 21. Transition is measured ±200 mV from steady-state voltage. 20. At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. The device is designed to achieve High Z before Low Z under the same system conditions. 21. This parameter is sampled and not 100% tested. Document Number: 001-74857 Rev. *B Page 22 of 32 CY7C1481BV33 Timing Diagrams Figure 5. Read Cycle Timing [22] tCYC CLK t t ADS CH t CL tADH ADSP t ADS tADH ADSC t AS tAH A1 ADDRESS A2 t WES t WEH GW, BWE, BWX t CES Deselect Cycle t CEH CE t ADVS t ADVH ADV ADV suspends burst OE t OEV t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t CDV t OELZ t CHZ t DOH Q(A2) Q(A2 + 1) Q(A2 + 2) t CDV Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note 22. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH. Document Number: 001-74857 Rev. *B Page 23 of 32 CY7C1481BV33 Timing Diagrams (continued) Figure 6. Write Cycle Timing [23, 24] t CYC CLK t t ADS CH t CL tADH ADSP t ADS ADSC extends burst tADH t ADS tADH ADSC t AS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst t WES tWEH BWE, BW X t WES t WEH GW t CES tCEH CE t ADVS tADVH ADV ADV suspends burst OE t Data in (D) High-Z t DS t DH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) OEHZ Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Notes 23. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH. 24. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BWX LOW. Document Number: 001-74857 Rev. *B Page 24 of 32 CY7C1481BV33 Timing Diagrams (continued) Figure 7. Read/Write Cycle Timing [25, 26, 27] tCYC CLK t t ADS CH t CL tADH ADSP ADSC t AS ADDRESS A1 tAH A2 A3 A4 t WES t A5 A6 WEH BWE, BW X t CES tCEH CE ADV OE t DS Data In (D) Data Out (Q) High-Z t OEHZ Q(A1) tDH t OELZ D(A3) D(A5) Q(A2) Back-to-Back READs D(A6) t CDV Q(A4) Single WRITE Q(A4+1) BURST READ DON’T CARE Q(A4+2) Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes 25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH. 26. The data bus (Q) remains in High Z following a write cycle, unless a new read access is initiated by ADSP or ADSC. 27. GW is HIGH. Document Number: 001-74857 Rev. *B Page 25 of 32 CY7C1481BV33 Timing Diagrams (continued) Figure 8. ZZ Mode Timing [28, 29] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 28. Device must be deselected when entering ZZ mode. See Truth Table on page 9 for all possible signal conditions to deselect the device. 29. DQs are in High Z when exiting ZZ sleep mode. Document Number: 001-74857 Rev. *B Page 26 of 32 CY7C1481BV33 Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 133 Ordering Code Package Diagram Part and Package Type CY7C1481BV33-133AXI 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free CY7C1481BV33-133BZI 51-85165 165-ball FBGA (15 × 17 × 1.4 mm) CY7C1481BV33-133BZXC 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free Operating Range lndustrial Commercial Ordering Code Definitions CY 7 C 1481 B V33 - 133 XX X X Temperature range: X = C or I C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C X = Pb-free Package Type: XX = A or BZ A = 100-pin TQFP (3 chip enable); BZ = 165-ball FBGA Speed Grade: 133 MHz V33 = 3.3 V VDD Die Revision: B errata fix PCN084636 Part Identifier: 1481 = SCD, 2 Mb × 36 (72 Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-74857 Rev. *B Page 27 of 32 CY7C1481BV33 Package Diagrams Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050 51-85050 *D Document Number: 001-74857 Rev. *B Page 28 of 32 CY7C1481BV33 Package Diagrams (continued) Figure 10. 165-ball FBGA (15 × 17 × 1.4 mm) (0.45 Ball Diameter) Package Outline, 51-85165 51-85165 *D Document Number: 001-74857 Rev. *B Page 29 of 32 CY7C1481BV33 Acronyms Acronym Document Conventions Description Units of Measure CE chip enable CMOS complementary metal-oxide-semiconductor °C degree Celsius EIA electronic industries alliance MHz megahertz FBGA fine-pitch ball grid array µA microampere I/O input/output mA milliampere JEDEC joint electron devices engineering council mm millimeter OE output enable ms millisecond SRAM static random access memory mV millivolt TQFP thin quad flat pack ns nanosecond TTL transistor-transistor logic ohm % percent pF picofarad V volt W watt Document Number: 001-74857 Rev. *B Symbol Unit of Measure Page 30 of 32 CY7C1481BV33 Document History Page Document Title: CY7C1481BV33, 72-Mbit (2 M × 36) Flow-Through SRAM Document Number: 001-74857 Rev. ECN No. Issue Date Orig. of Change ** 3466988 01/17/2012 GOPA Description of Change New data sheet. *A 3508574 01/25/2012 GOPA Changed status from Preliminary to Final. *B 3862706 01/09/2013 PRIT No technical updates. Completing Sunset review. Document Number: 001-74857 Rev. *B Page 31 of 32 CY7C1481BV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2012-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-74857 Rev. *B Revised January 9, 2013 Page 32 of 32 i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.