ETC NCP1239D

NCP1239
Low−Standby High
Performance PWM Controller
Housed in SO−16 the NCP1239 represents a major leap toward
ultra−compact Switch Mode Power Supplies specifically tailored for
medium to high power off−line applications, e.g. notebook adapters.
The NCP1239 offers everything needed to build a rugged and efficient
power supply, including a dedicated event management to drive a
Power Factor Correction front−end circuitry. The circuit disables the
front−end PFC stage while still in fault or standby conditions by
interrupting the PFC controller powering for improved no−load
consumption figures. As soon as normal operating mode recovers, the
NCP1239 feeds back the PFC that wakes−up.
When power demand is low, the IC automatically enters the
so−called skip cycle mode and provides excellent efficiency at light
loads. Because this occurs at a user adjustable low peak current, no
acoustic noise takes place.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Current−Mode Operation with Internal Ramp Compensation
Internal High−Voltage Current Source for loss−less Start−up
Adjustable Skip−Cycle Capability
Selectable Soft−Start Period
Internal Frequency Dithering for Improved EMI Signature
Go−to−Standby Signal for PFC Front−Stage
Large Vcc Operation from 12.2 V to 25 V
500 mV Over−Current Limit
±5% 500 mA/−800 mA Peak Current Capability
5 V / 10 mA Pinned−out Reference Voltage
Adjustable Switching Frequency up to 250 kHz.
Over−Load Protection Independent of the Auxiliary Vcc
Adjustable Over−Power Compensation
• High Power AC/DC Adapters for Notebooks etc.
• Offline Battery Chargers
• Set−Top Boxes Power Supplies, TV, Monitors etc.
February, 2004 − Rev. 0
MARKING
DIAGRAM
16
SO−16
FD SUFFIX
CASE 751B
16
NCP1239FD
AWLYWW
1
1
NCP1239 = Device Code
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
PIN CONNECTIONS
1
16
GTS
REF5V
Fault Detect
Rt
Brown−out
SS / Timer
Skip Adjust
FB
HV
NC
NC
Vcc
Drv
Gnd
CS
Over Power
Limit
ORDERING INFORMATION
Device
NCP1239FDR2
Typical Applications
 Semiconductor Components Industries, LLC, 2004
http://onsemi.com
Package
Shipping†
SO−16
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1
Publication Order Number
NCP1239/D
NCP1239
Vbulk
Rbo1
R10
to PFC_VCC
OVP REF5V
+
NTC
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
Vout
REF5V (5V/10mA)
Thermistor
+
CBulk
1
BO
Rbo2
Gnd
VCC
Rramp
Rcomp
NCP1239
Rt
Cbo
+
Css
Gnd
Figure 1. Typical Application Example
MAXIMUM RATINGS
Rating
Symbol
Power Supply Voltage
Vcc
25
V
V
500
V
RθJA
145
°C/W
TJMAX
150
°C
−60 to +150
°C
2
kV
200
V
Maximum Voltage on pin 16 (HV)
Maximum Junction Temperature
Storage Temperature Range
ESD Capability, HBM model (All pins except Vcc and HV)
ESD Capability, Machine Model
http://onsemi.com
2
Unit
−0.3, +10
Pins 1 to 10 (except Vref pin) maximum voltage
Thermal Resistance − Junction−to−Air, SOIC version
Value
NCP1239
ELECTRICAL CHARACTERISTICS (For typical values Tj = 25°C, for min/max values Tj = 0°C to +125°C, Max TJ = 150°C,
VCC = 20 V unless otherwise noted.)
Rating
Symbol
Pin
Min
Typ
Max
Unit
Supply Section
VCCON
Turn−on threshold level, Vcc going up
13
15.5
16.4
17.5
V
VCCOFF
Minimum operating voltage after turn−on
13
10.5
11.2
12.2
V
HYST1
Difference (VccON−VccOFF)
13
4.5
5.2
−
V
VCClatch
Vcc decreasing level at which the latch−off phase ends
13
6.5
6.9
7.2
V
VCCreset
Vcc level at which the internal logic gets reset
13
−
4.0
−
V
ICC1
Internal IC consumption, no output load on pin 12 (@ IRt = 20 µA)
13
−
2.1
3.0
mA
ICC2
Internal IC consumption, 1 nF output load on pin 12, FSW = 65 kHz
13
−
3.1
3.8
mA
ICC2
Internal IC consumption, 1 nF output load on pin 12, FSW = 100 kHz
13
−
3.9
5.0
mA
ICC2
Internal IC consumption, 1 nF output load on pin 12, FSW = 130 kHz
13
−
4.6
5.9
mA
ICC3
Internal IC consumption, latch−off phase
13
−
400
700
µA
High−Voltage Current Source (sunk by pin16), Vcc = 10 V
16
2.2
5.6
9.6
mA
Start−up Charge Current flowing out of the Vcc pin, Vcc=10 V
13
1.7
5.2
7.2
mA
High−Voltage Current Source, Vcc = 0
16
−
6.8
−
mA
4.7
4.6
5.0
4.9
5.2
5.1
Internal Start−up Current Source
IC1_hv
IC1_Vcc
IC2
5 V Reference Voltage (REF5V)
REF5V
Iref
Reference Voltage
@ no load on pin2
@ Ipin2 = 5 mA
2
V
Current Capability
2
5.0
10
−
mA
Drive Output
Vcl
Output Voltage Positive Clamp
12
11.5
13.6
16
V
Trise
Output Voltage rise−time @ CL = 1 nF, 10−90% of output signal
12
−
40
−
ns
Tfall
Output Voltage fall−time @ CL = 1 nF, 10−90% of output signal
12
−
20
−
ns
Vsource
High State Voltage Drop @ Ipin12 = 3 mA and Vcc = 12 V
12
−
2.5
3.3
V
Isource
Source Current Capability (@ Vpin12 = 0 V)
12
−
500
−
mA
ROL
Sink Resistance @ Vpin12=1 V
12
−
3.8
7.5
Ω
Isink
Sink Current Capability (@ Vpin12 = 10 V)
12
−
800
−
mA
Recommended Switching Frequency Range
12
25
−
250
kHz
Vosc
Pin 4 Voltage @ Rt = 100 kΩ
4
−
1.6
−
V
Kosc
Product (Switching Freq. times the Rt pin 4 resistance) (Note 1)
@ 65 kHz and 130 kHz
6050
6500
6950
Oscillator
fsw
kHz*kΩ
∆fsw
Internal modulation swing, in percentage of Fsw
−
±3.5
−
%
Dmax
Maximum duty−cycle
74
80
85
%
60
120
80
160
100
185
0.48
0.47
0.50
0.50
0.52
0.52
−
140
220
Current Control
Iocp
Vopl
TDEL_OCP
Internal Current source of the Over Power Limit Pin
@ 1 V on pin 5 and Vpin9 = 0.5 V
@ 2 V on pin 5 and Vpin9 = 0.5 V
9
Over Power Limitation Threshold
@ TJ = 25°C
@ TJ = 0°C to 125°C
9
Propagation delay from Vpin9 > Vopl to gate turned off
(pin12 loaded by 1 nF)
9
http://onsemi.com
3
µA
V
ns
NCP1239
ELECTRICAL CHARACTERISTICS (For typical values Tj = 25°C, for min/max values Tj = 0°C to +125°C, Max TJ = 150°C,
VCC = 20 V unless otherwise noted.)
Symbol
Rating
Pin
Min
Typ
Max
Unit
Maximum internal current set−point
10
0.84
0.90
0.95
V
Propagation delay from Vpin10 > Ilimit to gate turned off
(pin12 loaded by 1 nF)
10
−
140
220
ns
Current Control
ILimit
TDEL CS
TLEB−65kHz
Leading Edge Blanking Duration (pins 9 and 10) @ 65 kHz
9, 10
−
420
−
ns
TLEB−130kHz
Leading Edge Blanking Duration (pins 9 and 10) @ 130 kHz
9, 10
−
230
−
ns
Soft Start or Jittering charge current @ Vpin6 = 2.4 V
6
60
95
110
µA
Idisch
Jittering Discharge Current @ Vpin6 = 2.4 V
6
80
115
135
µA
Vjitter
Jittering Saw−Tooth Lower Threshold
6
1.67
1.80
1.89
V
VjitterH
Jittering Saw−Tooth Upper Threshold
6
2.85
3.00
3.20
V
VtimerL
Timer Peak Threshold
6
4.0
4.3
4.6
V
ItimerC
Timer Charge Current @ Vpin6 = 3.5 V and pin 8 open
6
4.1
5.5
6.6
µA
ItimerD
Timer Discharge Current @ Vpin6 = 3.5 V and pin8 open
6
−
400
−
µA
Internal Pull−up Resistor
8
−
20
−
kΩ
Source Current @ Vpin8 = 0.5 V
8
−
200
−
µA
Pin 8 to current set−point division ratio
−
−
3.0
−
−
Soft Start and Timer
Ich
Feedback Section
Rup
Ifb
Iratio
Internal Ramp Compensation
Rramp
Internal Resistor
10
−
32
−
kΩ
Vramp
Internal Saw−Tooth Amplitude
10
−
3.2
−
V
Skipping Mode and Stand−By Management
Rgts
Pin 1 output impedance in stand−by state
(pin 8 grounded, Vpin6 > 4.5 V) @ Vcc = 12.5 V
1
4.0
8.0
18
kΩ
Igts
Sink Current Source in Normal Mode
@ Vpin8 = 2 V, pin7 open @ Vcc−Vpin1=0.7 V
1
0.6
1.0
−
mA
Default Feed−Back Level for Skip Cycle Operation and Stand−by
Detection
7
380
430
480
mV
FB_stby−out
Default Feed−Back Level to Leave Standby
7
650
740
810
mV
Vstby−out/Vskip
Ratio leave stand−by set−point to skip cycle set−point
1.5
1.7
1.9
−
−
110
−
kΩ
−
3.0
−
−
FB−skip
Rpin7
Internal pin 7 Impedance
7
Pin 7 to skipping set−point ratio
Brown−Out Detection
BOthH
Brown−Out Detection Upper Threshold
5
0.45
0.50
0.55
V
BOthL
Brown−Out Detection Low Threshold
5
0.20
0.24
0.28
V
BOhyst
Brown−Out Hysteresis
5
0.20
0.26
0.30
V
Protections
TSD
Vfault
°C
Thermal Shutdown:
Thermal Shutdown Threshold
Hysteresis
140
30
Fault Detection Threshold
3
2.2
2.4
2.6
V
1. The nominal switching frequency fsw equals: fsw = KOSC / Rt. The implemented jittering makes the switching frequency continuously vary
around this nominal value (+/−3.5% variation).
http://onsemi.com
4
NCP1239
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
1
GTS
Shuts the PFC down in
standby
The stand−by detection block changes pin1 state in accordance to the mode
(stand−by or normal mode). Pin1 is designed to drive an external pnp transistor
that connects or disconnects the NCP1239’s Vcc to the PFC’s.
Pin Description
2
REF5V
A 5V reference voltage
This pin helps to internally bias the controller but can also be used to power
surrounding logic gates for any purposes. The typical output current is 10 mA. This
voltage source is disabled during the circuit start−up and latched−off phases. A
100 nF filtering capacitor must be placed between pin2 and ground.
3
Fault Detect
Enables to permanently
shutdown the part
If the pin3 voltage exceeds 2.4 V, the circuit is permanently shut down. This pin
can be used to monitor the voltage accross a thermistor in order to protect the
application from excessive heating and/or to detect an Over−Voltage condition.
4
Rt
Timing resistor
5
Brown−Out
Brown−Out
6
SS / Timer
Performs soft−start and
fault timeout
During Power on and fault conditions, the capacitor connected to this pin ensures a
soft−start period. When a fault is detected, this pin is internally brought high by a
current source. If 4.3 V are reached, the fault is confirmed and the circuit enters an
auto−recovery burst mode, otherwise the pin goes back to a lower value and
oscillates to perform frequency jittering.
7
Skip Adjust
Adjust skip level
By adjusting the skip cycle level, it is possible to fight against noisy transformers
and modify the stand−by detection thresholds. Keep pin7 open to operate with the
default levels (skip threshold set−point: 140 mV, normal mode recovery set−point:
250 mV).
8
FB
Feedback signal
An opto−coupler collector pulls this pin low to regulate
9
Over Power
Limit
Enables a precise peak
current clamp and then an
accurate Over Power
Detection
This pin delivers a current proportional to Vpin5, an image of the high voltage rail.
Inserting a resistor between pin 9 and the current sense resistor, an offset
proportional to the input voltage is built. Such offset compensates the circuit and
power switch propagation delays for an accurate power limitation in the whole input
voltage range.
10
CS
The current sense input
This pin receives the primary current information via a sense element. By inserting
a resistor in series with this pin, it becomes possible to introduce ramp
compensation.
11
Ground
The IC ground
12
Drv
Drives the MOSFET
13
Vcc
Supplies the controller
14
NC
−
Creepage distance
15
NC
−
Creepage distance
16
HV
The high−voltage startup
Pin4 resistor allows a precise frequency programming from 20 kHz up to 250 kHz.
This pin receives a portion of the Bulk capacitor to authorize operation above a
certain level of mains only. It also serves to elaborate an offset voltage on pin 9
used for Over Power Compensation.
−
By offering up to +500 mA/−800 mA peak, this pin lets you drive large Qg
MOSFET’s. It is clamped to 16 V maximum not to exceed the maximum
gate−source voltage of most power MOSFET’s.
This pin accepts up to 25 V from an auxiliary winding
This pin connects to the bulk capacitor to generate the start−up current
http://onsemi.com
5
NCP1239
FB<Vpin1 => Skip high
Skip
+
Skip
7
adjust
−
FB
100k
+
Stby_detect
S
UVLOs
Latch
Reset
Q
15r
450mV
16 HV
R
+
Q
25r
Internal
Thermal
Shutdown
−
FB>1.6*Vpin1 =>Stby_detect RESET
15
UVLO
Fault
detect
TSD
3
(Vcc<VccOFF)
−
OVL
2.5V
+
S
regOUT
Fault
14
Q
Vcc
R
Q
Vdd
PFC_Vcc
Regul
Vcc < 4V
10k
1
pfcON
stdwn
pfcOFF
1mA
13 Vcc
Start−Up_Phase
Stby
Vstop
S
Q
Vdd
Vdd
R
Q
OVL
Divider by 2
Vcc<7V
Stby_detect
SS / timer
Soft−Start
and timer
management
6
Error_Flag
Output
Buffer
OUTon
Soft Start
Ipk limit
REF5V 2
12 Drv
Jittering
Modulation
14V
clamp
+
5V
Ramp
Compensation
pfcON
3.2V
32k
11
CLK
−
5
PWM Latch
BO_in
BO
BO_out
+
+
0.5V / 0.25V
Gnd
S
Q
R
Q
10 CS
LEB
Vdd
Vstop
Vdd
BO_in
Oscillator
Rt 4
75A/V x Vpin5
CLK
−
+
2.5V
9 Over Power
Limit
Skip
Jittering
Modulation
LEB
Vdd
+
−
”Jittered”
Reference
−
+
+
0.5V
20k
FB 8
/3
0.9V
to Skip
Soft Start
Ipk limit
Error flag
Figure 2. Internal Circuit Architecture
http://onsemi.com
6
NCP1239
TYPICAL PERFORMANCE CHARACTERISTICS
8.5
8.0
7.5
6.0
IC2 (mA)
IC1_HV, (mA)
7.0
5.0
6.5
5.5
4.0
3.0
−25
0
25
50
75
100
4.5
−25
125
0
Figure 3. High Voltage Current Source vs.
Temperature @ VCC = 10 V
Pin16 Leakage Current (A)
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 4. High Voltage Current Source vs.
Temperature @ VCC = 0 V
50
16.7
45
16.6
40
16.5
VCC_on (V)
35
30
25
16.4
16.3
16.2
20
16.1
15
10
−25
25
0
25
50
75
100
16.0
−25
125
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. VCC Start−up Threshold vs. Temperature
Figure 5. High Voltage Pin Leakage Current vs.
Temperature
6.90
11.40
11.30
6.88
VCC_off (V)
VCCLATCH (V)
11.20
11.10
11.00
6.86
6.84
10.90
10.80
−25
0
25
50
75
100
125
6.82
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. VCC Turn−Off Threshold vs. Temperature
Figure 8. VCC Latched−Off vs. Temperature
http://onsemi.com
7
125
NCP1239
TYPICAL PERFORMANCE CHARACTERISTICS
2.80
5.0
2.60
4.5
2.40
4.0
ICC2 (mA)
ICC1 (mA)
130 kHz
2.20
3.5
65 kHz
2.00
3.0
1.80
2.5
1.60
−25
0
25
50
75
100
2.0
−25
125
100 kHz
0
TEMPERATURE (°C)
25
50
75
100
125
TEMPERATURE (°C)
Figure 9. No Load Circuit Consumption vs.
Temperature
Figure 10. Circuit Consumption (1nF on driver pin 12)
vs. Temperature
0.60
5.05
0.55
5.00
0 mA
4.95
0.45
REF5V (V)
ICC3 (mA)
0.50
0.40
0.35
4.90
5 mA
4.85
4.80
0.30
10 mA
4.75
0.25
0.20
−25
0
25
50
75
100
4.70
−25
125
0
TEMPERATURE (°C)
25
50
75
100
125
TEMPERATURE (°C)
Figure 11. Latched−Off Mode Consumption vs.
Temperature
Figure 12. REF5V Voltage Source vs. Temperature
2.75
7.0
2.70
6.0
5.0
2.60
SINK ()
Vdrop (V)
2.65
2.55
2.50
4.0
3.0
2.45
2.0
2.40
2.35
−25
0
25
50
75
100
1.0
−25
125
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Driver High State Voltage Drop vs.
Temperature
Figure 14. Driver Sink Resistance vs. Temperature
http://onsemi.com
8
NCP1239
TYPICAL PERFORMANCE CHARACTERISTICS
83
82
14.5
81
Dmax (%)
Vcl CLAMP VOLTAGE (V)
15.0
14.0
13.5
80
79
13.0
78
12.5
−25
0
25
50
75
100
77
−25
125
0
TEMPERATURE (°C)
65 kHz
125
160
BO=2 V
6540
140
130 kHz
6520
Iocp (A)
Kosc (kHz*k)
100
180
6560
6500
6480
120
100
80
6460
BO=1 V
200 kHz
6440
0
25
60
50
75
100
40
−25
125
0
Figure 17. Oscillator Kosc Parameter vs. Temperature
(Kosc=fsw*Rpin4)
0.52
0.92
0.51
0.91
ILimit (V)
0.93
0.50
0.89
0.48
0.88
50
75
75
100
125
0.90
0.49
25
50
Figure 18. Pin9 Current vs. Temperature
(@ Vpin9 = 0.5 V)
0.53
0
25
TEMPERATURE (°C)
TEMPERATURE (°C)
Vopl (V)
75
Figure 16. Maximum Duty Cycle vs. Temperature
6580
0.47
−25
50
TEMPERATURE (°C)
Figure 15. Driver Voltage Clamp vs. Temperature
6420
−25
25
100
0.87
−25
125
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. Over−Power Limitation Threshold vs.
Temperature
Figure 20. Maximum Current Set−Point vs.
Temperature
http://onsemi.com
9
125
NCP1239
TYPICAL PERFORMANCE CHARACTERISTICS
450
770
445
760
FBstby−out (mV)
FBskip (mV)
440
435
430
425
750
740
730
420
720
415
410
−25
0
25
50
75
100
710
−25
125
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Default Feed−back Threshold for
Stand−by Detection vs. Temperature
Figure 22. Default Feed−back Level for Normal
Operation Recovery
0.497
0.250
0.496
0.248
BO_th_L (V)
0.494
0.493
0.246
0.244
0.492
0.242
0.491
0.490
−25
0
25
50
75
100
125
0.240
−25
0
TEMPERATURE (°C)
25
75
100
Figure 24. Brown−Out Low Threshold vs.
Temperature
2.48
2.46
2.44
2.42
2.40
2.38
2.36
−25
50
TEMPERATURE (°C)
Figure 23. Brown−Out Upper Threshold vs.
Temperature
Vfault (V)
BO_th_H (V)
0.495
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 25. Fault Detect Threshold vs. Temperature
http://onsemi.com
10
125
NCP1239
SS / timer pin
Fault Management
4.3V
New Start−up
attempt
Fault confirmed
100ms
Fault not confirmed
100ms
10ms Jittering
3.0V
1.8V
fmax
fmin
OVL signal
(Over−Load)
1V
Error flag
1V
Error flag
1V
Error flag
Reset at UVLO
PFC off
PFC off
PFC on
DRV
Vcc
16.4V
11.2V
Fault occurs here
6.9V
Fb is ok
In the example with Cpin6=390 nF, the pin 6 capacitor approximately forces a 7.5 ms soft−start,
a 10 ms jittering period and a 100 ms timer.
Figure 26. Fault Management
http://onsemi.com
11
NCP1239
Stand−by Detection
Vpin6
(SS/timer)
Standby is not confirmed
Standby is confirmed,
4.3V
Jittering 10ms
3.0V
1.8V
100ms
delay
100ms
PFC is down
PFC running
Bunches of pulses
Drv
FB
No delay
FB−stby−out (1.7*Vpin7)
FB−skip (Vpin7)
Stby_detect latch is armed
Stby_detect latch is reset
Skip activity
Fb is ok
Standby is entered
Standby is left
In the example with Cpin6=390 nF, the pin 6 capacitor approximately forces a 7.5 ms soft−start,
a 10 ms jittering period and a 100 ms timer.
Figure 27. Stand−by Detection
http://onsemi.com
12
NCP1239
APPLICATION INFORMATION
a stand−by situation. Pin1 state changes in accordance to the
detected mode (stand−by or normal mode). Simply connect
a pnp transistor between the NCP1239 Vcc and the PFC
controller one and drive it using pin1, to enable the PFC
stage in normal mode and disable it in stand−by.
Soft−start: the capacitor connected to pin6 provides a
soft−start sequence that precludes the main power switch
from being stressed upon start−up. The same voltage is also
used to perform frequency jittering and timing for the fault
condition detection.
Major Fault Detection: the circuit detects when pin3
voltage exceeds 2.4 V. When this occurs, the NCP1239
considers that a major fault is present and as a consequence,
the circuit gets permanently latched−off. In this mode, the
circuit needs the Vcc to go down below 4 V to reset, for
instance when the user un−plugs the SMPS. This capability
is mainly intended to detect an over−voltage condition
or/and an over−heating of the application that would be
sensed by a thermistor.
Brown−out detection: by monitoring the level on pin5
during normal operation, the controller protects the SMPS
against low mains conditions. When the pin5 voltage falls
below 250 mV, the controllers stops pulsing until this level
goes back to 500 mV to prevent any instability.
Short−circuit protection: short−circuit and especially
over−load protections are difficult to implement when a
strong leakage inductance affects the transformer (the
auxiliary winding level does not properly collapse…). Here,
every time the feed−back pin is at its maximum (higher than
5 V practically), an error flag is asserted and a time period
starts, thanks to pin6 capacitor. If pin6 reaches 4.6 V while
the error flag is still present, the controller stops the pulses
and goes into a latch−off phase, operating in a
low−frequency burst−mode. As soon as the fault disappears,
the SMPS resumes its operation. The latch−off phase can
also be initiated, more classically, when Vcc drops below
UVLO (11.2 V typical).
Adjustable frequency and Internal dithering for
improved EMI signature: pin4 offers a means to precisely
adjust the switching frequency through a simple resistor to
ground. Frequency operation is allowed up to 250 kHz. By
modulating the internal switching frequency with the pin6
saw−tooth (100 Hz with 390 nF), natural energy spread
appears and softens the controller’s EMI signature.
5 V reference voltage: a 5 V regulator is provided to help
biasing any external circuitry in the vicinity of the controller.
This reference voltage can typically supply up to 10 mA.
The NCP1239 includes all necessary features to help
building a rugged and safe switch−mode power supply. The
following details the major benefits brought by
implementing the NCP1239 controller:
Current−mode operation with internal ramp
compensation: implementing peak current mode control,
the NCP1239 offers an internal ramp compensation signal
that can easily be summed up to the sensed current.
Subharmonic oscillations can thus be fought via the
inclusion of a simple resistor,
500 mV Current Sense threshold for Over Power Limit:
the NCP1239 operating in current mode, the circuit pin10
monitors the current to modulate its level according to the
power demand. Due to the ramp compensation, one must
generally note that the pin10 voltage is not the exact image
of the inductor current. A precise current limitation being
essential, the NCP1239 features a separate current sense pin
(pin9) for an accurate over−current detection. The low
threshold of this protection (500 mV) avoids excessive
losses in the current sense resistor and improves the
efficiency. In addition, pin9 sources a current that
proportional to the high−voltage rail, compensates the
current−sense and turn off delays at high line. A resistor
inserted between pin9 and the sensing resistor offsets the
pin9 current−sense information to build a precise overload
protection, independent of the mains input.
Large Vcc operation: the NCP1239 offers an extended
Vcc range up to 25 V, bringing greater flexibility in Flyback
or Forward applications.
Internal high−voltage startup switch: reaching low
levels of stand−by power represents a difficult exercise
when the controller requires an external, lossy, resistor
connected to the bulk capacitor. Thanks to an internal logic,
the controller disables the high−voltage current source after
start−up which no longer hampers the consumption in
no−load situations.
Skip−cycle capability: a continuous flow of pulses is not
compatible with no−load standby power requirements.
Slicing the switching pattern in bunch of pulses drastically
reduces overall losses but can, in certain cases, bring
acoustic noise in the transformer. Thanks to a skip operation
taking place at low peak currents only, no mechanical noise
appears in the transformer. Furthermore, the skip threshold
is made programmable to allow the best trade−off between
noise and efficiency.
Stand−by detect / Shutdown of the PFC front−stage: The
NCP1239 incorporates an internal logic that is able to detect
http://onsemi.com
13
NCP1239
Start−up Sequence
When the power supply is first connected to the mains
outlet, the internal current source (typically 5.2 mA) is
biased and charges up the Vcc capacitor. When the voltage
on this Vcc capacitor reaches the VccON level (typically
16.4 V), the current source turns off and no longer wastes
any power. At this time, the energy stored by the Vcc
capacitor serves to supply the controller and the auxiliary
supply is supposed to take over before Vcc collapses below
VccOFF. Figure 28 shows the internal arrangement of this
structure:
16
16.4 V /
11.2 V
+
−
As soon as Vcc reaches 16.4 V, driving pulses are
delivered on pin12 and the auxiliary winding grows up the
Vcc pin. Because the output voltage is below the target (the
SMPS is starting up), the feed−back pin is at its maximum
voltage. A resistor divider outputs the third of the feed−back
voltage that forms the current set−point. This set−point is
clamped and the limitation level slowly increases until it
reaches 0.9V during the soft start time. In nominal operation,
the set−point clamp keeps equal to 0.9 V (refer to Figure 29).
As soon as the feed−back voltage is high enough to
activate the 0.9 V set−point clamp (during the start−up
period but also anytime an overload occurs), an internal
error flag is asserted, testifying that the system is pushed to
the maximum power. At that moment, a 100 ms time period
(typically, with Cpin6=390 nF that also corresponds to 7.5
ms soft −start) starts while a logic block observes this error
flag. If the error flag keeps asserted all along the 100ms
period, then the controller assumes that the power supply
really undergoes a fault condition and immediately stops all
pulses to enter a safe burst operation. The 100 ms timer
enables to distinguish a start−up phase (shorter than 100 ms)
from an over−load condition. If the error flag is released
before the 100 ms period has elapsed, the controller
concludes that no error is present and resets the timer to use
it for other purposes (e.g. frequency dithering).
HV
5.2 mA / 0
13
CVcc
Aux
10
The current source brings Vcc above 16.4 V and then turns off
Figure 28.
to
Stand−by Management
(Skipping, GTS)
Vdd
CLK
PWM Latch
20k
S
8
Q
Q
Vin
Feed−back
/3
R
0.9 V
Current Sense
Comparator
Soft−start
oscillator
−
Ramp Compensation
Rramp
+
10
LEB
Current Sense
Rsense
pin5 (Brown−Out)
Over Power
Comparator
+
Over−Currents Compensation
LEB
Rcomp
9
Over Power
Limit
−
+
500 mV
Pin10 monitors the power switch current and compares it to the current set−point (one third of the feed−back voltage). The
current set−point is limited by the soft−start during the power−on sequence and permanently clamped to 0.9 V. A second pin
(pin9) monitors the current to clamp the power.
Figure 29.
http://onsemi.com
14
NCP1239
Figure 30 depicts the Vcc evolution during a proper startup sequence, showing the state of the error flag:
Vcc
VccON
VccOFF
Latch−off phase level
Logic reset level
FB
Full power
User
Powers up!
Feedback loops
reacts...
regulation
Skip level
Ip max
Error
Flag
Timer
7.5ms
SS
No error has
been confirmed
An error flag gets asserted after the soft−start period and as soon as the current set−point is maximum
Figure 30.
http://onsemi.com
15
NCP1239
PFC Start−up Sequence
To ensure an adequate start−up sequence of both PWM
section and the PFC stage, some logic and timing need to be
included as shown on the internal diagram. The key point
here is the fact that the PFC always starts after the PWM
section. As a result, the SMPS must be designed to cope with
transient universal mains operation. Why this? Because of
the light−to−heavy load transition where a case exists when
the PFC is off, the PWM in standby and the load is suddenly
applied. In this scenario, the PWM section must sustain the
entire transient period that lasts until the PFC re−starts since
it has been de−activated for standby.
The stand−by detection block generates an internal signal
“pfcON” that controls pin1 in accordance to the operation
mode:
− “pfcON” is high in normal mode and a current source
draws 1mA from pin1,
− “pfcON” is low in stand−by to disable the 1 mA current
source. A 10 kΩ resistor pulls up pin1 to Vcc.
This configuration makes it ideal to drive a pnp transistor
that connects or disconnects the NCP1239 Vcc to the PFC
controller one (refer to Figure 32). The “pfcON” signal is
activated following Figure 31 diagram. Let’s split this
drawing in different time periods to clearly depict signal
assertions:
Power on: during this time, Vcc rises up, the Vcc
capacitor being charged by the 5.2 mA current source. When
Vcc exceeds VccON (16.4 V typ.), driving pulses are
delivered to the MOSFET in an attempt to crank the power
supply. Vcc collapses (because the Vcc capacitor alone
delivers the energy) until sufficient auxiliary voltage is built
up in order to take over the start−up sequence and thus
self−supply the controller. As long as the output voltage has
not reached its wished value, the controller pushes for the
maximum peak current. During the soft−start (7.5 ms with
390 nF on pin6), the maximum permissible current linearly
increases till the maximum peak set−point is reached, the
internal 0.9 V zener diode actively clamping the current
amplitude to (0.9 V/Rsense). During this time, the NCP1239
asserts an error flag. A maximum current condition being
observed, the circuit determines if this state results from
either a normal response (start−up or a transient period) or
a fault condition. To make the difference, each time the error
flag is asserted, a 100 ms timer starts to count down. If the
error flag keeps asserted for the 100 ms period, there is a
fault and the PWM controller enters a safe, auto−recovery,
burst mode to limit the dissipated heat (see below for more
details). During the Power−on sequence, “pfcON” keeps
low to pull−up pin1 to Vcc until the error flag is down. When
the error flag is down, the power supply has entered
regulation, its auxiliary voltage is stable, then pin1 can turn
low (1 mA sink current) to safely allow PFC operation.
Entering Standby: when skip cycle starts to activate, a
100 ms countdown takes place and the logic observes the
skip activity. If the skip activity is still there at the end of the
100 ms, then stand−by is confirmed and the NCP1239 pulls
up pin1 to Vcc to shut down the PFC.
Leaving standby: in this case, as soon as the skip cycle
activity disappears, the circuit immediately re−activates the
1 mA sinking current source of pin1, to enable the PFC: there
is no reaction delay in this situation.
Short−circuit condition: a short circuit is detected on the
primary side by measuring the time the error flag is asserted.
As explained, if this flag is asserted longer than 100 ms, then
the PWM stops oscillating and enters a safe burst mode. In
this case, pin1 is pulled up to Vcc and the PFC is shut down.
During the burst, it is not activated (PFC is off) until the fault
goes away and the power supply resumes operation. The
PFC being shut off in short−circuit conditions, it naturally
reduces the main MOSFET stress.
Latch−off mode: if the controller is permanently
latched−off due to a major fault (pin3 detection of an OVP
or an excessive external temperature), the PFC is kept off
(pin1 being tied to Vcc).
http://onsemi.com
16
NCP1239
Vcc
PWM
regulation
Short−circuit
Short−circuit
Stby stby is left
16.4V
Nom
Pout
11.2V
6.9V
Timer
100ms
100ms
100ms
100ms
One Vcc cycle is skipped to
lower the burst mode duty
cycle to typically 5% in
fault conditions.
0.9V
flag
7.5ms
SS
PFC
Vcc
If the fault had disappeared
the SMPS would recover
normal operation
Stand−by
is confirmed
Connection of both controllers and PFC stage require a proper startup sequence
Figure 31.
http://onsemi.com
17
NCP1239
away as it is fully supplied by the PWM auxiliary winding
and even high quiescent current devices do not hamper the
standby power since they are completely disconnected in
standby.
The PFC controller connection is really straightforward as
testified by Figure 32: simply connect to pin1, the base of a
pnp transistor that connects the PFC’s Vcc to the NCP1239
one (perhaps add a small decoupling capacitor like a 0.1 F
on the PFC) and this is all! The PFC startup network goes
PFC stage
Rectified
ac line
Q1
PFC_VCC
1
8
2
7
3
6
4
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
5
+
PFC Controller
+
NCP1239
The NCP1239 turns off the pnp Q1 during the stand−by so that the PFC controller is no longer supplied in this mode.
Figure 32.
Short−Circuit or Overload Condition
The NCP1239 differs from other controllers in the sense
that a fault condition is detected independently of the
auxiliary voltage level. In auxiliary supply−based power
supplies, it is necessary that the (isolated) secondary output
conditions properly reflects on the (non−isolated) auxiliary
winding in order to instruct the controller on what is
happening on the other side of the transformer. For the
following reasons, it sometimes becomes extremely
difficult to build an efficient short−circuit protection
circuitry and even more difficult to implement over power
detection (e.g. the output load is 25% above the nominal
value but Vout is still present):
The primary leakage inductance is high: this is probably
the main reason why building efficient short−circuit
detection is difficult. When the power switch opens, the
leakage inductance superimposes a large over−voltage spike
on the drain voltage. This spike is seen on the secondary side
but also on the auxiliary winding. Unfortunately, since the
Vcc capacitor and the auxiliary diode form a peak rectifier,
the auxiliary Vcc often depends on this peak value rather
than the true plateau which corresponds to the output level:
http://onsemi.com
18
NCP1239
Leakage effect:
Vpeak = 24.2V
25.0
”clean” plateau
V = 13.4V
15.0
0V
5.00
−
5.00
−
15.0
236U
240U
244U
248U
252U
The leakage effect seen on the auxiliary side pulls−up the final level peak−rectified by the diode
Figure 33.
level before the 100 ms period has elapsed, nothing happens
and the controller continues working normally.
When a fault is detected, we have seen that the controller
stops delivering pulses. At this time, Vcc starts to drop
because the power supply is locked off. When the Vcc drops
below VccOFF (11.2 V typical), it enters a so−called
latch−off phase where the internal consumption is reduced
down to about 400 µA. The Vcc capacitor continues to
deplete, but at a lower rate. When Vcc finally reaches the
latch−off level (around 6.9 V), the start−up current source
turns on and pulls Vcc above VccON, exactly as a start−up
sequence would do. When Vcc exceeds VccON (16.4 V),
pulses are delivered and can last 100 ms maximum if there
is enough voltage or can be prematurely interrupted if Vcc
falls below VccOFF. Figure 34 shows the difference
between these two cases. As already explained, in
short−circuit bursts, the PFC section is not validated.
The short−circuit protection features a so−called
auto−recovery circuitry. That is to say, during the 100 ms
period, the power supply attempts to start−up. If the fault has
gone, then the controller resumes from the fault and the
power supply operates again. If the fault is still present, the
pulses are stopped at the end of the 100 ms section (Tpulse)
for a given time period Tfault. At the end of Tfault, a new
100 ms attempt is made and so on. To avoid any thermal
runaway, a burst duty−cycle defined by Tpulse/(Tfault+
Tpulse) below 10% is desirable ((Tfault+Tpulse) is the burst
period). If the 100 ms is made by an internal timer in
conjunction with the pin6 capacitor, the Tfault duration
builds on the Vcc capacitor which is charged / discharged
two times. Figure 35 portrays this behavior:
On Figure 33’s example, one can clearly observe the
difference between the peak and the real plateau DC level.
The delta is around 10 V, which obviously degrades the
auxiliary image of the secondary side. When a short−circuit
occurs, the leakage can be so strong that the whole plateau
has dropped to a few volts, but the leakage contribution
becomes so energetic (Ip = Ip max.) that even a few µs
duration is enough to prevent Vcc auxiliary from collapsing
and thus stopping the pulses. Needless to say that
over−power detection is simply impossible.
Low standby power requirement decreases Vcc at
no−load: this is particularly true if you try to reach less than
100 mW at high line. Thanks to skip cycle, the continuous
flow of pulses turns into bunches of pulses (sometimes 1−2
pulses only) that can be spaced by 50ms or more in certain
cases. The energy content in each bunch of pulses does not
suffer any attenuation. For instance, to lower Figure 33’s
peak, you could think of inserting a resistor with the
auxiliary diode to form a low pass filter with the Vcc
capacitor. Unfortunately, it would drastically reduce the Vcc
capacitor refueling current and Vcc could not be maintained.
To compensate that effect, a solution could be to increase the
turn ratio, but then the peak rectification problem comes
back again.
As one can see, a short−circuit protection free of the Vcc
level would be the best solution. This is exactly what the
NCP1239 brings you with an internal 100 ms timer. As soon
as the internal 0.9 V error flag is asserted high, a 100 ms
timer gets started. If the error flag keeps asserted during the
100 ms period, then the controller detects a true fault
condition and stops pulsing the output. If this is a simple
transient overload, e.g. the error flag goes back to a normal
http://onsemi.com
19
NCP1239
Cpin6=390 nF
Vcc
VccON
VccOFF
Drv
100ms
< 100ms
Bunch length given by timer
Bunch length given by VccOFF
When Vcc drops faster than the timer, it prematurely interrupts the pulses flow.
The 100 ms delay could be shortened or lengthened by changing the pin6 capacitor.
Figure 34.
Cpin6=390 nF
Vcc
VccON
t3
t1
VccOFF
t’1
t2
Latch−off phase level
t’2
Logic reset level
Drv
100ms
100ms
The burst period is ensured by the Vcc capacitor charge / discharge cycle
The 100 ms delay could be shortened or lengthened by changing the pin6 capacitor.
Figure 35.
http://onsemi.com
20
NCP1239
If by design we have selected a 47 F Vcc capacitor, it
becomes easy to evaluate the burst period and its duty−cycle.
This can be done by properly identifying all time events on
figure 35 and applying the classical formula: t = C * V / i.
To simplify, let’s consider t1 starts while Vcc=VccOFF.
Then:
• t1: I = ICC3 = 400 A, ∆V= 11.2 – 6.9 = 3 V t1 = 505ms
• t2: I = 5.2 mA, ∆V= 16.4 – 6.9 = 9.5 V t2 = 86 ms
• t3: I = 400 A, ∆V= 16.4 – 11.2 = 5.2 V t3 = 611 ms
• t’1=t1=505 ms
• t’2=t2=86 ms
The total period duration is thus the sum of all these events
which leads to Tfault = 1793 ms. If Tpulse = 100 ms, then
our burst duty−cycle equals 100/(1793+100) ≈ 5%, which is
excellent.
In fact, the calculation assumption, t1 starts while
Vcc=VccOFF, gives the worse case since the duty cycle is
calculated in the case where Tpulse exactly equals the active
phase duration (switching period when Vcc decreases from
VccON to VccOFF). In fact, Tpulse is generally:
−
−
shorter than the switching phase period. In this case, t1
is longer since the latched off phase starts earlier (at a
Vcc higher than VccOFF). As a consequence, the final
duty cycle is lower than previously estimated,
longer than the switching phase period. In this case, the
circuit detects an over−load condition simply because
Vcc drops below VccOFF (11.2 V) before the fault
timer has elapsed. Tpulse is lower than 100 ms and as a
result the duty cycle is also lower.
(Major) Fault Detection and Latched Off Mode
The NCP1239 features a fast comparator that
permanently monitors the “Fault Detect” pin level. If for any
reason this level exceeds 2.4 V (typical), the part
immediately stops oscillating and stays latched off until the
user cycles down the power supply. This enables the SMPS
designer to externally shut down the part in particular when
a major default occurs, e.g. an Over Voltage Protection
(OVP). Figure 36 shows what happens when the part is
latched:
Vcc
VccON
VccOFF
Latch−off phase level
Logic reset level
The user has unplugged, reset!
Drv
pin3
Stop!
2.4 V
When Vpin3 exceeds 2.4 V, NCP1239 permanently latches−off the output pulsesuntil its Vcc goes below 4 V. The figure can
illustrate a case where a thermistor supplied by REF5V is connected to pin3 to detect excessive temperatures of the application
(refer to application schematic).
Figure 36.
http://onsemi.com
21
NCP1239
application must not exceed. Choosing R equal to 5k, the
pin3 voltage at 130°C that equates:
Pin3 can serve to build an Over Voltage Protection by
placing a zener between the voltage to measure (e.g., Vcc)
and pin3 (refer to application schematic). If a 15 V zener is
applied, the pin3 comparator will switch when (Vcc−15 V)
exceeds the 2.4 V internal reference, that is, when Vcc is
higher than 17.5 V.
This pin can also monitor the temperature using an
external thermistor (refer to application schematic).
Thermistors can be of NTC type (Negative Temperature
Coefficient – the resistance decreases versus the
temperature) or of PTC type (Positive Temperature
Coefficient – the resistance increases versus the
temperature). Let’s assume that a NTC thermistor is used (as
in the application schematic). Placing it between the 5 V
reference voltage (REF5V) and pin3, and a classical
resistance between pin3 and ground, the pin3 voltage equals:
Vpin3 =
Vpin3(130C ) =
5k
* 5V = 2.5V
5k + 5k
triggers the fault comparator.
This example illustrates that one must just select the
bottom resistor so that it exhibits the same resistance as the
thermistor at the temperature to be detected.
If the thermistor is a PTC, it must be placed between pin3
and ground. One must place a resistor between the 5 V
reference voltage and pin3. Similarly, the resistor must be
selected so that its resistance equals the thermistor one at the
temperature to be detected.
Brown−Out and Over Power Limitation
SMPS are designed for a given input range. When the
input voltage is too low (brown−out), the SMPS tends to
compensate by sinking an increased current from the line.
As a result the power components may suffer from an
excessive heating and ultimately the SMPS may be
destroyed. To avoid such a risk, the NCP1239 incorporates
a brown−out detection that monitors the portion of the input
voltage that is applied to pin5.
R
* 5V
R + Rthermistor
, where R and Rthermistor are
respectively the resistor and the thermistor resistance.
Rthermistor decreasing versus the temperature, the pin3
voltage (Vpin3) increases when the temperature grows up.
For instance, the thermistor resistance can be in the range
of 500 kΩ at 25°C and as low as 5 kΩ at 130°C that as an
example, one can take as the temperature limit the
HV
CMP
Rupper
CMP
5
Driver
+
−
Driver is off
as long as
CMP is low
Rlower
+ 500 mV if CMP is low
240 mV if CMP is high
Vpin5
240 mV
500 mV
An hysteresis comparator monitors the SMPS input voltage
Figure 37.
comparator toggles, the internal reference voltage changes
from 500 mV to 240 mV. This effect is not latched: that is to
say, when the bulk capacitor is below the target, the
controller does not deliver pulses. As soon as the input
voltage grows−up and reaches the level imposed by the
resistive divider, pulses are passed to the internal driver and
activate the MOSFET. Figure 38 offers a way to connect the
elements around pin5 to create a Brown−Out detection:
Also called “Bulk OK” signal (BOK), the Brown−Out
(BO) protection prevents the power supply from being
adversely destroyed in case the mains drops to a very low
value. When it detects such a situation, the NCP1239 no
longer pulses but waits until the bulk voltage goes back to its
normal level. A certain amount of hysteresis needs to be
provided since the bulk capacitor is affected by some ripple,
especially at low input levels. For that reason, when the BO
http://onsemi.com
22
NCP1239
to converter
PFC
Preconverter
Rupper
ac line
Input
Filtering
Capacitor
Cbulk
+
5
Rlower
Cfil
Example where the voltage of the bulk capacitor is used for the brown−out Protection
Figure 38.
amount of power, actually the power of your converter (35W
in our example). The equation associated to Bload instructs
the simulator not to draw current until the Brown−Out
converter gives the order, just like what the real converter
will do. As a result, Vbulk is free of ripple until the node
CMP goes high, giving the green light to switch pulses. The
input line is modulated by the “timing” node which ramps
up and down to simulate a slow startup / turn−off sequence.
Then, by adjusting the Cfil value, it becomes possible to
select the right turn−off AC voltage. Figure 40 portrays the
typical signal you can expect from the simulator. We
measured a turn−on voltage of 85VAC whereas the turn−off
voltage is 72VAC. Further increasing Cfil lowers this level
(for instance, a 1 uF capacitor gives VBO=65VAC in the
example).
As we have seen, the load variations will modify this
turn−off level. To remove the dependency between VBO
and the load, it is possible to directly sense the rectified input
line present at the PFC stage input, as figure 41 offers. In that
case, there still exists the input line ripple, but this ripple is
independent of the load. By adjusting Cfil capacitance and
the divider section, you can build a brown−out detection
independent of the load.
The calculation procedure for Rupper and Rlower is easy.
The first level transition is always clean: the SMPS is not
working during the start−up sequence and there exists no
ripple superimposed on Cbulk. Supposed we want to start
the operation at Vbulk = Vtrip = 120 VDC (i.e., VinAC =
85V).
1. Fix a bridge current Ib compatible with your
standby requirements, for instance an Ib of 50µA.
2. Then evaluate Rlower by: Rlower = 0.5 / Ib =
10kΩ
3. Calculate Rupper by: (Vtrip – 0.5V) / Ib =
(120 – 0.5) / 50µA = 2.39MΩ
The second threshold, the level at which the power supply
stops (VBO), depends on the capacitor Cfil but also on the
selected bulk capacitor. Furthermore, when the load varies,
the ripple also does and increases as Vin drops. If Cfil allows
a too high ripple, chances exist to prematurely stop the
converter. By increasing Cfil, you have the ability to select
the amount of hysteresis you want to apply. The less ripple
appears on pin5, the larger the gap between Vtrip and VBO
(the maximum being VBO = Vtrip/2). The best way to assess
the right value of Cfil, is to use a simple simulation sketch
as the one depicted by figure 39. A behavioral source loads
the rectified DC line and adjusts itself to draw a given
http://onsemi.com
23
NCP1239
bulk
+
VBulk
Vline
∆
2
B1
Voltage
V(line)*V(timing)
Cbulk
47uF
IC = 40
IN
Bload
Current
V(CMP) >3 ? 35/V(bulk) : 0
−
3
PSpice:
EBload Value = { IF ( V(CMP)>3, 35/V(bulk), 0) }
bulk
timing
line
Rupper
2.4Meg
V1
cmp
+
V2
BrownOut
5
Cfil
220n
Rlower
10k
−
Bbrown
Voltage
V(CMP) > 3 ? 250m : 500m
PSpice:
EBbrown Value = { IF ( V(CMP)>3, 250m, 0) }
V2 timing 0 PWL 0 0.2 3s 1 7s 1 10s 0.2
V1 line 0 SIN 0 150 50
A simple simulation configuration helps to tailor the right value for Cfil
Figure 39.
200
16.0
100
12.0
0
8.0
−100
4.0
−200
0
Turn−off voltage occurs at:
VinRMS = 72.3 volts
Vbrown−out
8.156
8.175
8.195
8.215
Typical signals obtained from the simulator
Figure 40.
http://onsemi.com
24
8.235
NCP1239
Rectified ac line sensing
to converter
PFC
Preconverter
ac line
Rupper
Input
filtering
Capacitor
+
5
Cbulk
Rlower
Cfil
A second option to directly sense the mains
Figure 41.
In addition, it is not recommended to provide the output
with more power than normally necessary. To the light of
these statements, it becomes interesting to accurately limit
the amount of power drawn from the AC line in fault
conditions. The easiest way to do so consists of clamping the
peak current since in a discontinuous mode flyback
converter, the input power (Pin) can be calculated as
follows: Pin = 1/2 * Lp * Ippk2 * fsw, where Lp is the primary
inductor, Ippk is the inductor peak current and fsw is the
switching frequency.
Practically, a sense resistor converts the primary current
into a voltage that is compared to a voltage reference. When
the voltage representative of the current exceeds the voltage
reference, the controller turns off the power switch. The
theoretical maximum peak current is then: Imax = Vocp /
Rsense, where Vocp is the reference voltage (or over current
protection threshold) and Rsense is the sense resistor.
Unfortunately, the controller cannot turn off the power
switch immediately when it detects that the current exceeds
its maximum permissible level. Internal propagation delays
differ the drive turn low. In addition, the power switch needs
some time to turn off. Finally, the real current stop can be
250ns or more delayed. During this time, the current
continues ramping up so that an over−current is obtained.
This second option that directly senses the input voltage
(see figure 41), enables a more direct under−mains
detection. Even in a brown−out conditions, the PFC
pre−converter may be able to maintain a sufficient bulk
voltage, possibly at the price of some excessive stress.
Measuring the rectified ac line instead of the bulk voltage,
the NCP1239 more surely protects the PFC stage in
brown−out conditions.
Using:
− Rlower = 10 kΩ,
− Rupper = 2. 39 MΩ,
− Cfil = 1 F,
One obtains the following voltage thresholds:
− Vtrip = 85 Vrms,
− VBO = 65 Vrms.
Over−Power Limit
Overload conditions may push the converter to draw an
excessive power (which generally increases versus the input
voltage). One must avoid such a behavior:
a) not to have to dimension the converter for a power
higher than the nominal one,
b) to meet SMPS specifications that often request the
power not to exceed a given level.
http://onsemi.com
25
NCP1239
Actual Peak Current
Low Input
Voltage
δIHL
δILL
Vopl/Rsense
Wished Maximum
Peak Current
High Input
Voltage
δt
δt
The propagation delay (t) produces over−currents (ILL at low line, IHL at high line in the figure) that are proportional to the input
voltage. As a consequence, the actual maximum current and then the power limit gets higher when the ac line increases.
Figure 42.
Imax =
Vocp
Vin * δt
+
Rsense
Lp
Then,
Ipth =
, where Vin is the converter
input voltage and δt is the total delay in turning off the power
switch.
The NCP1239 enables the compensation of the second
term in the Imax equation for a precise limitation of the peak
current. A current source (Ipin9) proportional to the pin5
voltage flows out of pin9. Since pin5 receives a voltage
proportional to the input voltage for brown−out detection,
Ipin9 is proportional to the input voltage too. An external
resistor Rcomp can be connected between pin9 and the
positive terminal of Rsense, so that pin9 monitors the
following voltage:
Vpin9 = [Rsense * (Ip + Ipin9)] + (Rcomp * Ipin9)
Ipin9 being small compared to the inductor current, the pin9
voltage simplifies as follows:
Vpin9 = (Rsense * Ip) + (Rcomp * Ipin9)
Ipin9 is proportional to the pin5 voltage (80 µA/V*Vpin5 –
see parameters specification table) and Vpin5 is a portion of
the input voltage (Vpin5=kBO*Vin). Finally,
Ipin9 = 80 A/V * kBO * Vin
The voltage Vpin9 is compared to the internal reference
Vocp. When Vpin9 reaches Vocp, the corresponding
threshold current (Ipth) is deducted from:
Vopl = (Rsense * Ipth) + (Rcomp * 80 A/V * kBO * Vin)
Vopl − Rcomp * 80 A/V * k BO * Vin Rsense
Taking into account the over−current resulting from the
propagation delays, the maximum current is finally:
Rcomp * 80A/V * k BO * Vin Vin * δt
Vocp
−
+
Imax =
Rsense
Rsense
Lp
Rcomp * 80 A/V * k BO δt
=
Rsense
Lp
Choosing Rcomp so that
,
the current limit is made constant in the whole input voltage
range (Imax = Vocp / Rsense).
As an example, let’s assume that:
− the minimum input voltage for operation is 100 V =>
kBO=0.5/100=0.005,
− Rsense is 0.25 Ω,
− Lp=500 µH,
− The total propagation delays are δt=350 ns,
Then, the Rcomp resistor should be:
Rcomp =
http://onsemi.com
26
δt * Rsense
350n * 0.25
=
≈ 438Ω
80 * k BO * Lp 80 * 0.005 * 500 m
NCP1239
Vdd
CLK
Rbo1
Vin
PWM Latch
Vpin5
80A/V*Vpin5
S
5
Q
Rbo2
Brown−Out
Q
Cbo
to Brown−Out
Comparator
R
Vcomp = k*Rcomp*Vpin5
Rcomp
+
LEB
9
Over Power
Limit
−
+
Vcomp
Rsense
0.5V
to
Current Sense
Comparator
Rramp
10
Current Sense
An (averaged) portion of the input voltage is applied to the brown−out pin. A current source proportional to this voltage, flows through an
external resistor Rcomp to form an offset proportional to the (average) input voltage. Rcomp should be selected so that the offset compensates the over−current sensed by the current sensing resistor Rsense.
Figure 43.
Soft−Start
The NCP1239 features an internal soft−start activated
during the power on sequence (PON). As soon as Vcc
reaches 16.4 V, the current set−point is gradually increased
from nearly zero up to the maximum clamping level (e.g.
0.9V/Rsense). This situation lasts a programmable time that
is adjusted by the pin6 capacitor (7.5 ms typically with
Cpin6=390 nF). Further to that time period, the current
set−point is blocked to 0.9V/Rsense until the supply enters
regulation. The soft−start is also activated at each start of the
active phase of fault burst operation. Every re−start attempt
is followed by a soft−start activation.
16.4V
6.9V
Soft−start is activated during a start−up sequence or an OVL condition
Figure 44.
http://onsemi.com
27
NCP1239
Generally speaking, the soft−start will be activated when
Vcc ramps up either from zero (fresh power−on sequence)
or 6.9 V, the latch−off threshold after an over−load detection
(OVL) for instance. Figure 44 portrays the soft−start
behavior which a 390 nF soft−start capacitor on pin6. The
time scales are purposely shifted to offer a better zoom
portion.
In the NCP1239, the ramp features a swing of 3.2 V.
Suppose we select a 65 kHz version. Over a 65 kHz
frequency, it corresponds to a 130 mV/ms ramp. In our
FLYBACK design, let’s assume that our primary inductance
Lp is 350 mH, and the SMPS delivers 12 V with a Np:Ns
ratio of 1:0.1. The OFF time slope of the primary current is:
Vout + Vf ⋅ Ns
Np
Lp
that is, 371 mA/ms or 37 mV/ms, once
Internal Ramp Compensation
Ramp compensation is a known mean to cure
sub−harmonic oscillations. These oscillations take place at
half the switching frequency and occur only during
Continuous Conduction Mode (CCM) with a duty−cycle
greater than 50%. To lower the current loop gain, one usually
injects between 50 and 100% of the inductor down−slope.
Figure 45 depicts how internally the ramp is generated:
projected over a 0.1 Rsense for instance. If we select 75%
of the down−slope as the required amount of ramp
compensation, then we shall inject 27 mV/ms. Our internal
compensation being of 208 mV/ms, the divider ratio
(divratio) between Rramp and the 32 k is 0.178. A few lines
of algebra to determine Rramp:
19k ⋅ divratio
Rramp =
1 − divratio = 6.92k.
3.2V
The ramp is disabled during stand−by (i.e., when pfcON
is low). This inhibition avoids that the ramp compensation
modifies the set−point above which the NCP1239 enables
PFC.
0V
32k
Rramp
Frequency Jittering
Frequency jittering is a method used to soften the EMI
signature by spreading the energy in the vicinity of the main
switching component. NCP1239 offers a +3.5% deviation of
the nominal switching frequency. The sweep saw−tooth is
internally generated and modulates the clock up and down
with a period depending on the pin6 capacitor (10 ms
typically with 390 nF). Again, if one selects a 65 kHz
version, the frequency will equal 65 kHz in the middle of the
ripple and will increase as Vpin6 rises or decrease as Vpin6
ramps down. Figure 46 portrays the behavior we have
adopted:
LEB
CS
+
−
Rsense
from
setpoint
Inserting a resistor in series with the current sense
information brings ramp compensation
Figure 45.
Internal
ramp
67.6kHz
65kHz
Internal
sawtooth
62.4kHz
10ms
The Vpin6 ramp is used to introduce frequency jittering on the oscillator saw−tooth
Figure 46.
http://onsemi.com
28
NCP1239
Skipping Cycle Mode
The NCP1239 automatically skips switching cycles when
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, pin8 imposes a current set−point accordingly to
the load value. If the load demand decreases, the internal
loop asks for less peak current. When this set−point reaches
a fixed determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so−called skip cycle mode, also
named controlled burst operation. The default skip cycle
current is internally frozen to 30% of the maximum peak
current which is 0.5V/Rsense The power transfer now
depends upon the width of the pulse bunches (figure 47).
Suppose we have the following component values:
Lp, primary inductance = 350 mH
Fsw , switching frequency = 65 kHz
Ip skip = 600 mA (or 150 mV / Rsense)
The theoretical power transfer is therefore:
1/2 * Lp * Ip2 * Fsw = 4 W
If this IC enters skip cycle mode with a bunch length of
10ms over a recurrent period of 100ms, then the total power
transfer is:
4 W * 10 ms / 100 ms = 400 mW
To better understand how this skip cycle mode takes place,
a look at the operation mode versus the FB level
immediately gives the necessary insight:
FB pin Voltage
5V, FB pin open
2.7V upper dynamic range
Normal current mode operation
0.45V
Skip cycle operation
Ip MIN = 150mV / Rsense
Figure 47.
When FB is below the skip cycle threshold (0.45 V by
default), the circuit skips the switching cycle. When the IC
enters the skip cycle mode, the peak current cannot go below
(0.45 V/3)/Rsense or 150 mV/Rsense. Figure 48 shows
different values of pulse widths when the SMPS starts to
skip cycles at different power levels:
Power P1
Power P2
Power P3
Output pulses at various power levels (X = 5s/div) P1 < P2 < P3
Figure 48.
http://onsemi.com
29
NCP1239
300.0M
Max peak
current
200.0M
25% of max Ip
100.0M
0
315.4U
882.7U
1.450M
2.017M
2.585M
The skip cycle takes place at low peak currents which guaranties noise free operation
Figure 49.
PFC Inhibition in Stand−by
The circuit detects a light load condition by permanently
monitoring the skip cycle comparator activity: in normal
load condition this comparator keeps quiet. As soon as the
load strongly decreases, this comparator starts to toggle at a
low frequency rate: we are entering skip cycle and the
opto−coupler operates in a digital manner, ON/OFF. Figure
49 shows the way skip cycle is detected. In skip mode, the
feed−back voltage oscillates around Vpin7 (If no voltage is
applied to the pin7, a 430 mV voltage source supplies a
default value through a high impedance resistor). In these
conditions, the skip comparator (“COMP1”) that turns on
and off (to adjust the skip mode bunches of pulses), sets the
stand−by detection latch. A second comparator (“COMP2”)
compares the feed−back voltage (FB or Vpin8) to
1.7*Vpin7.
As long as the load keeps light, FB does not exceed
1.7*Vpin7 (i.e., 0.74 V typical if no voltage is forced to
pin7). A timer counts down and if COMP2 keeps high for
100 ms (typically with 390 nF on pin6), the NCP1239
considers that the system runs in the stand−by mode. Pin1
turns high, a 10kΩ resistor tying the pin to Vcc. If as shown
in figure 32, pin1 directly drives a pnp transistor that is
connected between Vcc and the PFC Vcc, this switch turns
off in stand−by. As a result, this transistor stops feeding the
PFC Vcc and ultimately shuts the PFC down.
As soon as FB exceeds 1.7*Vpin7, the circuit leaves the
stand−by mode without any delay by forcing a 1mA sinking
current source on pin1, that re−activates the pnp transistor
and then the PFC stage.
One can note that there is a 1/3 ratio between the actual
current set−point and the feed−back value FB. Therefore the
default thresholds for stand−by detection and normal mode
recovery (0.43 V, 0.74 V) actually corresponds to the 140
mV and 250 mV set−points.
70%
A delay is inserted to avoid false tripping of the GTS signal
Figure 50.
http://onsemi.com
30
NCP1239
One clearly sees that the GTS signal does not react to the fugitive low FB pin condition during startup
Figure 51.
FB < Vpin7 => Skip high
REF5V
Skip
+
R1
Skip
Adjust
100k
−
FB
COMP1
7
+
0.43V
R2
Stby_detect
S
Q
15r
Q
25r
COMP2
+
R
−
FB > 1.7*Vpin7 => Stby_detect RESET
GTS
100 ms timer (*)
(SS and timer block)
pin1
(*) the 100 ms delay is programmed by the pin6 capacitor
Internal Go−To−Standby signal elaboration
Figure 52.
Suppose our Flyback controller is built with a transformer
primary inductance of 250 µH. To pass 120 W, we assume
that a peak current of 4.2 A was needed. Thanks to these
numbers, we can easily now when the GTS signal will be
asserted:
Lp, primary inductance = 250 H
= 85%
Fsw , switching frequency = 65 kHz
Ip =
2⋅Pout
η⋅Lp⋅Fsw
Ip skip = 30% of Ip max = 1.26 A
The theoretical region at which the SMPS will enter
standby is: 1/2 * Lp * Ip * Fsw * 11 W. This number
can vary depending on the line level since the propagation
delay becomes a sensitive parameter, and on the efficiency
that is difficult to precisely predict in light load conditions.
The peak current at which the SMPS will leave standby is
48% of the peak current which means that a power of 28 W
is necessary to re−trigger the PFC.
= 4.2 A
http://onsemi.com
31
NCP1239
INFORMATIVE WAVEFORMS
The following plots were obtained using a 150 W application (output 19 V/7 A).
The NCP1239 enables the PFC Vcc as soon as the FB pin voltage has gone below a threshold
(about 2.7 V), that is when the internal error flag stops being asserted.
Figure 53. Start−up Sequence
http://onsemi.com
32
NCP1239
The feed−back voltage goes high and asserts the internal error flag. The pin6 timer counts for about 100 ms
(Cpin6=390ns) before shutting down the SMPS. One “Vcc cycle over two is skipped” to limit the duty cycle in overload.
Figure 54. Overload Conditions
http://onsemi.com
33
NCP1239
When the load current falls to a low level (CH4), the FB pin voltage diminishes to take into account the decay of the power
demand. As a consequence, the FB pin voltage goes below the “Vskip” threshold and the soft start timer counts about 100ms
(if Cpin6=330nF). When the 100ms time has elapsed, the PFC Vcc stops being fed.
Figure 55. Transition Normal to Stand−by
http://onsemi.com
34
NCP1239
When the load current increases from 1A to 5A, the FB pin increases too so that the supplied power
matches the new demand. The normal mode is recovered without delay.
Figure 56. Transition stand−by to normal
http://onsemi.com
35
NCP1239
PACKAGE DIMENSIONS
SO−16
FD SUFFIX
CASE 751B−05
ISSUE J
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.229
0.244
0.010
0.019
The product described herein (NCP1239), may be covered by one or more of the following U.S. patents: 6,362,067, 6,385,060, 6,429,709. There may be
other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
36
For additional information, please contact your
local Sales Representative.
NCP1239/D