ETC VT1712

PCI Multi-Channel Audio Controller
Revision 2.4
May 28, 2002
VIA Technologies, Inc.
Copyright Notice:
Copyright © 2002 VIA Technologies Incorporated. All Rights Reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means,
electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA
Technologies Incorporated. The material in this document is for information only and is subject to change without
notice. VIA Technologies Incorporated reserves the right to make changes in the product design without reservation
and without notice to its users.
Trademark Notices:
VT1712 and VT1724 may only be used to identify products of VIA Technologies.
Windows XP™. Windows 2000™. Windows ME™, Windows 98™, Windows 95™ and Plug and PlayTM are registered
trademarks of Microsoft Corp.
PCI™ is a registered trademark of the PCI Special Interest Group.
All trademarks are the properties of their respective owners.
Disclaimer Notice:
No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies
makes no warranties, implied or otherwise, in regard to this document and to the products described in this document.
The information provided by this document is believed to be accurate and reliable to the publication date of this document. However, VIA Technologies assumes no responsibility for any errors in this document. Furthermore, VIA Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent
infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change.
Offices:
USA Office:
Taipei Office:
940 Mission Court
Fremont, CA 94539
USA
Tel: (510) 683-3300
Fax: (510) 683-3301 or (510) 687-4654
Web: http://www.viatech.com
8th Floor, No. 533
Chung-Cheng Road, Hsin-Tien
Taipei, Taiwan ROC
Tel: (886-2) 2218-5452
Fax: (886-2) 2218-5453
Web: http://www.via.com.tw
Ordering Information:
VT1712 - 128PQFP
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Revision History
Document Release
Date
Revision
Initials
ICE1712 Data Sheet published by IC Ensemble, Inc.
1.1 (engg samples)
RD
Reflect all the changes, including architectural ones for the production part
Update Block Diag. in Fig. 4-1
Add VSR (ICE1232) support on Consumer AC-link path.
CCS09_1 and _0 controls for each direction.
Professional section I²S clocking scheme enhancement
MT01 and MT02 to support 64 and 88.2kHz. 256x and 128x MCLK global options.
Appendix, Table 7-2 to reflect above.
Add signal routing option of monitor to consumer section, via MT3C_0 bit (definition modified)
Cleanup typos: CCI06 and CCI08 content swap location.
2.0 (production)
2.1
Misc updates
RD
Remove Confidential notice
Update MT3B mixer volume update rate, patchbay, and digital mixer insertion delay descriptions
Fix typo on power-up default PCI06; Update Fig 4-3
RD
2.2
1/3/00
2.3
5/24/02 IC Ensemble, Inc. bought by VIA Technologies, product part number changed to VT1712 and
DH
document converted to VIA standard data sheet format
2.4
5/28/02 Cleaned up typograohical errors and fixed formatting issues
Revision 2.4, May 28, 2002
-i-
DH
Revision History
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Product Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 Product Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 Pin Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
PCI Interface and Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
PCI00: Vendor Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
PCI02: Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
PCI04: PCI Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
PCI06: PCI Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
PCI08: Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
PCI0A: Class Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
PCI0C: Cache Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
PCI0D: Latency Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
PCI0E: Header Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
PCI0F: BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
PCI10: Envy24 I/O Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
PCI14: DDMA I/O Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
PCI18: DMA Path Registers I/O Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
PCI1C: Multi-Track I/O Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
PCI2C: Sub-Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
PCI34: Capability Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
PCI34: Interrupt Pin and Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Revision 2.4, May 28, 2002
-ii-
Table of Contents
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
PCI3E: Latency and Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
PCI40: Legacy Audio Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
PCI42: Legacy Configuration Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
PCI60: System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
PCI61: AC-Link Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
PCI62: I2S Converters Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
PCI63: S/PDIF Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
PCI80: Capability ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
PCI81: Next Item Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
PCI82: Power Management Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
PCI84: Power Management Control / Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
PCI86: Power Management Control / Status (PMCSR) Base and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Hardware Interfaces & Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
CCS00: Control / Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
CCS01: Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
CCS02: Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
CCS03: Envy24 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
CCS04: Envy24 Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
CCS05: NMI Status 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
CCS06: NMI Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
CCS07: NMI Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
CCS08: Consumer AC’97 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
CCS09: Consumer AC’97 Command and Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
CCS0A: Consumer AC’97 Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
CCS0C: Primary MIDI UART Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
CCS0D: Primary MIDI UART Command / Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
CCS0E: NMI Status 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
CCS0F: Game Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
CCS10: I2C Port Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
CCS11: I2C Port Byte Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
CCS12: I2C Port Read / Write Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
CCS13: I2C Port Control and Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
CCS14: Consumer Record DMA Current / Base Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
CCS18: Consumer Record DMA Current / Base Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
CCS1B: PCI Configuration SERR# Shadow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
CCS1C: Secondary MIDI UART Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
CCS1D: Secondary MIDI UART Command / Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
CCS1E: Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.2 Controller Indexed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
CCI00:
CCI01:
CCI02:
CCI03:
CCI04:
CCI05:
Playback Terminal Count (High Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Playback Terminal Count (Low Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Playback Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Playback Left Volume / Pan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Playback Right Volume / Pan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Soft Volume / Mute Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Revision 2.4, May 28, 2002
-iii-
Table of Contents
Technologies, Inc.
We Connect
CCI06:
CCI07:
CCI08:
CCI10:
CCI11:
CCI12:
CCI20:
CCI21:
CCI22:
CCI30:
CCI31:
VT1712 - PCI Multi-Channel Audio Controller
Playback Sampling Rate (Low Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Playback Sampling Rate (Middle Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Playback Sampling Rate (High Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Record Current / Base Terminal Count (High Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Record Current / Base Terminal Count (Low Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Record Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
GPIO Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
GPIO Write Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
GPIO Direction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Consumer Section Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Multi-Track Section Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.3 DDMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.4 DMA Path Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
4.5 Consumer Section DMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
DS0: DirectSound DMA Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
DS2: DirectSound DMA Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
DS4: Channel Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
DS8: Channel Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Channel Control and Status at Index 4h (DS8 = x4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Consumer Mode Sampling Rate at Index 5h (DS8 = x5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Consumer Mode Left / Right Volume at Index 06h (DS8 = x6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
4.6 Professional Multi-Track Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
4.6.1
Multi-Track Mode Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
MT00:
MT01:
MT02:
MT04:
MT05:
MT06:
Professional Section DMA Interrupt Mask and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Professional Section Sampling Rate Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
Professional Section AC’97 Codec I²S Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Professional Section AC’97 Codec Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Professional Section AC’97 Codec Command / Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
Professional Section AC’97 Codec Data Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
4.6.2
Multi-Track Playback Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
MT10:
MT14:
MT16:
MT18:
Professional Section Playback DMA Current / Base Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Professional Section Playback DMA Current / Base Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Professional Section Playback Current / Base Terminal Count . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Professional Section Playback and Record Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
4.6.3
Multi-Track Record Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
MT20:
MT24:
MT26:
MT28:
Professional Section Record DMA Current / Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
Professional Section Record DMA Current / Base Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
Professional Section Record Current / Base Terminal Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
Professional Section Record Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
4.6.4
Professional Section Digital Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
MT30: Routing Control for Data to PSDOUT[0:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
MT32: Routing Control for SPDOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
MT34: Captured (Recorded) Data Routing Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
4.6.5
Multi-Track Digital Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
Revision 2.4, May 28, 2002
-iv-
Table of Contents
Technologies, Inc.
We Connect
MT38:
MT3A:
MT3B:
MT3C:
MT3E:
MT3F:
VT1712 - PCI Multi-Channel Audio Controller
Left / Right Volume Control Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
Volume Control Stream Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
Volume Control Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
Digital Mixer Monitor Routing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
Peak Meter Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42
Peak Meter Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.3 AC Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1 Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Revision 2.4, May 28, 2002
-v-
Table of Contents
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
List of Figures
Figure 2-1.
128-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 4-6.
Figure 4-7.
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
I²S Format Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Crystals to Master Clocks Clock Generation Tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
Master Clocks to Bit Clocks, L/R Clocks and Sync Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
Multi-Track DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Data Stream Routing Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
Digital Mixer Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 5-7.
Cold Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Warm Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xBCLK to xxSYNC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setup and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rise Time and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC-Link Power Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 2.4, May 28, 2002
-vi-
5-2
5-3
5-3
5-4
5-5
5-6
5-6
List of Figures
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
List of Tables
Table 2-1.
Table 2-2.
Table 2-3.
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Alphabetical Pin Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Numerical Pin Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Table 3-1.
PCI Host Interface Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Table 4-2.
Table 4-3.
Table 4-4.
Table 4-5.
Table 4-6.
Table 4-7.
CCSxx Controller Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
DMA Channels and Respective Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
DSx Consumer DMA Channel Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
DS8 Register, Low Nibble Index Description Applicable to Channel-0 through D . . . . . . . . . . . . . . 4-21
Channel Parameter Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
MTxx Controller Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Table 5-2.
Table 5-1.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 5-9.
Table 5-10.
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cold Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Mode Master clock delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xBCLK / xxSYNC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setup and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC-Link Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-1.
Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Table A-1.
Table A-2.
Table A-3.
Table A-4.
AC-Link Interface Parameters and Ratios (Pin 50 Floating / Pulled Up) . . . . . . . . . . . . . . . . . . . . . . .
I²S Interface Parameters and Ratios (Pin 50 Pulled Down) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/PDIF Output I²S Interface Parameters and Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/PDIF Input I²S Interface Parameters and Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 2.4, May 28, 2002
-vii-
5-1
5-1
5-2
5-2
5-3
5-3
5-4
5-5
5-5
5-6
A-1
A-1
A-2
A-2
List of Tables
Technologies, Inc.
We Connect
Revision 2.4, May 28, 2002
VT1712 - PCI Multi-Channel Audio Controller
-viii-
List of Tables
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
VT1712
Envy24™
PCI Multi-Channel Audio Controller
Product Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PCI 2.1 I/F with bus mastering and burst modes
24-bit resolution audio format support
Sampling rates up to 96kHz
8x2 I/O on AC-link or I²S, up to 4x2 converters
Simultaneous I²S for S/PDIF I/O up to 96kHz
20 channels, 36-bit wide digital mixer
Monitor and master copy functions
Peak meters on all 20 professional multi-track streams
Concurrent 16 streams DirectSoundTM accelerator
Sample Rate Converter for DirectSound applications
Two MPU-401 MIDI UART ports
ACPI and PCI PMI support
I²C subset I/F for E²PROM (configuration and ID storage) and peripherals control
HW SoundBlaster® Pro legacy
FM synthesis for DOS® legacy
64-voices SW Wavetable General MIDI Synthesizer for Windows95
DirectInputTM compatible Joystick port
8-bit GPIO port
Windows® 95/98, NT4.0 drivers
24.576, 16.9344 or 22.5792 MHz crystal operation
3.3V operating supply (5V tolerant I/O)
128-pin PQFP (14mm x 20mm body)
1.1 Product Applications
•
•
•
•
•
•
•
•
•
•
PC-based multi-track audio
Discrete multi-channel audio
High-end PCI audio
“Pro-sumer” audio
General purpose multi-channel I/O
Computer telephony
PC-based data acquisition
PC-based waveform generation
PC-based instrumentation
PC-based control and automation
Revision 2.4, May 28, 2002
1-1
Features and Overview
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Overview
The Envy24TM is a versatile PCI multi-channel I/O controller. It allows up to 12x2 simultaneous input and output
channels with the data source or destination being either analog or digital. Some of the typical applications for this part
are computer based multi-track audio, multi-channel audio, PC-based data acquisition, waveform generation and
computer telephony integration. The Envy24 can be combined with professional grade I²S converters, S/PDIF
transmitters/receivers or AC-link codecs, such as the VT1611ATM. The controller integrates a very high resolution
digital mixer allowing up to 20 channels of mixing. This is aimed specifically for monitoring final outputs, making
master copies and for budget conscious studios that may lack an individual out-board mixer.
The Envy24 supplies a master I²C interface providing connection to an E²PROM to store and retrieve PCI Subsystem
and Subsystem vendor IDs, specific board configurations and custom features identification. This interface is available
for controlling other devices as well.
For target markets where legacy audio is still important, the SoundBlaster Pro compatible hardware ensures hardware
compatibility under DOS for DDMA (Distributed DMA) and non-DDMA systems. The device also includes a
Microsoft Win9x architecture based DirectSound hardware accelerator that interfaces to AC’97 via AC-link. The
separate path allows concurrent operation with the 24-bit professional multi-track audio section.
The Envy24 is a “Digital-Ready” audio device allowing acceleration in cooperation with the host and redirecting audio
streams to other endpoints.
The Envy24 integrates two independent MPU-401 MIDI UARTs. This features allows hooking up multiple external
MIDI devices and dedicating the two paths for different purposes.
Additionally, a conventional standard Joystick port and timer is integrated. Only R and C components are necessary to
complete the circuit. Also an 8-bit GPIO brings flexibility for multi-purpose use.
The Envy24 is a power miser device due to its aggressive power management scheme and hard-wired design
architecture. The device is ACPI compliant making it suitable for platforms designed for “OnNow”.
Depending on the sampling rates that need to be supported by the target solution, one or two crystals are sufficient to
operate the whole system. Alternatively, a PLL Clock synthesizer chip can be used to generate the necessary
frequencies. The clock chip can be controlled by the GPIO pins for programmability.
For more detail on the part, please refer to the system block diagram Figure 4-1 in Section 4.
Revision 2.4, May 28, 2002
1-2
Features and Overview
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Pinouts
The following section includes the pinout diagram of the chip that is housed in a standard 128-PQFP. Also, three lists of
pin assignments are provided for your convenience. They are logically sorted by functionality and description,
alphabetically and numerically sorted in ascending order. These list are provided to assist hardware development, test,
debugging and quality assurance. The mechanical data about the part can be found in Section 6.
Revision 2.4, May 28, 2002
2-1
Pinouts
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
2.1 Pinout Diagram
JSD1
JSD0
PRST#
SPDOUT
SPDIN
GND
SPSYNC
SPSCLK
SPMCLKIN
SPMCLKOUT
INTA#
RST#
VCC
GND
PCICLK
GNT#
REQ#
AD31
AD30
VCC
AD29
AD28
AD27
AD26
AD25
GND
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VCC
AD24
CBE3#
IDSEL
AD23
AD22
GND
AD21
AD20
AD19
AD18
AD17
VCC
GND
AD16
CBE2#
FRAME#
IRDY#
TRDY#
GND
DEVSEL#
STOP#
SERR#
PAR
CBE1#
GND
VCC
AD15
AD14
AD13
AD12
AD11
GND
AD10
AD9
AD8
CBE0#
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
JSD2
JSD3
GND
JSD4
JSD5
JSD6
JSD7
TX1
RX1
VCC
CMCLK
CSDOUT
CBCLK
CSDIN
CSYNC
GND
CRST#
PMCLK
PSDOUT[3]
PSDOUT[2]
PSDOUT[1]
VCC
GND
PSDOUT[0]
PBCLK
PSDIN[3]
PSDIN[2]
PSDIN[1]
GND
PSDIN[0]
PSYNC
SCLK
SDA
TESTEN#
NC
VCC_X1
XOUT1
XIN1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
GND_X1
VCC_X2
XOUT2
XIN2
GND_X2
GPIO7/RX2
GPIO6/TX2
GPIO5
GPIO4
GND
VCC
GPIO3
GPIO2
GPIO1
GPIO0
AD0
AD1
AD2
GND
VCC
AD3
AD4
AD5
AD6
AD7
GND
Figure 2-1. 128-Pin PQFP Package
Revision 2.4, May 28, 2002
2-2
Pinouts
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
2.2 Pin Descriptions
The following table provides a brief description of each pin of the VT1712. Pins with dual usage may be listed twice for
consistency.
The following abbreviations are used to identify the pin types.
I - Input Signal
O - Output Signal
B - Bidirectional Signal
OD - Open Drain
A - Analog Signal
PU - Pull-up. 50 KΩ nominal
Table 2-1. Pin Descriptions
PCI Bus Interface
Symbol
Type
AD[31:0]
B
Multiplexed PCI Address / Data Bus.
B
Bus Command / Byte Lane Enable. These signals are bus commands during the address phase and byte
lane enable during the data phase. These signals are output during a bus master cycle.
I
PCI Bus Clock.
B
Device Select. The VT1712 drives this signal active when it decodes its address as the current target of the
current acces.
B
PCI Cycle Frame. When asserted by the bus mster, this signal indicates the beginning of a bus
transaction.During the final data phase of a bus transaction it is deasserted.
GNT#
I
PCI Bus Grant. When active it indicates bus master is granted to VT1712.
IDSEL
I
Initialization Device Select. This is the chip select during the PCI configuration register accesses
INTA#
OD
IRDY#
B
Initiator Ready.
PAR
B
Parity Signal.
REQ#
O
Bus Master Control Request
RST#
I
System Reset. All VT1712 registers and state machines are at default when this signal is asserted.
CBE#[3:0]
PCICLK
DEVSEL#
FRAME#
Description
PCI Interrupt Request.
SERR#
OD
PCI System Error.
STOP#
B
Target Disconnect.
TRDY#
B
Target Ready.
I²C Port
SDA
B
Serial Data.
SCLK
O
Serial Bit Shift Clock.
Game Port
JSD[7:4]
I
Joystick Fire Buttons.
JSD[3:0]
A
Joystick Coordinates Inputs.
Primary MPU-401 UART
TX1
O, PU
Primary MPU-401 Transmit Data.
RX1
I, PU
Primary MPU-401 Receive Data.
Revision 2.4, May 28, 2002
2-3
Pinouts
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Table 2-1. Pin Descriptions (continued)
Secondary MPU-401 UART
TX2 / GPIO6
O
Secondary MPU-401 Transmit Data.
RX2 / GPIO7
I
Secondary MPU-401 Receive Data.
CSYNC
O
48kHz fixed rate sync pulse
CBCLK
I
12.288MHz Serial Bit Clock
CSDIN
I
Incoming Serial Data Stream
CSDOUT
O
Outbound Serial Data Stream
CMCLK
O
Master Clock for AC’97 codec. Outputs XIN1 crystal frequency, typically 24.576 MHz .
CRST#
O
Consumer Codec master reset
Consumer AC-Link Interface
Professional Multi-Track AC-Link / I²S Interface
PSYNC
PBCLK
O
AC’97: 48kHz fixed rate sync pulse for up to 4 codecs, or
8 I²S type converters: Left/Right Clock
I/O
Serial Bit Clock. It can be master or slave configured
PSDIN[3:0]
I
4 separate incoming stereo stream pairs
PSDOUT[3:0]
O
4 separate outbound stereo stream pairs
PMCLK
O
Master Clock for AC’97 codecs or I²S converters
PRST#
O
Cold reset for Professional Multi-track I²S/AC-link I/F
Clocks
XOUT1
A
Clock Out 1.
XIN1
A
Clock In 1. 24.576 MHz (512*48 KHz). Runs all fixed clock blocks.
XOUT2
A
Clock Out 2.
XIN2
A
Clock In 2. 16.9344 MHz (384*44.1 KHz) or 22.5792 MHz (512*44.1 KHz) or external PLL output
S/PDIF (Sony / Philips Digital Interface)
SPMCLKIN
I
S/PDIF Master Clock Input.
SPMCLKOUT
O
S/PDIF Master Clock Output.
SPSCLK
O
S/PDIF Serial Bit Clock.
SPDIN
I
Incoming S/PDIF Serial Data.
SPDOUT
O
Outbound S/PDIF Serial Data.
SPSYNC
O
S/PDIF Frame Sync.
General Purpose I/O
Symbol
Type
Description
GPIO7 / RX2
B, PU
General Purpose I/O. Secondary MPU-401 Receive data
GPIO6 / TX2
B, PU
General Purpose I/O. Secondary MPU-401 Transmit data
GPIO5 / S1
B, PU
General Purpose I/O. Clock rate select for external clock chip select
GPIO4 / S0
B, PU
General Purpose I/O. Clock rate select for external clock chip select
B, PU
General Purpose I/O. E²PROM presence indicator during power-up (default). The state is reflected on
CCS13[7] bit.
GPIO3 / E²PROM
Revision 2.4, May 28, 2002
2-4
Pinouts
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Table 2-1. Pin Descriptions (continued)
GPIO2
B, PU
General Purpose I/O.
GPIO1
B, PU
General Purpose I/O.
B, PU
General Purpose I/O. Sets AC-link interface for professional section during power-up (default). The state
is reflected on PCI61[7] bit in reverse polarity.
GPIO0 / I²S#
Test Mode
TESTEN#
I, PU
Test Mode Enable. Do not connect for normal operation.
Power and Ground
VCC
Digital Supply Voltage. 3.3V
GND
Ground.
Revision 2.4, May 28, 2002
2-5
Pinouts
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
2.3 Pin Lists
Table 2-2 lists all the pins alphabetically. Table 2-3 lists all the pins in numerical order.
Table 2-2. Alphabetical Pin Listing
Symbol
Pin(s)
Symbol
Pin(s)
AD[31:0]
2, 5-6, 8-12, 15, 28-32, 34-36, 40-44, 47-49,
120-121, 123-127,
PMCLK
85
CBCLK
90
PRST#
105
CBE#[3:0]
3, 16, 25, 37
PSDIN[3:0]
73, 75-77
CMCLK
92
PSDOUT[3:0]
79, 82-84
CRST#
86
PSYNC
72
CSDIN
89
REQ#
119
CSDOUT
91
RST#
114
CSYNC
88
RX1
94
DEVSEL#
21
RX2 / GPIO[7]
59
FRAME#
17
SCLK
71
GND
7, 14,20, 26, 33, 39, 46, 55, 74, 80, 87, 100,
108, 116, 128
SDA
70
GND_X1
64
SPDIN
107
GND_X2
60
SPDOUT
106
GNT#
118
SERR#
23
GPIO[0] / I²S#
50
SPMCLKIN
111
GPIO[1]
51
SPMCLKOUT
112
GPIO[2]
52
SPSCLK
110
GPIO[3] / E²PROM
53
SPSYNC
109
GPIO[4]/S0
56
STOP#
22
GPIO[5]/S1
57
TESTEN#
69
GPIO[6] / TX2
58
TRDY#
19
GPIO[7] / RX2
59
TX1
95
IDSEL
4
TX2 / GPIO[6]
58
INTA#
113
VCC
1, 13, 27, 38, 45, 54, 81, 115, 122
IRDY#
19
VCC_X1
67
JSD[7:0]
96-99, 101-104
VCC_X2
63
PAR
24
XIN[2:1]
61, 65
PBCLK
78
XOUT[2:1]
62, 66
PCICLK
117
Revision 2.4, May 28, 2002
2-6
Pinouts
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Table 2-3. Numerical Pin Listing
Pin #
Symbol
Pin #
Symbol
Pin #
Symbol
Pin #
Symbol
1
VCC
33
GND
65
XOUT1
97
JSD6
2
AD24
34
AD10
66
VCC_X1
98
JSD5
3
CBE3#
35
AD9
67
VCC
99
JSD4
4
IDSEL
36
AD8
68
GND
100
GND
5
AD23
37
CBE0#
69
TESTEN#
101
JSD3
6
AD22
38
VCC
70
SDA
102
JSD2
7
GND
39
GND
71
SCLK
103
JSD1
8
AD21
40
AD7
72
PSYNC
104
JSD0
9
AD20
41
AD6
73
PSDIN[0]
105
TX2
10
AD19
42
AD5
74
GND
106
SPDOUT
11
AD18
43
AD4
75
PSDIN[1]
107
SPDIN
12
AD17
44
AD3
76
PSDIN[2]
108
VCC
13
VCC
45
VCC
77
PSDIN[3]
109
SPSYNC
14
GND
46
GND
78
PBCLK
110
SPSCLK
15
AD16
47
AD2
79
PSDOUT[0]
111
SPMCLKIN
16
CBE2#
48
AD1
80
GND
112
SPMCLKOUT
17
FRAME#
49
AD0
81
VCC
113
INTA#
18
IRDY#
50
GPIO[0]
82
PSDOUT[1]
114
RST#
19
TRDY#
51
GPIO[1]
83
PSDOUT[2]
115
VCC
20
GND
52
GPIO[2]
84
PSDOUT[3]
116
GND
21
DEVSEL#
53
GPIO[3]
85
PMCLK
117
PCICLK
22
STOP#
54
VCC
86
CRST#
118
GNT#
23
SERR#
55
GPIO[4] / S0
87
GND
119
REQ#
24
PAR
56
GPIO[5] / S1
88
CSYNC
120
AD31
25
CBE1#
57
GPIO[6] / TX2
89
CSDIN
121
AD30
26
GND
58
GPIO[7] / RX2
90
CBCLK
122
VCC
27
VCC
59
GND_X2
91
CSDOUT
123
AD29
28
AD15
60
XIN2
92
CMCLK
124
AD28
29
AD14
61
XOUT2
93
VCC
125
AD27
30
AD13
62
VCC_X2
94
RX1
126
AD26
31
AD12
63
GND_X1
95
TX1
127
AD25
32
AD11
64
XIN1
96
JSD7
128
GND
Revision 2.4, May 28, 2002
2-7
Pinouts
Technologies, Inc.
We Connect
Revision 2.4, May 28, 2002
VT1712 - PCI Multi-Channel Audio Controller
2-8
Pinouts
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
PCI Interface and Configuration Registers
Table 3-1. PCI Host Interface Register Map
Byte 3
Byte 2
Byte 1
Byte 0
Offset (Hex)
Device Identification
Vendor Identification
00
PCI Device Status
PCI Command
04
Class Code
BIST
Header Type
Reserved. Read as 0
Revision ID
08
Latency Timer
Reserved. Read as 0
0C
Controller I/O Base Address
10
DDMA I/O Base Address
14
DMA Path Registers I/O Base Address
18
Professional Multi-Track I/O Base Address
1C
Subsystem ID
Subsystem Vendor ID
2C
Reserved. Read as 0
30
Capability Pointer
34
Reserved. Read as 0
38
Minimum Latency and Maximum Grant
Interrupt Pin and Line
3C
Legacy Configuration Control
Legacy Audio Control
40
Hardware Configuration Control
Power Management Capability
PMCSR Support Extensions and Data
Revision 2.4, May 28, 2002
Next Item Pointer
60
Capability ID
80
Power Management Control and Status
84
3-1
PCI Interface and Configuration Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
3.1 PCI Configuration Registers
PCI00: Vendor Identification
Address Offset: 00 - 01h
Default Value: 1412h
Bit
Attribute
15:0
RO
Description
Vendor Identification Number. 16-bit value assigned to VIA Technologies, Inc.
PCI02: Device Identification
Address Offset: 02 - 03h
Default Value: 1712h
Bit
Attribute
15:0
RO
Description
Device Identification Number. 1712 reflects the part number.
PCI04: PCI Command
Address Offset: 04 - 05h
Default Value: 0000h
Description
Bit
Attribute
15:10
R0b
Reserved. Read as 0s.
9
R0b
Fast Back-to-Back Enable. This bit is hardwired to 0 (Not Implemented).
8
R/W
SERR# enable. 1= enable. 0=disable (default).When enabled, FM and MIDI I/O writes will be trapped and causes
SERR# asserted. PCISTS register reports the status of the SERR# signal.This bit has a shadow defined in register
bit CCS1B_0.
7
R0b
A/D stepping enable. This bit is hardwired to 0 (Not Implemented).
6
R0b
Parity error detect enable. Hardwired to 0 (Not Implemented).
5
R0b
VGA palette snoop enable. Hardwired to 0 (Not Implemented).
4
R0b
Memory write and invalidate enable. Hardwired to 0 (Not Implemented).
3
R0b
Special Cycle Enable (SCE). Hardwired to 0 (Not Implemented).
2
R/W
Bus master enable. 1=enable. 0=disable (default).
1
R0b
Memory Access. Hardwired to 0 (Not Implemented).
0
R/W
I/O Space accesses enable. 1=enable. 0=disable (default).
Revision 2.4, May 28, 2002
3-2
PCI Interface and Configuration Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
PCI06: PCI Status
Address Offset: 06 - 07h
Default Value: 0210h
Description
Bit
Attribute
15
R/W/C
PAR status. Parity error detected (even when parity not enabled).
14
R/W/C
SERR# status. This bit is set to 1 when SERR# is asserted (even when it is not enabled) and cleared by writing 1
to it.
13
R/W/C
Master abort status. This bit is set to 1 when master aborts and cleared by writing "1" to it.
12
R/W/C
Received target abort status. This bit is set to 1 when target abort is received and cleared by writing a 1 to it.
11
R0b
Signaled target abort status. This bit is set when target abort generated and cleared by writing a 1 to it. Hardwired
to 0 (never abort).
10:9
R10b
DEVSEL# timing status. Envy24 always asserts DEVSEL# with medium timing.
8
R0b
PERR# response. Read as 0 (Not Implemented).
7
R0b
Fast back to back. Read as 0 (Not implemented).
6
R0b
User Define Function (UDF). Read as 0 (Not implemented).
5
R0b
Reserved. Read as 0. 33MHz only.
4
R1b
Hardwired to 1 to indicate the support for PCI power management capability.
3:0
R0000b
Reserved. Read as 0s.
PCI08: Revision ID
Address Offset: 08h - 09h
Default Value: 000Xh
Bit
Attribute
15:0
R00h
7:0
RO
Description
Revision ID
PCI0A: Class Code
Address Offset: 0Ah - 0Bh
Default Value: 0401h
Description
Bit
Attribute
15:8
RO
Base Class. Reflects Multimedia
7:0
RO
Sub class. Reflects Audio.
Revision 2.4, May 28, 2002
3-3
PCI Interface and Configuration Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
PCI0C: Cache Size
Address Offset: 0Ch
Default Value: 00h
Bit
Attribute
7:0
RO
Description
Read as 0. Not supported
PCI0D: Latency Timer
Address Offset: 0Dh
Default Value: 00h
Bit
Attribute
Description
7:3
R/W
Latency timer
2:0
RO
Read as 0
PCI0E: Header Type
Address Offset: 0Eh
Default Value: 00h
Bit
Attribute
7:0
RO
Description
Read as 0
PCI0F: BIST
Address Offset: 0Fh
Default Value: 00h
Bit
Attribute
7:0
RO
Description
Read as 0. Not supported
PCI10: Envy24 I/O Base
Address Offset: 10h - 13h
Default Value: 00000001h
Description
Bit
Attribute
31:5
RW
Controller I/O Base Address for CCSxx registers described in section 4.1
4:1
R0h
Hardwired to 0 to have 32 bytes I/O space. This includes UARTs and game port.
0
R1b
Hardwired to 1 to indicate registers map to I/O space
Revision 2.4, May 28, 2002
3-4
PCI Interface and Configuration Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
PCI14: DDMA I/O Base
Address Offset: 14h -17h
Default Value: 00000001h
Bit
Attribute
31:4
R/W
3:1
R000b
0
R1b
Description
DDMA Slave Channel Base Address for DDMAx registers described in section 4.2
Hardwired to 0 to have 16 bytes I/O space
Hardwired to 1 to indicate registers map to I/O space
PCI18: DMA Path Registers I/O Base
Address Offset: 18h - 1Bh
Default Value: 00000001h
Bit
Attribute
31:4
R/W
3:1
R000b
0
R1b
Description
DMA path registers I/O Base Address for DSx registers described in section 4.4
Hardwired to 0 to specify requirement of 16 bytes I/O space
Hardwired to 1 to indicate registers map to I/O space
PCI1C: Multi-Track I/O Base
Address Offset: 1Ch - 1Fh
Default Value: 00000001h
Description
Bit
Attribute
31:6
R/W
5:1
R0
Hardwired to 0 to have 64 bytes I/O space
0
R1b
Hardwired to 1 to indicate registers map to I/O space
Multi-Track I/O Base Address for MTxx registers described in section 4.5
PCI2C: Sub-Vendor ID
Address Offset: 2Ch - 2Fh
Default Value: 17121412h
Bit
Attribute
31:0
RO
Revision 2.4, May 28, 2002
Description
Sub-vendor ID: Read it from external E²PROM after reset if it exists, otherwise, same as vendor ID. It can also
be written by disabling write protection bit defined in PCI42_7.
3-5
PCI Interface and Configuration Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
PCI34: Capability Pointer
Address Offset: 34h
Default Value: 80h
Bit
Attribute
7:0
RO
Description
CP7-CP0: Capability data structure pointer for PCI power management. Hardwired to 80h.
PCI34: Interrupt Pin and Line
Address Offset: 3Ch - 3Dh
Default Value: 01FFh
Description
Bit
Attribute
15:8
RO
01h read from this register indicates the interrupt pin used is INTA# and cannot be modified.
7:0
R/W
Interrupt line routing information set by POST during power-up initialization. Default FFh indicates no
connection to the PIC yet.
PCI3E: Latency and Grant
Address Offset: 3Eh - 3Fh
Default Value: 0000h
Description
Bit
Attribute
15:8
RO
Maximum latency
7:0
RO
Minimum grant
Revision 2.4, May 28, 2002
3-6
PCI Interface and Configuration Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
PCI40: Legacy Audio Control
Address Offset: 40h - 41h
Default Value: 807Fh
Description
Bit
Attribute
15
R/W
14:12
R000b
11:10
R/W
Reserved
9:8
R/W
Reserved
7:6
R/W
SB DMA Channel Select:
00 DMA 0
01 DMA 1 (default)
10 Reserved
11 DMA 3
5
R/W
I/O Address Alias Control
1: select the 10-bit decode (default)
0: select the 16-bit decode In either case, the AD(31:16) should be zero
4
R/W
Reserved
3
R/W
MPU-401 I/O enable
2
R/W
Game Port enable (200h)
1
R/W
FM I/O enable (AdLib 388h base)
0
R/W
SB I/O enable
Revision 2.4, May 28, 2002
0: Legacy Audio Hardware enable.
1: Legacy Audio Hardware disabled (default)
-
3-7
PCI Interface and Configuration Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
PCI42: Legacy Configuration Control
Address Offset: 42h - 43h
Default Value: 0006h
Description
Bit
Attribute
15:8
R/W
Interrupt vector to be snooped.
7
R/W
0: SVID read only. (default)
1: SVID read/write enable.
6
R/W
0: snoop SB 22C/24Ch I/O write cycle to assert SERR#: disable (default)
1: snoop SB 22C/24Ch I/O write cycle to assert SERR# : enable
5
R/W
0: snoop PIC I/O R/W cycle to assert SERR#: disable (default)
1: snoop PIC I/O R/W cycle to assert SERR#: enable
4
R/W
0: snoop PCI bus interrupt acknowledge cycle: disable (default)
1: snoop PCI bus interrupt acknowledge cycle: enable
3
R/W
0: SB base 220h (default)
1: SB base 240h
2:1
R/W
0: MPU-401 base 300h
1: MPU-401 base 310h
2: MPU-401 base 320h
3: MPU-401 base 330h (default)
0
RW
0: DDMA enable (default)
1: Legacy DMA enable
Revision 2.4, May 28, 2002
3-8
PCI Interface and Configuration Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
PCI60: System Configuration
Address Offset: 60h
Default Value: 0Fh
The following four bytes (60h-63h) should be read from E2PROM by driver and then written to setup the codec
configuration, unless otherwise noted.
Bit
Attribute
Description
7:6
R/W
XIN2 Clock Source Configuration. Refer to register MT01 and Table A-2 in the Appendix
00: XIN2: 22.5792MHz crystal (44.1kHz*512)
01: XIN2: 16.9344MHz crystal (44.1kHz*384)
10: XIN2: from external clock synthesizer chip (e.g. MK1412) which needs to be controlled via S0, S1 pins.
These shared GPIO4 and 5 pins become write only and the direction will not be controllable via CCI22.
11: - Reserved
5
R/W
0: one MPU-401 UART only
1: two MPU-401 UARTs.
4
R/W
Consumer AC'97 codec:
0: Consumer AC'97 does exist
1: Consumer AC'97 does not exist
R/W
Must have at least one pair of professional multi-track ADC and DAC.
00: one stereo ADC connected
01: two stereo ADCs connected
10: three stereo ADCs connected
11: four stereo ADCs connected
R/W
Must have at least one pair of professional multi-track ADC and DAC.
00: one stereo DAC connected
01: two stereo DACs connected
10: three stereo DACs connected
11: four stereo DACs connected
3:2
1:0
PCI61: AC-Link Configuration
Address Offset: 61h
Default Value: 00h
Except for bit 7, the four bytes at 60h-63h should be read from E2PROM by driver and then written to setup the codec
configuration.
Description
Bit
Attribute
7
R/W
Multi-track converter type: 0: AC'97 1: I²S.
Reflects power-up status of pin 50 during reset cycle in reverse polarity. Can be overwritten
6:2
R/W
Reserved.
1
R/W
If bit 7 is 0:
0: split mode: AC’97 codec SDATA_OUT split to different pin outputs
1: packed mode: AC’97 codec SDATA_OUT packed in slots 3 to 10
0
R/W
If bit 7 is 0:
0: split mode: AC’97 code:SDATA_IN split from different pin inputs
1: packed mode: AC’97 codec SDATA_IN packed in slots 3 to 10
Revision 2.4, May 28, 2002
3-9
PCI Interface and Configuration Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
PCI62: I2S Converters Features
Address Offset: 62h
Default Value: 01h
This byte is valid only when PCI61_7 is 1. The four bytes at 60h-63h should be read from E2PROM by driver and then
written to setup the codec configuration.
Description
Bit
Attribute
7
R/W
For I²S codec Volume and mute
0: I²S codec has no volume/mute control feature.
1: I²S codec has volume/mute control capability and need to be program through GPIO (e.g., CS4222)
6
R/W
I²S converter 96kHz sampling rate support. 0: does not; 1 : supports
5:4
R/W
Converter resolution:
00: 16-bit
01: 18-bit
10: 20-bit
11: 24-bit
3:0
R/W
Other I²S IDs
PCI63: S/PDIF Configuration
Address Offset: 63h
Default Value: 03h
The four bytes at 60h-63h should be read from E2PROM by driver and then written to setup the codec configuration.
Description
Bit
Attribute
7:2
R/W
S/PDIF chip ID
1
R/W
1: S/PDIF Stereo In is present. Forces 64bpf on I²S interface.
0
R/W
1: S/PDIF Stereo Out is present. Forces 64bpf on I²S interface.
PCI80: Capability ID
Address Offset: 80h
Default Value: 01h
Bit
Attribute
Description
7:0
RO
Capability ID
PCI81: Next Item Pointer
Address Offset: 81h
Default Value: 00h
Bit
Attribute
7:0
RO
Revision 2.4, May 28, 2002
Description
Hardwired to 0 to indicate the end of list
3 - 10
PCI Interface and Configuration Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
PCI82: Power Management Capabilities
Address Offset: 82h - 83h
Default Value: 0401h
Description
Bit
Attribute
15:11
RO
PME not supported. Hardwired to 0.
10
R1
D2 state support. Hardwire to 1.
9
R0
D1 state not support. Hardwired to 0.
8:6
R000
5
R0
DSI. Hardwired to 0.
4
R0
Aux. Power. Hardwired to 0
3
R0
PMC clock for generation of PME#. Hardwired to 0.
2:0
R001b
Reserved.
Hardwired to 001 to indicate PPMI 1.0 compliance
PCI84: Power Management Control / Status
Address Offset: 84h - 85h
Default Value: 0000h
Description
Bit
Attribute
15
R0b
PME status. Read as 0.
14:13
R00b
Data scale. Not supported.
12:9
R0h
Data select: Not supported.
8
R0b
PME assertion. Hardwired to 0
7:2
RO
Hardwired to 000000
R/W
Power state. To determine the current state of power state.
00 : D0
01 : D1 (not supported)
10 : D2
11 : D3_hot
1:0
PCI86: Power Management Control / Status (PMCSR) Base and Data
Address Offset: 86h - 87h
Default Value: 0000h
Bit
Attribute
15:0
R0000h
Revision 2.4, May 28, 2002
Description
-
3 - 11
PCI Interface and Configuration Registers
Technologies, Inc.
We Connect
Revision 2.4, May 28, 2002
VT1712 - PCI Multi-Channel Audio Controller
3 - 12
PCI Interface and Configuration Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Hardware Interfaces & Interface Registers
In the previous section PCI host interface and configuration registers were discussed. In this section description of the
major blocks, their respective hardware interfaces and associated registers will be discussed. In most cases the four I/O
base addresses have a one to one correspondence with the major functional blocks. Therefore, the following subchapters will be organized based on the logical grouping of the registers on the offsets of their respective I/O base
addresses.
The first figure in this section, Figure 4-4-1, is a chip level block diagram with typical external interface usage. It is a
very good overview of the whole chip, but should not be regarded as the most detailed diagram. As appropriate, the
databook will resort to sub-block diagrams to further detail the functionality. These are the multi-track DMA transfer
mechanism, data stream routing capabilities and the digital mixer block diagram.
Revision 2.4, May 28, 2002
4-1
Hardware Interfaces & Interface Registers
Four I2S
or AC-Link
Pairs
4 ADC/Codec
AC’97 Codec
Four I2S
or AC-Link
Pairs
I2S I/O
Technologies, Inc.
We Connect
Revision 2.4, May 28, 2002
4 DAC/Codec S/PDIF I/O
AC-Link I/F
Σ
2x20b ch.
12x24b ch.
2x16b ch.
16 ch. SRC and DS
Digital Mixer
20 Ch., 36b
Digital Mixer
10x24b ch.
12x24b ch.
RX2 TX2
MPU-401
UART
MPU-401
UART
SD
GPIO
JSD
8-bit
GPIO
Joystick
Port
10x24b ch.
DMA
DMA
DirectSound
DMA
14 str.
Legacy
and
Audio
PCM
8/16b
Record
DMA
packed path
PCI 2.1 Bus Master BIU with Burst Mode
Hardware Interfaces & Interface Registers
PCI BUS
Figure 4-1. Functional Block Diagram
I²C/E²PROM
PORT
VT1712 - PCI Multi-Channel Audio Controller
4-2
RX1 TX1
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
4.1 Controller Registers
The following registers are offset from base address set by PCI10. The 32 bytes I/O space includes main control / status
registers, I2C interface, MPU-401 MIDI UARTs and game port control as well. Each CCSxx register is physically
located at the address determined by [PCI10]+xx and accessed directly. The registers can be accessed as a byte, word or
dword register.
Table 4-2. CCSxx Controller Register Map
Byte 3
Byte 2
Byte 1
Byte 0
Offset (Hex)
CCIxx Index
Envy24 Status
Interrupt Mask
Envy24 Control/Stat.
00
NMI Index
NMI Data
NMI Status 1
CCIxx Data
04
C. AC ‘97 Comm./Stat.
Cons. AC ‘97 Index
08
Consumer AC ‘97 Data Port
Game Port
NMI Status 2
MIDI 1 Comm./Status
MIDI UART 1 Data
0C
I²C Port Control/Status
I²C Port R/W Data
I²C Port Byte Address
I²C Port Dev. Address
10
Consumer Record DMA Current/Base Address
SERR# Shadow
Timer
14
Consumer Record DMA Count Address
MIDI 2 Comm./Status
MIDI UART 2 Data
18
1C
CCS00: Control / Status
Address Offset: 00h
Default Value: 00h
Description
Bit
Attribute
7
R/W
Entire Chip soft reset
6
R/W
Legacy mode only:
1: enable SERR# assertion for the DS DMA Channel-C interrupt
0: disable SERR# assertion for the DS DMA Channel-C interrupt (default)
5
RO
4
R/W
Legacy mode only:
1: set the DOS WT volume control coming from DS Channel-C/D index registers B.
0: set the DOS FM volume control coming from SB mixer register space. (default)
This bit is used in the legacy mode for the switching between FM and WT under DOS. For FM and WT under
Windows, it is always coming from DS Channel-C/D index register B.
3
R/W
0: SERR# level (default)
1: SERR# edge (only one PCI clock width)
2
R0
1
R/W
Legacy mode only:
1: enable SERR# assertion for SB interrupt
0: disable SERR# assertion for SB interrupt (default)
0
R/W
Mode select: 0: SB mode 1: native mode
Revision 2.4, May 28, 2002
-
4-3
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
CCS01: Interrupt Mask
Address Offset: 01h
Default Value: FEh
Description
Bit
Attribute
7
R/W
Primary MIDI interrupt mask
6
R/W
Timer mask
5
R/W
Secondary MIDI interrupt mask.
4
R/W
Professional Multi-track playback and record. This is the macro interrupt mask for both playback and record.
3
R/W
FM/MIDI trapping interrupt mask
2
R/W
Playback DS DMA channels mask (effective for all the playback DMA channels from 0 to D)
1
R/W
Consumer record DMA channel interrupt mask
0
R/W
Consumer/SB mode playback interrupt mask (DMA channel E and F)
CCS02: Interrupt Status
Address Offset: 02h
Default Value: 00h.
These bits are sticky and only writing a 1 to that bit location will clear itself.
Description
Bit
Attribute
7
R/W/C
Primary MIDI receiver FIFO
6
R/W/C
Timer
5
R/W/C
Secondary MIDI receiver FIFO
4
RO
3
R/W/C
2
RO
1
R/W/C
Native mode record (Record DMA)
0
R/W/C
Native/SB playback
Revision 2.4, May 28, 2002
Multi-track playback or record. This is the macro interrupt status for both playback and record. To clear individual
status bit, write a 1 to the associated bit location defined in section 4.4.
FM/MIDI trapping
Direct Sound. This is the macro interrupt status for DS Channels (0 through D). To clear individual status bit,
Write a 1 to the associated bit location defined in the DS DMA channel register section.
4-4
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
CCS03: Envy24 Index
Address Offset: 03h
Default Value: 00h
Description
Bit
Attribute
7:6
R00b
-
5:0
R/W
Index register. Write the CCIxx register’s xx index as described in section 4.1.1.
CCS04: Envy24 Data
Address Offset: 04h
Default Value: 00h.
Bit
Attribute
Description
7:0
See 4.1.1
Data register. Content for CCIxx register.
Revision 2.4, May 28, 2002
4-5
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
CCS05: NMI Status 1
Address Offset: 05h
Default Value: 00h
Description: This register pertains to legacy audio hardware synthesis emulation in DOS. Reading from this register will
clear itself and de-assert the SERR# signal. However, it will not clear the SERR# bit PCI06[14]. To clear it, write 1 to
that bit location instead. Refer to register CCS0E as well.
Description
Bit
Attribute
7
RO
1: PCI I/O read/write cycle if bit PCI43[5] is set to 1.
6
RO
1: SB 22C/24C write if bit PCI 43[6] is set to 1.
5
R0b
-
4
RO
1: SB interrupt (either SB DMA or SB F2 command) if bit [PCI10][1] is set to 1.
3
RO
1: DS channel C DMA interrupt (for FM/WT data transfer DMA) if bit [PCI10][6] is set to 1.
2
RO
1: MIDI 330h or [PCI_10]h+Ch write
1
R0
-
0
RO
1: FM data register write (389h/221h/229h/38bh/223h)
CCS06: NMI Data
Address Offset: 06h
Default Value: 00h
Description: This register pertains to legacy audio hardware synthesis emulation in DOS.
Bit
Attribute
7:0
RO
Description
Trapped data for TSR to be read (either FM 389h(221h,229h)/38bh(223h), MIDI 330h write, PIC I/O or SB 22C/
24C write cycle (if enabled). Note that only write to FM data will assert SERR# but not write to FM index.
CCS07: NMI Index
Address Offset: 07h
Default Value: 00h
Description: This register pertains to legacy audio hardware synthesis emulation in DOS.
Bit
Attribute
7:0
RO
Revision 2.4, May 28, 2002
Description
Trapped data for FM Index only.
4-6
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
CCS08: Consumer AC’97 Index
Address Offset: 08h
Default Value: 00h
Description
Bit
Attribute
7
R0b
-
6:0
R/W
AC’97 registers Index. Refer to the AC’97 specification for register descriptions.
CCS09: Consumer AC’97 Command and Status
Address Offset: 09h
Default Value: 00h
Description
Bit
Attribute
7
R/W
Cold reset
W: 1 to cold reset the codec. 0: CRST# will be de-asserted.
6
R/W
Warm reset
W: 1 to warm reset the codec by asserting CSYNC. 0: CSYNC will be de-asserted.
5
R/W
W: 1 to write to AC’97 codec registers
R: 1 indicate the write cycle is still in progress. Cleared when write cycle is complete.
4
R/W
W: 1 to read from AC’97 codec registers
R: 1 indicate the read cycle is still in progress. This bit is cleared when there is valid data.
3
RO
AC’97 codec ready status bit.
After power on, driver should check that this bit is 1 before accessing codec registers.
2
R0b
-
1
R/W
Enable VSR for Playback (DirectSound accelerator bypassed. Only Channel-E and F active)
0
R/W
Enable VSR for Record (digital return feature automatically disabled)
CCS0A: Consumer AC’97 Data Port
Address Offset: 0Ah - 0Bh
Default Value: 0000h
Description
Bit
Attribute
15:8
R/W
AC’97 codec register data higher byte (index 0Bh)
7:0
R/W
AC’97 codec register data lower byte (index 0Ah)
Revision 2.4, May 28, 2002
4-7
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
CCS0C: Primary MIDI UART Data
Address Offset: 0Ch
Default Value: 00h
Bit
Attribute
7:0
R/W
Description
MIDI UART data register
CCS0D: Primary MIDI UART Command / Status
Address Offset: 0Dh
Default Value: 00h
Bit
Attribute
7:0
R/W
Description
MIDI UART command and status register
CCS0E: NMI Status 2
Address Offset: 0Eh
Default Value: 00h
Description: This register pertains to legacy audio hardware synthesis emulation in DOS. Reading from this register will
not clear itself. Refer to register CCS05 as well
Description
Bit
Attribute
7:6
R0
-
5:4
RO
FM bank indicator: 01: FM bank 0 (388h/220h/228h) 10: FM bank 1 (38ah/222h)
3:0
RO
PIC I/O cycle
0001: 20h write
0010: A0h write
0101: 21h write
0110: A1h write
1001: 20h read
1010: A0h read
1101: 21h read
1110: A1h read
CCS0F: Game Port
Address Offset: 0Fh
Default Value: 00h
Bit
Attribute
7:0
RW
Revision 2.4, May 28, 2002
Description
Game port register
4-8
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
CCS10: I2C Port Device Address
Address Offset: 10h
Default Value: 00h
Each write to this register will trigger to start the read/write cycle. So, before write to this I/O address, driver needs to
check to make sure that the status bit is idle as defined in the I²C status register CCS13. The controller is always the only
master and does not support multi-byte data burst mode.
Description
Bit
Attribute
7:1
R/W
I2C device address.
Device address "1010000" is reserved for the external I²C E2PROM such as 24C02 for sub-vendor ID and
configuration data.
0
R/W
0: read 1: write
CCS11: I2C Port Byte Address
Address Offset: 11h
Default Value: 00h
Bit
Attribute
7:0
R/W
Description
Byte address to read or write
CCS12: I2C Port Read / Write Data
Address Offset: 12h
Default Value: 00h
Bit
Attribute
7:0
RW
Description
Read or write data
CCS13: I2C Port Control and Status
Address Offset: 13h
Default Value: 00h
When bit 0 is 0 (meaning the I2C port is idle), SCLK (pin 71) will be tri-stated. Envy24 is providing the serial clock
only when it reads/writes through I2C bus at a nominal rate of 31.25 KHz.
Description
Bit
Attribute
7
RO
6:2
0
1
R/W
Reserved. Keep at 0 state.
0
RO
I²C port read/write status. 0: idle 1: busy
Revision 2.4, May 28, 2002
Reflects the power strapping on GPIO3 (pin 53). A 1 (default) indicates external E2PROM exists. A 0 (pull down
by a resistor) means, no external E2PROM connected.
-
4-9
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
CCS14: Consumer Record DMA Current / Base Address
Index: 14h - 17h
Default Value: 00000000h:
Bit
Attribute
31:28
R0
27:0
R/W
Description
Write the Record DMA base address
Read the current Record DMA count
Byte aligned boundary is supported on this DMA channel.
CCS18: Consumer Record DMA Current / Base Count
Index: 18h - 19h
Default Value: 0000h
Bit
Attribute
15:0
R/W
Description
Write the Record DMA initial buffer size in bytes minus one. This register auto-decrements as the DMA transfer
progresses. It reinitializes automatically to the original buffer size once it reaches 0 count.
Read current Record DMA pointer.
See also registers CCI10 and CCI11 for Record DMA interrupt generation.
Revision 2.4, May 28, 2002
4 - 10
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
CCS1B: PCI Configuration SERR# Shadow
Address Offset: 1Bh
Default Value: 00h
Bit
Attribute
7:1
R0
0
R/W
Description
Reserved.
This bit shadows bit PCI04[8]. A 1 indicates SERR# assertion enabled, a 0 assertion disabled
CCS1C: Secondary MIDI UART Data
Address Offset: 1Ch
Default Value: 00h
Bit
Attribute
7:0
R/W
Description
MIDI UART data register
CCS1D: Secondary MIDI UART Command / Status
Address Offset: 1Dh
Default Value: 00h
Bit
Attribute
7:0
R/W
Description
MIDI UART command and status register
CCS1E: Timer
Index: 1Eh - 1Fh
Default Value: 4000h
Description
Bit
Attribute
15
R/W
0: Timer count disable (default)
1: Timer count enable
14:0
R/W
Read: the current timer value
Write: to set up the period for the internal 15 bits timer to generate interrupt.
This timer uses the internal MIDI logic clock (500 KHz).
Revision 2.4, May 28, 2002
4 - 11
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
4.2 Controller Indexed Registers
The following section describes the content to be written to or read through CCS03 and CCS04 registers and their effect
on the controllers operation. These 8-bit indexed registers manage various functions. It may take multiple accesses if a
functionality control takes more than one 8-bit register.
Registers CCI00 to CCI0F are defined for output through DMA Channel-E and Channel-F while CCI10 to CCI1F for
the consumer section capture on Record DMA channel. See Table 4-2 in section 4.3 for the description of the DMA
channels.
CCI00: Playback Terminal Count (High Byte)
Index: 00h
Default Value: 00h
Bit
Attribute
7:0
WO
Description
Write the high byte playback terminal count in bytes. This register auto-decrements as the DMA transfer
progresses. When it reaches 0, it generates and interrupt. Program the desired count in dword units minus one to
determine the interrupt frequency desired.
CCI01: Playback Terminal Count (Low Byte)
Index: 01h
Default Value: 00h
Bit
Attribute
7:0
WO
Description
Write the high byte playback terminal count in bytes. See description above in CCI00.
CCI02: Playback Control
Index: 02h
Default Value: 00h
Description
Bit
Attribute
7
R/W
Turbo mode (4x up sampling in the host by software), valid only when sampling rate is at 12 KHz or above.
When this bit is set to 1, the Channel E and F in DirectSound will accept the 4x up streams.
6
R/W
Reserved
5
R0b
-
4
R/W
0: 16 bits signed 1: 8 bits unsigned
3
R/W
0: mono 1: stereo
2
R/W
FIFO flush (sticky bit. Requires toggling).
1
R/W
Pause
0
R/W
Playback enable
Revision 2.4, May 28, 2002
4 - 12
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
CCI03: Playback Left Volume / Pan
Index: 03h
Default Value: 07h
Description
Bit
Attribute
7:6
R00b
-
5:0
R/W
Left stream volume: 1.5dB attenuation per step. Default: -10.5dB
000000: 0dB
....
000111 : 10.5 dB (default)
....
011111: -46.5dB
111111: muted (instead of -94.5dB)
CCI04: Playback Right Volume / Pan
Index: 04h
Default Value: 07h
Description
Bit
Attribute
7:6
R00b
-
5:0
R/W
Right stream volume:1.5dB attenuation per step. Default: -10.5dB
000000: 0dB
....
000111 -10.5 dB (default)
....
011111: -46.5dB
111111: muted (instead of -94.5dB)
CCI05: Soft Volume / Mute Control
Index: 05h
Default Value: 05h (about 6.4ms from 0 to 96dB)
Bit
Attribute
7:0
R/W
Revision 2.4, May 28, 2002
Description
Soft volume update rate (48 KHz/[CCI05], about every 20 µs*[CCI05] per 1.5dB step).
These bits apply to all the DirectSound channels 0 through D as well.
4 - 13
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
CCI06: Playback Sampling Rate (Low Byte)
Index: 06h
Default Value: 0xFFh
Bit
Attribute
7:0
R/W
Description
see note below.
Note: SR, consumer mode (WAV PCM on Channel E and F) Sampling Rate is a 20-bit value programmed among registers CCI06 through CCI08.
SR = fs* 220/48000. This has the resolution of less than 1Hz. When it is programmed to (220 -1), sampling rate will be rounded to 48 KHz
exactly.
CCI07: Playback Sampling Rate (Middle Byte)
Index: 07h
Default Value: 0xFFh
Bit
Attribute
7:0
R/W
Description
see note under CCI06.
CCI08: Playback Sampling Rate (High Byte)
Index: 08h
Default Value: 0x0Fh
Description
Bit
Attribute
7:4
R0h
-
3:0
R/W
see note under CCI06.
CCI10: Record Current / Base Terminal Count (High Byte)
Index: 10h
Default Value: 00h
Bit
Attribute
7:0
WO
Revision 2.4, May 28, 2002
Description
Write the high byte record terminal count in bytes. Like register CCS18, this register also auto-decrements as the
DMA transfer progresses. When it reaches 0, it generates and interrupt. Program the desired count in dword units
minus one to determine the interrupt frequency desired.
4 - 14
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
CCI11: Record Current / Base Terminal Count (Low Byte)
Index: 11h
Default Value: 00h
Bit
Attribute
7:0
WO
Description
Write the low byte record terminal count in bytes. See description above in CCI10.
CCI12: Record Control
Index: 12h
Default Value: 00h
Description
Bit
Attribute
7
R/W
1: Digital return enable: (only for DMA Channel-10)
The recorded signal will be the sum of CSDIN and SRC outputs.
6:3
R0h
-
2
R/W
0: 16-bit signed; 1: 8-bit unsigned
1
R/W
0: stereo; 1: mono
0
R/W
0: Record disable 1: Record enable
Conditions in native mode record DMA transfer: It is assumed that:
• 16 bit mono: starting address is in 2X and byte count is 2X (i.e., multiples of 2) bytes -1
• 16 bit stereo: starting address is in 4X and byte count is 4X bytes -1
• 8 bit mono: starting address is in 1X and byte count is 1X bytes -1
• 8 bit stereo: starting address is in 2X and byte count is 2X bytes -1
Each time DMA stops, the lowest bytes of address and count/TC are all need to be programmed before it starts again.
Consumer record only at 48 KHz when using AC’97 codecs, such as the VT1611 that do not incorporate VSR support.
Use the VT1611A to support hardware native VSR.
Revision 2.4, May 28, 2002
4 - 15
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
CCI20: GPIO Data
Index: 20h
Default Value: 00h
The direction is set up in CCI22 the GPIO direction control register. These register bits can be writable only when the
corresponding mask bit is zero in the mask register. Also, if the direction is output, it reads back the last data written.
Some GPIO pins may be optionally configured for predefined functions. The use of these will depend upon board
configuration as defined by the E²PROM settings content. See PCI60 (32-bit) register description for more details.
Bit
Attribute
7:0
R/W
Description
GPIO data (Warning: GPIO pins may be shared with other functions)
CCI21: GPIO Write Mask
Index: 21h
Default Value: FFh
Bit
Attribute
7:0
R/W
Description
GPIO write mask
0: Corresponding CCI20 register bit can be written. 1: Can NOT be written.
CCI22: GPIO Direction Control
Index: 22h
Default Value: 00h
Description
Bit
Attribute
7
R/W
GPIO7 direction. If 2nd MIDI UART in use, this bit will be read as 0 always.
6
R/W
GPIO6 direction. If 2nd MIDI UART in use, this bit will be read as 1 always
5
R/W
GPIO5 direction. If external clock synthesizer is used, this bit will be read as 1 always.
4
R/W
GPIO4 direction. If external clock synthesizer is used, this bit will be read as 1 always.
3
R/W
GPIO3 direction. During reset, this pin is used for E²PROM power-on strapping.
2
R/W
GPIO2 direction. If TESTEN# pin is active, this pin is always input.
1:0
R/W
GPIO1 and GPIO0 direction control register.
For all bits 0: input; 1: output.
Revision 2.4, May 28, 2002
4 - 16
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
CCI30: Consumer Section Power Down
Index: 30h
Default Value: 00h
Description
Bit
Attribute
7
R/W
1: Crystal clock generation power down for XTAL_1
6
R/W
1: Game port analog power down
5
R/W
Reserved.
4
R/W
1: Stop I²C port clock
3
R/W
1: Stop MIDI clock
2
R/W
1: Stop AC’97 clock
1
R/W
1: Stop DS Block clock
0
R/W
1: Stop PCI clock for SB, DMA controller (excluding PCI BIU, config. space and this register)
CCI31: Multi-Track Section Power Down
Index: 31h
Default Value: 00h
Description
Bit
Attribute
7
R/W
1: Crystal clock generation power down for XTAL_2
6:3
R/W
Reserved
2
R/W
1: Stop S/PDIF clock
1
R/W
1: Stop Professional digital mixer clock
0
R/W
1: Stop Multi-track I²S serial interface clock
There are four power states defined in the PCI bus power management spec.
States
Description
D0
Normal operation state after system power up or internal reset
D1
not supported.
D2
Power down all the blocks defined in the power down registers.
D3(hot)
Same as D2 state, except a transition to D0 will generate an internal reset (incl. PCI config. space)
Revision 2.4, May 28, 2002
4 - 17
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
4.3 DDMA Registers
The following register definitions are derived from the DDMA spec. They are used by the SoundBlaster legacy block
(playback or record) Microsoft Windows MMSystem Wave (WAV) playback, also known as native mode. The
following registers are offset from the base address set by PCI14 and described below by the [PCI14] symbol to reflect
the DDMA base address.
Description
I/O Address
Attribute
[PCI14] + 0h
R/W
DMA Base and Current Address bit 0-7
[PCI14] + 1h
R/W
DMA Base and Current Address 8 : 15
[PCI14] + 2h
R/W
DMA Base and Current Address 16 :23
[PCI14] + 3h
R/W
DMA Base and Current Address 24 : 31
[PCI14] + 4h
R/W
DMA Base and Current Count 0 : 7
[PCI14] + 5h
R/W
DMA Base and Current Count 8 :15
[PCI14] + 6h
-
DMA Base and Current Count 16 : 23
(Not supported, reflecting the 64K page boundary)
[PCI14] + 7h
-
Reserved
[PCI14] + 8h
R/W
[PCI14] + 9h
-
Request. Not implemented.
[PCI14] + Ah
-
Reserved
[PCI14] + Bh
W
Mode
[PCI14] + Ch
W
Master reset
[PCI14] + Dh
-
Master clear. Not implemented.
[PCI14] + Eh
-
Reserved
[PCI14] + Fh
W
Revision 2.4, May 28, 2002
Status and Command
Channel Mask
4 - 18
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
4.4 DMA Path Descriptions
Physically, there are 19 individual bus master DMAs, 17 for playback and 2 for record. DMA Channels 0 to F are for the
Consumer section (both native/SoundBlaster and DirectSound streams playback) as described in 4.4. Record DMA is
used for native 48 KHz record. Both of consumer playback and record paths are interfaced to an external AC'97
compliant codec via AC-link. Channel-10 is used for transferring 10 individual data streams (e.g., 8 multi-track
playback and one stereo S/PDIF) to 24-bit outputs. The relevant register descriptions can be found in section 4.5. These
10 streams are sent from the system memory in interleaved data format through one DMA FIFO/address/count/control
register set only. Channel-11 is used for transferring 12 individual data streams (e.g. one stereo pair returned from the
professional digital mixer, 8 professional multi-track record and one stereo S/PDIF input). These 12 streams are sent to
the system memory in interleaved data format through one DMA FIFO/address/count/control register set only. Both of
these playback/record channels can support externally I²S type and AC'97 compliant codecs.
Table 4-3. DMA Channels and Respective Functionality
DMA Channels
Cosumer/Multi-Track
Channel-0
DirectSound - 0
O
CSDOUT: L/R
Channel-1
DirectSound - 1
O
CSDOUT: L/R
Channel-2
DirectSound - 2
O
CSDOUT: L/R
Channel-3
DirectSound - 3
O
CSDOUT: L/R
Channel-4
DirectSound - 4
O
CSDOUT: L/R
Channel-5
DirectSound - 5
O
CSDOUT: L/R
Channel-6
DirectSound - 6
O
CSDOUT: L/R
Channel-7
DirectSound - 7
O
CSDOUT: L/R
Channel-8
DirectSound - 8
O
CSDOUT: L/R
Channel-9
DirectSound - 9
O
CSDOUT: L/R
Channel-A
DirectSound - A
O
CSDOUT: L/R
Channel-B
DirectSound - B
O
CSDOUT: L/R
Channel-C
DirectSound - C (FM/WT-L)
O
CSDOUT: L
Channel-D
DirectSound - D (FM/WT-R)
O
CSDOUT: R
Channel-E
DirectSound - E (PCM-L)
O
CSDOUT: L
Channel-F
DirectSound - F (PCM-R)
O
CSDOUT: R
Record DMA
SB/MMSYS PCM L/R Record
I
CSDIN: L/R
Channel-10
Multi-track Playback (10 interleaved)
O
PSDOUT0-3 L/R and SPDOUT
Channel-11
Multi-track Record (12 interleaved)
I
PSDIN0-3 L/R, SPDIN and digital mix
Revision 2.4, May 28, 2002
Direction
4 - 19
Destination/Source
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
4.5 Consumer Section DMA Channel Registers
The following registers are offset from base address set by PCI18. The DSx registers are located at [PCI18]+x. The 16
bytes I/O space controls the consumer section DMA channels for DOS legacy, native and DirectSound.
Table 4-4. DSx Consumer DMA Channel Register Map
Byte 3
Byte 2
Byte 1
DirectSound DMA Interrupt Status
Byte 0
Offset (Hex)
DirectSound DMA Interrupt Mask
Channel Data
00
04
-
Channel Index
-
08
0C
DS0: DirectSound DMA Interrupt Mask
Address Offset: 00 - 01h
Default Value: 3FFFh
Description
Bit
Attribute
15:14
R00b
-
13:00
R/W
Each bit corresponding to the interrupt mask for each channel (0 to D). Default is masked.
DS2: DirectSound DMA Interrupt Status
Address Offset: 02 - 03h
Default Value: 0000h
Bit
Attribute
15:14
R00b
13:0
R/WC/
Revision 2.4, May 28, 2002
Description
Each bit corresponding to the interrupt status of each channel (0 to D)
These are sticky bits. The driver needs to clear by writing a 1 to the corresponding bit.
4 - 20
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
DS4: Channel Data
Address Offset: 04h - 07h
Default Value: 00000000h.
Bit
Attribute
31:0
R/W
Description
Channel Data register. See 32-bit index register description after Table
4-5.
DS8: Channel Index
Address Offset: 08h
Default Value: 00h
Description
Bit
Attribute
7:4
R/W
Channel number. Valid only from Channel-0 to D. E and F are reserved for PCM streams regardless
whether running in native or SB mode.
3:0
R/W
Channel Index register. The table below is used for command decoding purposes.
Table 4-5. DS8 Register, Low Nibble Index Description Applicable to Channel-0 through D
Description
Index
Attribute
0h
R/W
Bits [27:0]
W: Buffer_0 DMA base address[27:0]
R: current active DMA buffer address[27:0]. Byte address.
1h
R/W
Bits [15:0]
W: Buffer_0 DMA base count [15:0]
R: current active DMA count [15:0]. Program byte count minus one.
2h
R/W
Bits[27:0]
W: Buffer_1 DMA base address bit [27:0]
R: same as in index 0h. Byte address
3h
R/W
Bits [15:0]
W: Buffer_1 DMA base count [15:0]
R: same as in index 1h. Program byte count minus one.
4h
R/W
Bits [7:0] R/W: Channel Control and Status register.
5h
R/W
Bits [19:0] Channel Sampling Rate
6h
R/W
Bits [13:0] (see note below) Channel left and right volume/pan control
Note:
• When the playback enable bit is changed from 0 to 1 (in Index 4 bit 0), the first active buffer will be from buffer 0.
Before this, the return active address and count will not be updated.
Conditions in DMA transfer:
•
•
•
•
16 bit mono: starting address is in 2X and count is multiple of 2X bytes (-1)
16 bit stereo: starting address is in 4X and count is multiple of 4X bytes (-1)
8 bit mono: starting address is in 1X and count is multiple of 1X bytes (-1)
8 bit stereo: starting address is in 2X and count is multiple of 2X bytes (-1)
Revision 2.4, May 28, 2002
4 - 21
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Channel Control and Status at Index 4h (DS8 = x4h)
Default: 00000060h
Description
Bit
Attribute
31:8
R000h
7
RO
1: indicating that the current active buffer is Buffer_1.
0: indicating that the current active buffer is Buffer_0.
To avoid the case of reading this bit during the transition, it is recommended that driver read this bit in the ISR so
that the returned address and count are in-sync. with the buffer status.
6
R/W
0: Buffer_1 auto init. disable (single block mode)
1: Buffer_1 auto init. enable (loop mode), default.
5
R/W
0: Buffer_0 auto init. disable (single block mode)
1: Buffer_0 auto init. enable (loop mode ), default.
4
R/W
Flush FIFO
3
R/W
1: stereo; 0: mono (default).
For the DirectSound path this bit is only valid and can be programmed in the even number of channels, i.e.,
0,2,4..,C. The second data element will be routed to the next odd slot into the internal SRC core. Driver should not
program the odd number channel address and count etc. since it is occupied. (sampling rate and volume should
still be programmed, however).
2
RW
Consumer mode data format:
0: 16-bit signed; 1: 8-bit unsigned
1
RW
DMA request 1:pause
0
RW
DMA request 1: start, 0:stop
-
Consumer Mode Sampling Rate at Index 5h (DS8 = x5h)
Index: 05h
Default Value: 0x000FFFFFh (48 KHz)
Bit
Attribute
31:20
R0
19:00
R/W
Revision 2.4, May 28, 2002
Description
SR: Sampling Rate for all DirectSound streams (except Channel E and F, see CCI06) is a 20-bit value. SR = fs*
220/48000. This has the resolution of less than 1Hz. When it is programmed to (220 -1), sampling rate will be
rounded to 48 KHz exactly.
4 - 22
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Consumer Mode Left / Right Volume at Index 06h (DS8 = x6h)
Index: 06h
Default: 00000707h
Bit
Attribute
31:14
R0
13:8
R/W
7:6
R0
5:0
R/W
Description
Right volume:1.5dB attenuation per step.
000000: 0dB
....
000111: -10.5 dB (default)
....
011111: -46.5dB
....
111111: muted (instead of -94.5dB)
Left volume :1.5dB attenuation per step. Default: -10.5dB. Same table as in Right volume.
Note:
Channels E and F are dedicated for consumer PCM left and right streams respectively for either Microsoft Windows
MMSystem Wave (WAV) or SoundBlaster. In the MMSystem mode, the sampling rate and the volume are defined in the
CCS3 and CCS4 index registers. In the SB mode, the sampling rate is coming from SB command and volume is defined
in the SB mixer registers.
Channel C and D are dedicated for FM synthesis output left and right streams respectively in the SB mode. In this case,
the FM volume will be coming from the SB mixer register space setting. The sampling rate, however, is determined
from the above DS8 index registers.
Table 4-6. Channel Parameter Controls
Channels
Mode
Data
Interrupt Status Bit
Volume Control
Sampling Frequency
E:F
Legacy
DOS SB PCM
INTA# (routing)
SB mixer register
SB command
C:D
Legacy
DOS FM
NMI: for I/O trapping INTA#
or NMI for data transfer
SB mixer register
DS8, index register 5
Programmed by TSR
C:D
Legacy
DOS WT
Same as above
DS8=x6h CCS00[4]=1b
Same as above.
E:F
Native
Native PCM
INTA#: CCS02
CCS03, CCS04
SE index registers 6-8
C:D
Native
Native FM/WT
INTA#: DS2, DS3
DS8, index register 6
DS8, index register 5
Revision 2.4, May 28, 2002
4 - 23
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
4.6 Professional Multi-Track Control Registers
The following registers are offset from base address set by PCI1C. The MTxx registers are located at [PCI1C]+xx. The
64 bytes I/O space controls the professional multi-track record and playback, audio stream routing, digital mixer and
related output capability. Refer to Table 4-3 on page 19 of this chapter for a concise description of the DMA channels
involved.
Table 4-7. MTxx Controller Register Map
Byte 3
Byte 2
Byte 1
Byte 0
Offset (Hex)
-
I²S data format
Sampling Rate Select.
DMA Int. Mask/Status
00
P. AC ‘97 Comm./Stat.
Prof. AC ‘97 Index
04
Professional section AC ‘97 Data Port
Professional Playback DMA Current/Base Address
P. Playback DMA Current/Base Terminal Count
08
0C
10
Prof. Playback DMA Current/Base Count
-
P. Playback Control
Professional Record DMA Current/Base Address
P. Record DMA Current/Base Terminal Count
P. Record Control
Routing control to PSDOUT[3:0]
Captured data Routing Selection
Vol. Control Ch. Index
Peak meter data
Peak meter index
24
28
2C
Routing control to SPDOUT
Volume Control Rate
18
1C
20
Prof. Record DMA Current/Base Count
-
14
30
34
L/R Volume Control
-
Mixer monitor return
38
3C
4.6.1 Multi-Track Mode Control Registers
MT00: Professional Section DMA Interrupt Mask and Status
Address Offset: 00h
Default Value: C0h
This register relates to both Channel-10 and 11 (Professional playback and record). When DMAs are stopped, the last
latched value is retained. This “DC” value may affect the digital mixer operation.
Description
Bit
Attribute
7
R/W
Multi-track record interrupt mask
6
R/W
Multi-track playback interrupt mask
5:2
R0
1
R/W/C
Multi-track record interrupt status. Write a 1 to clear.
0
R/W/C
Multi-track playback interrupt status. Write a 1 to clear.
Revision 2.4, May 28, 2002
-
4 - 24
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
MT01: Professional Section Sampling Rate Select
Address Offset: 01h
Default Value: 00h.
This register applies to both Channel-10 and 11. For S/PDIF input, correct sampling rate must be set as well. See
Figure 4-4-3 and Figure 4-4-4 on page 27 and page 28 respectively, in this chapter.
Description
Bit
Attribute
7:5
R000b
4
R/W
S/PDIF input clock as the master. 0: disabled
1: enabled. S/PDIF receiver chip provides the master clock through SPMCLKIN (pin 111)
Note that in this mode, 256X is the highest master clock available while the AC’97 MCLK requires
512X. VIA Technologies’ AC’97 codecs, such as the VT1611, are designs based on BCLK which uses
MCLK/2, i.e. 256X. When S/PDIF provides the master clock, if VIA Technologies’ AC’97 codecs
are used, before setting S/PDIF as the master clock, proceed to switching the primary codec into slave
mode (refer to the VT1611 datasheet). In this mode PBCLK will be output from Envy24.
3:0
R/W
Codec sampling rate select:
All multi-track channels are set to the same rate. These bits are ignored if S/PDIF input is master.
0000: 48 KHz
0001: 24 KHz
0010: 12 KHz
0011: 9.6 KHz
0100: 32 KHz
0101: 16 KHz
0110: 8 KHz
0111: 96 KHz
1111: 64 KHz
1000: 44.1 KHz
1001: 22.05 KHz
1010: 11.025 KHz
1011: 88.2 KHz
others: reserved
Revision 2.4, May 28, 2002
-
4 - 25
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
MT02: Professional Section AC’97 Codec I²S Data Format
Address Offset: 02h
Default Value: 00h
Description
Bit
Attribute
7:4
R0
3
R/W
MCLK/LRCLK ratio,
0: 256x (default)
1: 128x
2
R/W
SCLK/LRCLK ratio, i.e. bpf (bits per frame, each frame corresponding to 1/SR)
Typically useful for 44.1 KHz sampling rate and its multiples where converters use 384X oversampling. If S/PDIF
is used as reflected in PCI63[0] or 1, 64bpf mode is forced and this bit is rendered inactive.
0: 64bpf (32/32) default. (PMCLK on pin 85 is 256 * LRCLK)
1: 48bpf (24/24) (PMCLK is 384 * LRCLK)
1:0
R/W
Data format:
00: I²S (timing diagram provided below)
others: Reserved
-
See Figure 4-4-2 below for a timing diagram for bits [1:0]. See Figure 4-4-3 and Figure 4-4-4 on page 27 and page 28
respectively for the visual description of other bits.
PSYNC/
SPSYNC
Left
Right
PBCLK/
SPSCLK
PSDIN[0:3]
PSDOUT[0:3]
SPDIN
SPDOUT
MSB
LSB
MSB
LSB
MSB
Figure 4-2. I²S Format Timing Diagram
MT04: Professional Section AC’97 Codec Index
Address Offset: 04h
Default Value: 00h
Bit
Attribute
7
R0
6:0
R/W
Revision 2.4, May 28, 2002
Description
AC’97 registers Index. Refer to the AC’97 specification for register descriptions.
4 - 26
Hardware Interfaces & Interface Registers
512fsc
256fsc
1
2
SP* = S/PDIF I²S port
CSYNC
(pin 88)
1
256
C* = Consumer section
fsc
P* = Pro section
fsp = Pro sampling rate
SCLK
(pin 71)
1
8
1
49152
fsc = Consumer sampling rate
1
2
MIDI TX/RX rate
MPU-401 and
Game Port logic
XIN1
(pin 64)
256X
divide by
MT02[3]=0
1, 2, 3, 4, 6, 8, 10, 12
Hardware Interfaces & Interface Registers
XIN2
(pin 60)
divide by
1, 2, 4, 8
SPMCLKIN
(pin 111)
256fsp
1
2
MT01[3:0]
for 384X and
SPDIF absent
1
3
MT02[3]=1
PCI60[7:6]=01 &
PCI63[1:0]=00
Master
MT01[4]=0
MT01[4]=1
Slave
PMCLK
(pin 85)
VT1712 - PCI Multi-Channel Audio Controller
4 - 27
Figure 4-3. Crystals to Master Clocks Clock Generation Tree
CBCLK
(pin 90)
Technologies, Inc.
We Connect
Revision 2.4, May 28, 2002
CMCLK
(pin 92)
Technologies, Inc.
We Connect
MT02[3] = 1 &
PCI61[7] = 1
(MT02[3] = 0 or
PCI60[6] = 0)
& PCI61[7] = 1
PMCLK
(pin 85)
MT02[3] = 1 &
PCI61[7] = 1
MT02[3] = 1
1
2
MT01[4] = 1 or
MT02[3] = 0
1
4
MT02[2] = 1 &
PCI63[1:0] = 00b
PBCLK
(pin 78)
1
2
for 384X and SPDIF absent
1
48
default (256X or 128X)
MT02[2] = 0
1
64
1
4
1
8
PCI61[7] = 0
PSYNC
(pin 72)
fsp
1
256
for AC’97 mode only
128X MCLK
default 256X MCLK
or SPDIF in master
1
2
1
64
SPSYNC
(pin 109)
fsp
for AC’97 mode only
Hardware Interfaces & Interface Registers
PCI61[7] = 0
SPMCLKOUT
(pin 112)
128fsp
SPSCLK
(pin 110)
64fsp
SP* = S/PDIF I²S port
P* = Pro section
fsp = Pro sampling rate
VT1712 - PCI Multi-Channel Audio Controller
4 - 28
Figure 4-4. Master Clocks to Bit Clocks, L/R Clocks and Sync Generation
Revision 2.4, May 28, 2002
MT01[4] = 1 & PCI61[7] = 0
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
MT05: Professional Section AC’97 Codec Command / Status
Address Offset: 05h
Default Value: 00h
Description
Bit
Attribute
7
R/W
Cold reset. Write 1 to assert PRST# (pin105) active. Write back 0 to remove reset condition from all professional
section codecs.
6
R/W
Warm reset. Write 1 to have warm reset by asserting PSYNC (pin 72). This bit together with PRST# (pin 105)
active (MT05[7]=1) can be used to set the external VIA Technologies’ primary AC’97 codec to slave mode (such
as the VT1611). This must be done when S/PDIF input is the master. Apply Cold reset to restore codec master
mode.
5
R/W
Write 1 to write to AC’97 codec register
Reading a 1 indicates the write cycle is still in progress, cleared when write cycle complete.
4
R/W
Write 1 to read AC’97 CODEC register
Reading a 1 indicates the read cycle is still in progress, cleared when there is valid data.
3
RO
AC’97 codec ready status bit. After power-on, check that this bit is 1 before accessing codec registers.
2
R0b
-
1:0
R/W
ID for external AC’97 registers read/write.
00: select primary AC’97 codec.
01: select second slave AC’97 codec.
10: select third slave AC’97 codec.
11: select fourth slave AC’97 codec.
MT06: Professional Section AC’97 Codec Data Port
Address Offset: 06h - 07h
Default Value: 00h
Description
Bit
Attribute
15:8
R/W
AC’97 codec register data high byte (index 07h) Refer to the AC’97 specification for register descriptions..
7:0
R/W
AC’97 codec register data low byte (index 06h). Refer to the AC’97 specification for register descriptions.
Revision 2.4, May 28, 2002
4 - 29
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
4.6.2 Multi-Track Playback Registers
The following figure is a visual representation of the multi-track data transfer mechanism. A ping-pong
buffer structure is implemented for a seamless flow of multiple streams. 32-bit data transfers are used regardless of the audio data resolution. All transfer data are left (MSB) justified. Each transfer request results into a
PCI bus master burst cycle.
from physical inputs
to physical outputs
Stream/Track
Stream/Track
1
2
3
4
5
6
7
8
9
10
Byte Lanes
3
2
1
DMA Channel-10
0
3
(Playback)
2
DMA Channel-11
1
0
12
11
10
9
8
7
6
5
4
3
2
1
(Record)
PCI
Figure 4-5. Multi-Track DMA Transfer
MT10: Professional Section Playback DMA Current / Base Address
Index: 10h - 13h
Default Value: 00000000h. Channel-10 interleaves 10 slots, each with 32-bit from the system memory.
Description
Bit
Attribute
31:28
R0h
- (Address space beyond 256MB is not supported)
27:2
R/W
Write the Playback DMA base address in dword units
(up to 256 MB address space supported)
Read current address in dword units.
1:0
R00b
- (This DMA channel supports dword boundary only)
Revision 2.4, May 28, 2002
4 - 30
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
MT14: Professional Section Playback DMA Current / Base Count
Index: 14h - 15h
Default Value: 0000h
Bit
Attribute
15:0
R/W
Description
Write the Playback DMA initial buffer size in dword units minus one. This register auto-decrements as the DMA
transfer progresses. It reinitializes automatically to the original buffer size once it reaches 0 count.
Read the current Playback DMA pointer.
MT16: Professional Section Playback Current / Base Terminal Count
Index: 16 - 17h
Default Value: 0000h
Bit
Attribute
15:0
WO
Description
Write the terminal count. This register also auto-decrements as the DMA transfer progresses. When it reaches 0, it
generates and interrupt. Program the desired count in dword units minus one to determine the interrupt frequency
desired.
MT18: Professional Section Playback and Record Control
Index: 18h
Default Value: 00h.
Description
Bit
Attribute
7:3
R0
2
R/W
1: Record start; 0: Record stop. Shadowed in MT28[0].
1
R/W
1: Pause; 0: Resume
0
R/W
1: Playback start; 0: Playback stop
Revision 2.4, May 28, 2002
-
4 - 31
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
4.6.3 Multi-Track Record Registers
MT20: Professional Section Record DMA Current / Base Address
Index: 20h - 23h
Default Value: 00000000h. Channel-11 interleaves 12 slots, each with 32-bit data to the system memory.
Description
Bit
Attribute
31:28
R0h
- (Address space beyond 256MB is not supported)
27:2
R/W
Write the Playback DMA base address in dword units
(up to 256 MB address space supported)
Read current address in dword units.
1:0
R00b
- (This DMA channel supports dword boundary only)
MT24: Professional Section Record DMA Current / Base Count
Index: 24 - 25h
Default Value: 0000h
Bit
Attribute
15:0
R/W
Description
Write the Record DMA initial buffer size in dword units minus one. This register auto-decrements as the DMA
transfer progresses. It reinitializes automatically to the original buffer size once it reaches 0 count.
Read the current Record DMA pointer after having allowed at least 2 sample frames.
MT26: Professional Section Record Current / Base Terminal Count
Index: 26h - 27h
Default Value: 0000h
Bit
Attribute
15:0
WO
Description
Write the terminal count. This register also auto-decrements as the DMA transfer progresses. When it reaches 0, it
generates and interrupt. Program the desired count in dword units minus one to determine the interrupt frequency
desired.
MT28: Professional Section Record Control
Index: 28h
Default Value: 00h
Bit
Attribute
7:1
R0
0
R/W
Revision 2.4, May 28, 2002
Description
1: Record start; 0: Record stop. Same functionality as MT18[2]
4 - 32
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
4.6.4 Professional Section Digital Loopback
The Envy24 provides an extensive routing capability of the data streams. The following registers control the routing
from numerous sources to various destination. Insertion of the stream routing functionality adds a maximum of a single
sample cycle delay with respect to the original data. The switch matrix being so complex, careful register setting is crucial to avoid undesirable effects. For simplicity of the register description only pin names are used. Refer to the pin list
for pin numbers and location.
The diagram below is a visual representation of possible connection. If a dot is missing on an intersection, it reflects the
lack of routing capabitlity.
Output from DMA
Slot 1
Slot 2
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7
Slot 8
Slot 9
Slot10
Input from ADC
Source
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Stream 8
Stream 9
Stream10
Input to DMA
Slot 1
Slot 2
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7
Slot 8
Slot 9
Slot10
Slot11
Slot12
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Stream 8
Stream 9
Stream10
Output to DAC
Consumer L
Consumer R
Destination
D mix L
D mix R
Figure 4-6. Data Stream Routing Capabilities
Revision 2.4, May 28, 2002
4 - 33
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
MT30: Routing Control for Data to PSDOUT[0:3]
Address Offset: 30h - 31h
Default Value: 00h
When PSDIN[0:3] or SPDIN are selected as the source, refer to register MT34.
Description
Bit
Attribute
15:14
R/W
PSDOUT[3] Right source
00: from DMA Channel-10 output slot 8
01: 10: from PSDIN[X] loopback
11: from SPDIN input loopback
13:12
R/W
PSDOUT[2] Right source
00: from DMA Channel-10 output slot 6
01: 10: from PSDIN[X] loopback
11: from SPDIN input loopback
11:10
R/W
PSDOUT[1] Right source
00: from DMA Channel-10 output slot 4
01: 10: from PSDIN[X] loopback
11: from SPDIN input loopback
9:8
R/W
PSDOUT[0] Right source
00: from DMA Channel-10 output slot 2.
01: from digital mixer monitor Right output
10: from PSDIN[X] loopback
11: from SPDIN input loopback
7:6
R/W
PSDOUT[3] Left source
00: from DMA Channel-10 output slot 7
01: 10: from PSDIN[X] loopback
11: from SPDIN input loopback
5:4
R/W
PSDOUT[2] Left source
00: from DMA Channel-10 output slot 5
01: 10: from PSDIN[X] loopback
11: from SPDIN input loopback
3:2
R/W
PSDOUT[1] Left source
00: from DMA Channel-10 output slot 3
01: 10: from PSDIN[X] loopback
11: from SPDIN input loopback
1:0
R/W
PSDOUT[0] Left source
00: from DMA Channel-10 output slot 1
01: from digital mixer monitor Left output
10: from PSDIN[X] loopback
11: from SPDIN input loopback
Revision 2.4, May 28, 2002
4 - 34
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
MT32: Routing Control for SPDOUT
Address Offset: 32h - 33h
Default Value: 0000h
When PSDIN[0:3] or SPDIN are selected as the source, refer to register 38h-3Bh.
Description
Bit
Attribute
15
R/W
SPDIN input loop back to SPDOUT Right output
1: SPDIN Right input
0: SPDIN Left input
14 : 12
R/W
PSDIN[X] input loop back to SPDOUT Right output
000: PSDIN[0]: L
001: PSDIN[0]: R
010: PSDIN[1]: L
011: PSDIN[1]: R
100: PSDIN[2]: L
101: PSDIN[2]: R
110: PSDIN[3]: L
111: PSDIN[3]: R
11
RW
SPDIN input loop back to SPDOUT Left output
1: S/PDIF right input
0: S/PDIF left input
10:8
RW
PSDIN[X] input loop back to SPDIOUT Left output
000: PSDIN[0]: L
001: PSDIN[0]: R
010: PSDIN[1]: L
011: PSDIN[1]: R
100: PSDIN[2]: L
101: PSDIN[2]: R
110: PSDIN[3]: L
111: PSDIN[3]: R
7:4
R0h
-
3:2
R/W
Source loop back to the SPDOUT Right output
00: from DMA Channel-10 slot 10
01: from digital mixer monitor Right output
10: from PSDIN[X] (defined in bits 14:12 of this register)
11: from SPDIN (defined in bit 15 of this register)
1:0
R/W
Source loop back to the SPDOUT Left output
00: from DMA Channel-10 slot 9
01: from digital mixer monitor Left output
10: from PSDIN[X] (defined in bits 10:8 of this register)
11: from SPDIN (defined in bit 11 of this register)
Revision 2.4, May 28, 2002
4 - 35
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
MT34: Captured (Recorded) Data Routing Selection
Address Offset: 34 - 37h
Default Value: 00000000h.
Description
Bit
Attribute
31
R/W
SPDIN input loopback to PSDOUT[3] Right slot
1: SPDIN Right input
0: SPDIN Left input
30:28
R/W
PSDIN[X] loopback to PSDOUT[3] Right slot
000: PSDIN[0]: L
001: PSDIN[0]: R
010: PSDIN[1]: L
011: PSDIN[1]: R
100: PSDIN[2]: L
101: PSDIN[2]: R
110: PSDIN[3]: L
111: PSDIN[3]: R
27
R/W
SPDIN input loopback to PSDOUT[3] Left slot
1: SPDIN Right input
0: SPDIN Left input
26:24
R/W
PSDIN[X] loopback to PSDOUT[3] Left slot
000: PSDIN[0]: L
001: PSDIN[0]: R
010: PSDIN[1]: L
011: PSDIN[1]: R
100: PSDIN[2]: L
101: PSDIN[2]: R
110: PSDIN[3]: L
111: PSDIN[3]: R
23
R/W
SPDIN input loopback to PSDOUT[2] Right slot
1: SPDIN Right input
0: SPDIN Left input
22:20
R/W
PSDIN[X] loopback to PSDOUT[2] Right slot
000: PSDIN[0]: L
001: PSDIN[0]: R
010: PSDIN[1]: L
011: PSDIN[1]: R
100: PSDIN[2]: L
101: PSDIN[2]: R
110: PSDIN[3]: L
111: PSDIN[3]: R
19
R/W
SPDIN input loopback to PSDOUT[2] Left slot
1: S/PDIF right input
0: S/PDIF left input
Revision 2.4, May 28, 2002
4 - 36
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Description
Bit
Attribute
18:16
R/W
PSDIN[X] loopback to PSDOUT[2] Left slot
000: PSDIN[0]: L
001: PSDIN[0]: R
010: PSDIN[1]: L
011: PSDIN[1]: R
100: PSDIN[2]: L
101: PSDIN[2]: R
110: PSDIN[3]: L
111: PSDIN[3]: R
15
R/W
SPDIN input loopback to PSDOUT[1] Right slot
1: SPDIN Right input
0: SPDIN Left input
14 : 12
R/W
PSDIN[X] loopback to PSDOUT[1] Right slot
000: PSDIN[0]: L
001: PSDIN[0]: R
010: PSDIN[1]: L
011: PSDIN[1]: R
100: PSDIN[2]: L
101: PSDIN[2]: R
110: PSDIN[3]: L
111: PSDIN[3]: R
11
R/W
PSDIN[X] loopback to PSDOUT[1] Left slot
1: S/PDIF right input
0: S/PDIF left input
10:8
R/W
PSDIN[X] loopback to PSDOUT[1] Left slot.
000: PSDIN[0]: L
001: PSDIN[0]: R
010: PSDIN[1]: L
011: PSDIN[1]: R
100: PSDIN[2]: L
101: PSDIN[2]: R
110: PSDIN[3]: L
111: PSDIN[3]: R
7
R/W
SPDIN input loopback to PSDOUT[0] Right slot
1: SPDIN Right input
0: SPDIN Left input
6:4
R/W
PSDIN[X] loopback to PSDOUT[0] Right slot
000: PSDIN[0]: L
001: PSDIN[0]: R
010: PSDIN[1]: L
011: PSDIN[1]: R
100: PSDIN[2]: L
101: PSDIN[2]: R
110: PSDIN[3]: L
111: PSDIN[3]: R
3
R/W
SPDIN input loopback to PSDOUT[0] Left slot
1: SPDIN Right input
0: SPDIN Left input
Revision 2.4, May 28, 2002
4 - 37
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
Bit
Attribute
2:0
R/W
Revision 2.4, May 28, 2002
VT1712 - PCI Multi-Channel Audio Controller
Description
PSDIN[X] loopback to PSDOUT[0] Left slot
000: PSDIN[0]: L
001: PSDIN[0]: R
010: PSDIN[1]: L
011: PSDIN[1]: R
100: PSDIN[2]: L
101: PSDIN[2]: R
110: PSDIN[3]: L
111: PSDIN[3]: R
4 - 38
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
4.6.5 Multi-Track Digital Monitoring
The Envy24 integrates a 36-bit resolution digital hardware mixer. The width of the data path is strictly to ensure that
during processing of all the channels, under any condition, no resolution is lost. The dynamic range of the end user
system will be limited by the range of the physical output devices used. In order to maintain identical gain to the input
stream (i.e. 0dB), the resulting 24-bit is not msb-aligned to the 36-bit. The overflow bits correspond to the analog
distortion due to saturation. The user would need to reduce the overall attenuation of the inputs to avoid clipping.
Insertion of the digital mixer adds only a single sample cycle delay with respect to the original data. This extremely low
latency all digital mixer provides monitoring functionality and can replace a traditional external analog input mixer.
There are 20 independent audio data streams to mix and control the volume. The output destination of this mixer can be
the consumer AC ‘97 codec, an external DAC at PSDOUT[0] or SPDOUT or both simultaneously, as well as return to
the host on slots 11 and 12 (the last two) of DMA Channel-11. Refer to the registers MT30, MT32, MT34 and MT3Ch
in section 4.5.4 about audio data routing. Note that the consumer AC’97 path is limited to 48 KHz sampling rate
maximum and for sub-48 KHz sampling rates, Channel-A and B of the DirectSound accelerator are allocated for SRC
when the digital mixer return stream is at a sample rate other than 48 KHz. All other DirectSound streams operate
concurrently without alterations.
MT38: Left / Right Volume Control Data
Address Offset: 38 - 39h
Default Value: 0707h
Refer to MT3A register for the audio data channel selection.
Description
Bits
Attribute
15
R0b
-
14:8
R/W
Right Volume control. Same format as the in the left volume control.
7
R0b
-
6:0
R/W
Left volume control.
0000000: 0dB
0000001: -1.5dB (0.841395141)
0000010: -3.0dB (0.7079458)
0000011: -4.5dB (0.5956621)
....
0000111: -10.5 dB (default)
....
0011111: -46.5dB
....
0111111: -94.5dB
1000000: -96dB
....
1100000: -144dB (maximum attenuation)
1111111: mute
Revision 2.4, May 28, 2002
4 - 39
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
MT3A: Volume Control Stream Index
Address Offset: 3Ah
Default Value: 00h
Description
Bit
Attribute
7:6
R00b
-
5:0
R/W
Index to select stream:
00000: Playback stream 1 (Channel-10 slot 1)
00001: Playback stream 2 (Channel-10 slot 2)
00010: Playback stream 3 (Channel-10 slot 3)
00011: Playback stream 4 (Channel-10 slot 4)
00100: Playback stream 5 (Channel-10 slot 5)
00101: Playback stream 6 (Channel-10 slot 6)
00110: Playback stream 7 (Channel-10 slot 7)
00111: Playback stream 8 (Channel-10 slot 8)
01000: Playback stream 9 (Channel-10 slot 9, typ. S/PDIF Left output stream)
01001: Playback stream 10 (Channel-10 slot 10, typ. S/PDIF Right output stream)
01010: Record stream 1 (Channel-11 slot 1)
01011: Record stream 2 (Channel-11 slot 2)
01100: Record stream 3 (Channel-11 slot 3)
01101: Record stream 4 (Channel-11 slot 4)
01110: Record stream 5 (Channel-11 slot 5)
01111: Record stream 6 (Channel-11 slot 6)
10000: Record stream 7 (Channel-11 slot 7)
10001: Record stream 8 (Channel-11 slot 8)
10010: Record stream 9 (Channel-11 slot 9, typ. S/PDIF Left input stream)
10011: Record stream 10 (Channel-11 slot 10, typ. S/PDIF Right input stream)
others: ignored.
MT3B: Volume Control Rate
Address Offset: 3Bh
Default Value: 30h
Bits
Attribute
7:0
R/W
Description
Volume update rate control (sampling rate, PSYNC)
This register allows gradual change of the digital mixer volume setting. The value in MT3B specifies the
number of samples to elapse (in hex) between each 1.5dB increment/decrement in volume mixer. This gradual
volume update continues until the setting programmed into MT38 is reached. The appropriate value to program may vary, but 00 or 01h are good choices for most cases.
Revision 2.4, May 28, 2002
4 - 40
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
MT3C: Digital Mixer Monitor Routing Control
Address Offset: 3Ch
Default Value: 00h
Bits
Attribute
7:6
R0
0
R/W
Description
1: Route digital mixer output to the Consumer AC’97 path by allocating Channel-A and B.
Right Monitor Output
(routing selection via MT30, MT32, MT3C)
Left Monitor Output
(routing selection via MT30, MT32, MT3C)
Read peaks via MT3E, MT3F
Peak
Peak
24b
24b
Σ
Σ
36b
0dB
0dB
0dB
MT38
....
0dB
0dB
-144dB -144dB
Peak Peak
0dB
-144dB
-144dB
24b
24b
36b
0dB
MT39
....
MT38
....
-144dB
Peak
36b
36b
0dB
MT39
....
-144dB -144dB
24b
Peak
Peak
-144dB
24b
Peak Peak
Peak
slot 1..... slot 10slot 1..... slot 10
(Stream attenuator selection via MT3A)
DMA Channel-10
DMA Channel-11
(Playback)
(Record)
slot 1..... slot 10slot 1..... slot 10
(Stream attenuator selection via MT3A)
DMA Channel-10
DMA Channel-11
(Playback)
(Record)
Figure 4-7. Digital Mixer Functional Diagram
Revision 2.4, May 28, 2002
4 - 41
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
MT3E: Peak Meter Index
Address Offset: 3Eh
Default Value: 00h
Bits
Attribute
7:5
R000b
4:0
R/W
Description
Peak meter stream index
00000: Playback stream 1 (Channel-10 slot 1)
00001: Playback stream 2 (Channel-10 slot 2)
00010: Playback stream 3 (Channel-10 slot 3)
00011: Playback stream 4 (Channel-10 slot 4)
00100: Playback stream 5 (Channel-10 slot 5)
00101: Playback stream 6 (Channel-10 slot 6)
00110: Playback stream 7 (Channel-10 slot 7)
00111: Playback stream 8 (Channel-10 slot 8)
01000: Playback stream 9 (Channel-10 slot 9, typ. S/PDIF Left output stream)
01001: Playback stream 10 (Channel-10 slot 10, typ. S/PDIF Right output stream)
01010: Record stream 1 (Channel-11 slot 1)
01011: Record stream 2 (Channel-11 slot 2)
01100: Record stream 3 (Channel-11 slot 3)
01101: Record stream 4 (Channel-11 slot 4)
01110: Record stream 5 (Channel-11 slot 5)
01111: Record stream 6 (Channel-11 slot 6)
10000: Record stream 7 (Channel-11 slot 7)
10001: Record stream 8 (Channel-11 slot 8)
10010: Record stream 9 (Channel-11 slot 9, typ. S/PDIF Left input stream)
10011: Record stream 10 (Channel-11 slot 10, typ. S/PDIF Right input stream)
10100: Record stream 11 (Channel-11 slot 11, typ. digital mixer monitor Left output stream)
10101: Record stream 12 (Channel-11 slot 12, typ. digital mixer monitor Right output stream)
others: ignored.
MT3F: Peak Meter Data
Address Offset: 3Fh
Default Value: 00h
Bits
Attribute
7:0
R
Revision 2.4, May 28, 2002
Description
Peak data derived from the absolute value of 9 msb. 00h min - FFh max volume. Reading the register resets the
meter to 00h.
4 - 42
Hardware Interfaces & Interface Registers
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Electrical Specifications
5.1 Maximum Ratings
Table 5-1. Maximum Ratings
Parameter
Min
Storage Temperature
-55
Operating Ambient Temperature
DC Supply Voltage (Analog and Digital)
I/O Pin Voltage
Typ
Max
Unit
150
°C
0
25
70
°C
3.0
3.3
4.0
V
VDD
V
TBD
W
GND - 0.5
Power Dissipation
5.2 Electrical Specifications
Table 5-2. DC Characteristics
( TA=25°C, VDD = 3.3V ± 5%; GND = 0V; 50pF Load )
Symbol
Parameter
VIN
Input Voltage Range
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
Min
Typ
-0.3
Max
Unit
VDD+0.3
V
0.3 x VDD
V
0.4 x VDD
V
0.2 x VDD
0.5 x VDD
V
V
–
Input Leakage Current
-10
10
µA
–
Output Leakage Current
-10
10
µA
–
Output Buffer Drive Current
Revision 2.4, May 28, 2002
TBD
5-1
mA
Electrical Specifications
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Table 5-3. Power Consumption
( TA=25°C, VDD = 3.3V ± 5%; GND = 0V; 50pF Load )
Symbol
Parameter
Min
Typ
Max
Unit
IVDD
Supply Current: Power Up
110
mA
IVDD
Supply Current: Partial Power Up
TBD
mA
IVDD
Supply Current: Partial Power Down
TBD
mA
IVDD
Supply Current: Power Down
TBD
mA
5.3 AC Timing Characteristics
(Test Conditions: TA=25°C, VDD = 3.3V ± 5%; GND = 0V; 50pF Load)
Table 5-4. Cold Reset
Symbol
Parameter
Min
TRST_LOW
CRST#/PRST# Active Low Pulse Width
TRST2CLK
CRST#/PRST#
Startup Delay
Inactive
to
CBLK/PBCLK/SPSCLK
TRST_LOW
Typ
Max
Unit
1
µs
162.8
ns
TRST2CLK
xRST#
xxCLK
Figure 5-1. Cold Reset Timing
Revision 2.4, May 28, 2002
5-2
Electrical Specifications
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Table 5-5. Warm Reset
Symbol
Parameter
Min
TSYNC_HIGH
CSYNC/PSYNC Active High Pulse Width
TSYNC2CLK
CSYNC/PSYNC Inactive to CBLK/PBCLK Startup
Delay
Typ
Max
1.3
TSYNC_HIGH
Unit
µs
162.8
ns
TSYNC2CLK
xSYNC
xBCLK
Figure 5-2. Warm Reset Timing
Table 5-6. Slave Mode Master clock delay
Symbol
Parameter
TSPI2MCK
SPMCLKIN to PMCLK Delay
TSPI2SPO
SPMCLKIN to SPMCLKOUT Delay
Min
Typ
Max
Unit
4
ns
5.5
ns
SPMCLKIN
TSPI2MCK
PMCLK
SPMCLKOUT
TSPI2SPO
Figure 5-3. Master Clock Delay
Revision 2.4, May 28, 2002
5-3
Electrical Specifications
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Table 5-7. xBCLK / xxSYNC Timing
Symbol
TCLK_PERIOD
Parameter
Min
Typ
xBCLK Frequency
see Appendix
xBCLK Period
see Appendix
xBCLK Output Jitter
TBD
Max
Unit
MHz
ns
750
ps
TCLK_HIGH
xBCLK Pulse Width (high)
see Appendix
ns
TCLK_LOW
xBCLK Pulse Width (low)
see Appendix
ns
xBCLK Duty Cycle
see Appendix
%
xxSYNC Frequency
see Appendix
kHz
see Appendix
µs
TCLK_DC
TSYNC_PERIOD xxSYNC Period
TSYNC_HIGH
xxSYNC Pulse Width (high)
see Appendix
µs
TSYNC_LOW
xxSYNC Pulse Width (low)
see Appendix
µs
TCLK_HIGH
TCLK_LOW
xBCLK
TCLK_PERIOD
TSYNC_HIGH
TSYNC_LOW
xxSYNC
TSYNC_PERIOD
Figure 5-4. xBCLK to xxSYNC Timing
Revision 2.4, May 28, 2002
5-4
Electrical Specifications
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Table 5-8. Setup and Hold
Symbol
TSETUP1
Parameter
Min
xSDOUT Setup to falling edge of xBCLK
Typ
Max
Unit
15
ns
THOLD1
xSDOUT Hold from falling edge of xBCLK
5
ns
TSETUP2
xSYNC Setup to rising edge of xBCLK
15
ns
THOLD2
xSYNC Hold to rising edge of xBCLK
5
ns
Note:
SDATA_IN seup and hold calculations determined by AC’97 controller propagation delay.
TSETUP1
THOLD1
xBCLK
xSDIN,
xSDOUT
xSYNC
TSETUP2
THOLD2
Figure 5-5. Setup and Hold Time
Table 5-9. Rise and Fall Time
Symbol
Parameter
Min
Typ
Max
Unit
TRISE
xBCLK rise time
2
6
ns
TFALL
xBCLK fall time
2
6
ns
TRISE
xxSYNC rise time
2
6
ns
TFALL
xxSYNC fall time
2
6
ns
TRISE
xSDIN rise time
2
6
ns
TFALL
xSDIN fall time
2
6
ns
TRISE
xSDOUT rise time
2
6
ns
TFALL
xSDOUT fall time
2
6
ns
Revision 2.4, May 28, 2002
5-5
Electrical Specifications
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
BIT_CLK,
SYNC
SDATA_IN,
SDATA_OUT
TRISE
TFALL
Figure 5-6. Rise Time and Fall Time
Table 5-10. AC-Link Low Power Mode
Symbol
Parameter
TS2_PDOWN
End of Slot 2 to CBCLK/PBCLK to CSDIN/PSDIN low
Note:
Min
Typ
Max
Unit
1
µs
CBCLK/PBCLK not to scale.
xSYNC
Slot 1
Slot 2
xBCLK
TS2_PDOWN
xSDOUT
xSDIN
Figure 5-7. AC-Link Power Mode Timing
Revision 2.4, May 28, 2002
5-6
Electrical Specifications
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Mechanical Specifications
6.1 Thermal Specifications
Parameter
Min
Typ
Max
Unit
Thermal Resistenace θJA (Still Air)
TBD
°C/W
Junction Temperature
TBD
°C
Revision 2.4, May 28, 2002
6-1
Mechanical Specifications
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
6.2 Package Dimensions
A
B
Pin 1 Identifier
D C
J
E
I
F
H
G
Table 6-1. Mechanical Dimensions
Symbol
A
B
C
D
E
minimum
17.0
13.9
23.0
19.9
0°
maximum
17.4
14.1
23.4
20.1
7°
F
0.5
G
H
I
J
0.17
0.25
–
0.65
0.23
-
3.4
0.95
Note: Dimensions are in millimeters, unless otherwise stated.
Revision 2.4, May 28, 2002
6-2
Mechanical Specifications
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Appendix A
A.1 Appendix A
The following tables will help system designers and software developers correctly set the sampling rate and clock ratios.
To determine via software whether AC-link or I²S converters are used, read back PCI61[7]. Based on the outcome
either Table A-1 or Table A-2 should be used. To set the sampling rate, regardless of the converter type used, program
MT01. MT02 will have no effect in AC-link mode. MT02 will set I²S interface bpf, oversampling rate, master clock to
sampling rate ratio and similar characteristics. For a visual description of hardware settings refer to Figure 4-4-3 and
Figure 4-4-4 on page 27 and page 28 of chapter 4 respectively .
Table A-1. AC-Link Interface Parameters and Ratios (Pin 50 Floating / Pulled Up)
PSYNC (SR in kHz)
PMCLK/PSYNC
XINx/PMCLK
PBCLK / PSYNC (bpf)
96
-
-
-
48
512
1
256
24
512
2
256
12
512
4
256
32
512
1.5*
256
16
512
3*
256
8
512
6
256
9.6
512
5*
256
44.1
512
1
256
22.05
512
2
256
11.025
512
4
256
Note: When using AC’97 codecs, the XIN2 must have 22.5792 MHz (512*44.1 KHz) to be able to support the sampling rates at
44.1 KHz and submultiples. The dividers marked with * at sampling rates 32 / 16 / 9.6 KHz, will not have 50% duty cycle PMCLK.
Table A-2. I²S Interface Parameters and Ratios (Pin 50 Pulled Down)
PSYNC (SR in kHz)
PMCLK/PSYNC
XINx/PMCLK
PBCLK / PSYNC (bpf)
96
128 or 256
2 or 1
64
64
128
3*
64
48
128 or 256
4 or 2
64
24
128 or 256
8 or 4
64
12
128 or 256
16 or 8
64
32
128 or 256
6 or 3*
64
16
128 or 256
12or 6
64
Revision 2.4, May 28, 2002
A-1
Appendix A
Technologies, Inc.
We Connect
VT1712 - PCI Multi-Channel Audio Controller
Table A-2. I²S Interface Parameters and Ratios (Pin 50 Pulled Down)
PSYNC (SR in kHz)
PMCLK/PSYNC
XINx/PMCLK
PBCLK / PSYNC (bpf)
8
128 or 256
24 or 12
64
9.6
128 or 256
20 or 10
64
88.2
128 or 256
2 or 1
64
44.1
256 or 384
2 or 1
64 or 48
22.05
256 or 384
4 or 2
64 or 48
11.025
256 or 384
8 or 4
64 or 48
Note: Clock source either 22.5792 MHz for 512*44.1 KHz or 16.9344 MHz for 384*44.1
KHz, software controlled via PCI60[7-6]. For 512*48 KHz, the clock source is 24.576 MHz.
The divider marked with * like the one at 32 KHz sampling rate, will not have 50% duty cycle
PMCLK. See MT02 for I²S data format and clock ratios. 48 bpf is available for XIN2
originating clocks only.
Table A-3. S/PDIF Output I²S Interface Parameters and Ratios
SPSYNC (SR in kHz)
SPMCLKOUT/SPSYNC SPSCLK/SPSYNC (bpf)
96
128
64
48
128
64
44.1
128
64
32
128
64
Note: Refer to CS8402A, CS8404A transmitters
Table A-4. S/PDIF Input I²S Interface Parameters and Ratios
SPSYNC (SR in kHz)
SPMCLKIN/SPSYNC
SPSCLK/SPSYNC (bpf)
96
256
64
48
256
64
44.1
256
64
32
256
64
Note: Refer to CS8412, CS8414 receivers. To set the controller into slave
mode, set MT01[4]. When S/PDIF input is the master clock, 256x is the
maximum PMCLK. This input can be used to synchronize with external Super
Word Clock inputs. This can also be used to slave multiple PCI controllers in a
single workstation.
Revision 2.4, May 28, 2002
A-2
Appendix A