S6B33A2 128 RGB Segment & 129 Common Driver For 4,096 Color STN LCD Sep. 06. 2002. Ver. 1.3 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD S6B33A2 Specification Revision History Version 0.0 Content Original Date Oct. 2001 1. Page11 0.1 Added & Changed Test Pin 2. Page24 Deleted “Data Bus Mode Set” Instruction Deleted “Driving Current Mode & Bias Set” Instruction Deleted “Row Vector Mode Set” Instruction Added “DDRAM Burst Mode On/Off” Instruction 3. Page25 Deleted “Data Bus Mode Set” description 4. Page26 Reduced bus bandwidth of DIV(1) and DIV(2) 5. Page28 Deleted “Driving Current Mode and Bias Set” description 6. Page33 Deleted “Row Vector Mode Set” description Added “DDRAM Burst Mode On/Off” description 7. Page37 - Nov. 2001 Deleted “MDI” bit in “Entry Mode Set” parameters 8. Page49 - Modified the register list and parameters according to modification 0.2 - Page2 Deleted C24+, C24- pin in block diagram 2.Page 9 Deleted C24+, C24- pin in pin description 3.Page12 - Deleted “REG_ENB” pin - Deleted “TEST2”, “TEST3” pin 4.Page23 - Delete “REG_ENB” pin on figure20 5.Page25 Added “Red, Green and Blue Palette Set” instruction. 6.Page 28 Changed DCDC clock division ratio 7.Page 35 Added “GSM” bit for gray scale selection at “Gray Scale Mode Set” instruction Page 37 Added “Red, Green and Blue Palette Set” description Page38 Added “HL” bit at “Entry Mode Set” instruction Page 50 Modified the register list and parameters according to modification 11.Page 54 Changed Oscillator frequency tolerance and range 12.Page41,43,44,55,56 - The duty of partial mode1 is changed from 1/69 to 1/66 Dec. 2001 2 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD S6B33A2 Specification Revision History Version 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Content - Page4~9 Added key coordinates, pad dimension, configuration and coordinates 2. Page59 Added “the limitation of usage of analog circuit” in detail 3. Page65~66 - Added system application diagram 1. Page3 Deleted CK Pin 2. Page10 Modified pin description 3. Page16 - Collected the code of X,Y address 4. Page 50 - Described write/read data which is accessed by MCU I/F in 256 color mode 1. Page5 - Deleted *note about ILB, TOM align key - Page26, 50 - Added display format select command(60H/61H) 2. Page27 Added “DIV2” bit at “Oscillation Mode Set” instruction 3. Page66 - Add maximum rating voltage of capacitors - Page 26,35,36 - Delete Burst mode on/off instruction 2. Page 59,60 – Add MPU 68/80 Parallel I/F AC Timing 1. Page 65 - Add shot-key diode at application circuit 1. Page 26, 35, 51 - Add ROW Vector Mode Set Command 1. Page 65 - Add Values of Schottky barrier diode. 1. Page 30 - Corrected Miss-typing. 1. Page 53~61 - Filled TBD items 1. Page 18 - Delete “Block NO” on figure15. 2. Page 59-60 - Delete a word of “25°C” from condition item on table17. 3. Page 54 - Add DC Spec of DC2IN, VIN2 and VIN45 4. Page 55 - Add Current Measure data Date Jan. 2002 Jan. 2002 Jan.2002 Mar.2002 May.2002 May.2002 May.2002 Jun.2002 Jul.2002 Jul.2002 Sep.2002 3 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD CONTENTS INTRODUCTION ............................................................................................................................................ 1 FEATURES .................................................................................................................................................... 1 PAD CONFIGURATION ................................................................................................................................. 4 PIN CONFIGURATION................................................................................................................................... 6 PAD CENTER COORDINATES ...................................................................................................................... 7 FUNCTIONAL DESCRIPTION .......................................................................................................................13 MPU INTERFACE ..................................................................................................................................13 DISPLAY DATA RAM .............................................................................................................................16 INSTRUCTION PARAMETE R .................................................................................................................49 SPECIFICATIONS .........................................................................................................................................52 ABSOLUTE MAXIMUM RATINGS ...........................................................................................................52 OPERATING VOLTAGE .........................................................................................................................52 DC CHARACTERISTICS (1) ...................................................................................................................53 DC CHARACTERISTICS (2) ...................................................................................................................54 DC CHARACTERISTICS (3) ...................................................................................................................55 DC CHARACTERISTICS (4) ...................................................................................................................56 DC CHARACTERISTICS (5) ...................................................................................................................57 AC CHARACTERISTICS .........................................................................................................................58 4 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD INTRODUCTION S6B33A2 is a mid-display-size-compatible driver for liquid crystal dot matrix gray-scale graphic systems. With onchip RC oscillator circuit, the display-timing signal is generated without being sent from MPU. Also, it is capable of using 8bit/16bit data bus alternatively and operating with 68/80-series MPU in asynchronous. Due to the internal bitmap display RAM of 128 ×128 ×12-bit, S6B33A2 is capable of operating max. 128 RGB x 128 dot LCD panels in low-power consumption. Being the segment RGB 3-output, one pixel is 12-bit data and S6B33A2 can display 4,096 color. FEATURES Driver Output − 129 COM X 128 RGB SEG Gray Scale Function − − 4,096 color display of R: 16 gray scale, G: 16 gray scale, B: 16 gray scale 256 color display of R: 8 gray scale, G: 8 gray scale, B: 4 gray scale On-chip Display Data RAM − Capacity: 128 x 128 x 12 = 196,608 bits Display Mode − − − − Normal display mode: Entire duty displaying Partial display mode: Partial displaying Standby mode: Internal display clocks off Area scroll mode: Particular area scrolling Microprocessor Interface − − 8-bit/16 bit parallel bi-directional interface with 6800-series or 8080-series 3/4 Pin SPI (only write operation) On-chip Low Power Analog Circuit − − − − − − On-chip RC oscillator (Internal cap. & external resistor), external clock available Voltage converter Voltage regulator Voltage follower On-chip electronic contrast control (256 steps) Bias ratio: 1/6 Operating Voltage Range − − − − VDD : 1.8 to 3.3 [V] (without Internal Regulator), 2.4 to 3.3 [V] (With internal Regulator) VIN1: 2.4 to 3.6 [V] Display operating voltage(V1): 2.0 to 3.3 V LCD Operating Voltage Range : 20 V Low Power Consumption - 650 uA Typ. Package Type - COG 1 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Output Pad Pitch - 38um Min. 2 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD BLOCK DIAGRAM SEGA0 SEGA127 SEGB0 - - -SEGB127 COM0 - - - COM128 SEGC0 SEGC127 VDD VDD1 VSS VCC V1 VM V0 VEE SEG Driving Circuit COM Driving Circuit OSC5 VIN45 VOUT45 C11+ C11C12C12+ 384 129 CL FR 1536 VIN2 V1OUT Voltage Converter/ Voltage Regulator/ Voltage Follower Display data RAM 128 X 1536 I/O Buffer X - Address Control Circuit REG_OUT MPU System Control Circuit Power Regulator Circuit Instruction Decoder PM Bus Holder Y - Address Control Circuit -VR DC3IN C31+ C31+VR LCD System Control Circuit MPU INTERFACE DC2IN C21+ C21C22+ C22C23+ C23- CDIR Decoder Circuit VIN1 V1T INTRS VMOUT DC2OUT Oscillator Circuit OSC1 OSC2 OSC3 OSC4 /CS1 CS2 D/I /RD /WR MPU[1:0] PS /RST DB<15:0> Status Figure 1. Block Diagram 3 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD PAD CONFIGURATION 652 230 ....................... .. 653 229 Y (0,0) 704 X S6B33A2 178 ............ . 1 177 PAD : Bump Key : ILB Align Key : COG Align Key : COF Align Key : TOM Figure 2. S6B33A2 Chip Pad Configuration Table 1. S6B33A2 Pad Dimensions Item Pad No. Chip size - Pad pitch Bumped pad size Bumped pad height Size X Y 16670 2430 1 ~ 177 90 178 to 229, 230 to 652, 653 to 704 38 µm 1 ~ 177 70 70 178 to 229, , 653 to 704 170 23 230 to 652 23 170 All Pad Unit 17 4 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Figure 3. Bump, COG Align Key Coordinate 30µm 30µm 30µm 30µm 30µm 30µm 42µm 108µm 108µm 42µm 30µm 108µ m 108µm (7495,-725) 60µm 30µm 30µm 30µm (-7374,740) Figure 4. ILB Align Key Coordinate 50µm 42µ m 42µm (-7500,-785) (7340,665) 50µm 20µm (-7975,820) (7975,820) Figure 5. COF Align Key Coordinate 220um 220um (-6785, 545) (7120, 545) 580um (-7005, -35) Left (6900, -35) Right Figure 6. TOM Coordinate 5 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD PIN CONFIGURATION COM0 COM1 COM2 : : : : : : : : : : : : COM45 COM46 COM47 COM48 COM49 COM50 : : : COM60 COM61 COM62 S6B33A2 (Top View) SEGC0 SEGB0 SEGA0 SEGC1 SEGB1 SEGA1 SEGC2 SEGB2 SEGA2 : : : : : : : : : : : : : : : : : : : : : : : : : : SEGC125 SEGB125 SEGA125 SEGC126 SEGB126 SEGA126 SEGC127 SEGB127 SEGA127 : : : : : : : : : : : : COM65 COM64 COM63 COM110 COM109 108 COM128 COM127 COM126 : : : COM113 COM112 COM111 VOIN VCC VRP C31P C31M VEE VRN C24M C24P C23M C23P C22M C22P C21M C21P DC2IN DC2OUT VMIN VMOUT V1T V1OUT V1IN C12M C12P C11M C11P VOUT45 VIN45 VIN2 VIN1 VDD REG_OUT VDD1 OSC1 OSC2 OSC3 OSC4 OSC5 INTRS VSS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RDB WRB RS RSTB PM FR CL TEST0 TEST1 TEST2 TEST3 TEST4 CS2 CS1B CDIR MPU0 MPU1 PS VOIN Figure 7. S6B33A2 Chip Pin Configuration 6 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD PAD CENTER COORDINATES Table 2. Pad Center Coordinates [Unit: µm] NO NAME X Y NO NAME X Y NO NAME X Y NO NAME X Y 1 DUMMY -7920 -1100 61 VSS -2520 -1100 121 V1OUT 2880 -1100 181 COM<1> 8165 -955 2 DUMMY -7830 -1100 62 VSS -2430 -1100 122 V1OUT 2970 -1100 182 COM<2> 8165 -917 3 V0IN -7740 -1100 63 VSS -2340 -1100 123 V1T 3060 -1100 183 COM<3> 8165 -879 4 V0IN -7650 -1100 64 VDD -2250 -1100 124 VMOUT 3150 -1100 184 COM<4> 8165 -841 5 VSS -7560 -1100 65 INTRS -2160 -1100 125 VMOUT 3240 -1100 185 COM<5> 8165 -803 6 PS -7470 -1100 66 OSC5 -2070 -1100 126 VMOUT 3330 -1100 186 COM<6> 8165 -765 7 VDD -7380 -1100 67 VSS -1980 -1100 127 VMIN 3420 -1100 187 COM<7> 8165 -727 8 MPU<1> -7290 -1100 68 OSC4 -1890 -1100 128 VMIN 3510 -1100 188 COM<8> 8165 -689 9 VSS -7200 -1100 69 OSC3 -1800 -1100 129 VMIN 3600 -1100 189 COM<9> 8165 -651 10 MPU<0> -7110 -1100 70 OSC2 -1710 -1100 130 DC2OUT 3690 -1100 190 COM<10> 8165 -613 11 VDD -7020 -1100 71 OSC1 -1620 -1100 131 DC2OUT 3780 -1100 191 COM<11> 8165 -575 12 CDIR -6930 -1100 72 VDD1 -1530 -1100 132 DC2IN 3870 -1100 192 COM<12> 8165 -537 13 VSS -6840 -1100 73 VDD1 -1440 -1100 133 DC2IN 3960 -1100 193 COM<13> 8165 -499 14 CS1B -6750 -1100 74 VDD1 -1350 -1100 134 C21P 4050 -1100 194 COM<14> 8165 -461 15 CS2 -6660 -1100 75 VDD1 -1260 -1100 135 C21P 4140 -1100 195 COM<15> 8165 -423 16 TEST<4> -6570 -1100 76 VDD1 -1170 -1100 136 C21P 4230 -1100 196 COM<16> 8165 -385 17 TEST<3> -6480 -1100 77 VDD1 -1080 -1100 137 C21M 4320 -1100 197 COM<17> 8165 -347 18 TEST<2> -6390 -1100 78 REG_OUT -990 -1100 138 C21M 4410 -1100 198 COM<18> 8165 -309 19 TEST<1> -6300 -1100 79 REG_OUT -900 -1100 139 C21M 4500 -1100 199 COM<19> 8165 -271 20 TEST<0> -6210 -1100 80 REG_OUT -810 -1100 140 C22P 4590 -1100 200 COM<20> 8165 -233 21 VDD -6120 -1100 81 VDD -720 -1100 141 C22P 4680 -1100 201 COM<21> 8165 -195 22 CL -6030 -1100 82 VDD -630 -1100 142 C22P 4770 -1100 202 COM<22> 8165 -157 23 FR -5940 -1100 83 VDD -540 -1100 143 C22M 4860 -1100 203 COM<23> 8165 -119 24 PM -5850 -1100 84 VDD -450 -1100 144 C22M 4950 -1100 204 COM<24> 8165 -81 25 RSTB -5760 -1100 85 VDD -360 -1100 145 C22M 5040 -1100 205 COM<25> 8165 -43 26 RS -5670 -1100 86 VDD -270 -1100 146 C23P 5130 -1100 206 COM<26> 8165 -5 27 VSS -5580 -1100 87 VDD -180 -1100 147 C23P 5220 -1100 207 COM<27> 8165 33 28 WRB -5490 -1100 88 VIN1 -90 -1100 148 C23P 5310 -1100 208 COM<28> 8165 71 29 RDB -5400 -1100 89 VIN1 0 -1100 149 C23M 5400 -1100 209 COM<29> 8165 109 30 VDD -5310 -1100 90 VIN1 90 -1100 150 C23M 5490 -1100 210 COM<30> 8165 147 31 DB<0> -5220 -1100 91 VIN1 180 -1100 151 C23M 5580 -1100 211 COM<31> 8165 185 32 DB<1> -5130 -1100 92 VIN1 270 -1100 152 VRN 5670 -1100 212 COM<32> 8165 223 33 DB<2> -5040 -1100 93 VIN1 360 -1100 153 VRN 5760 -1100 213 COM<33> 8165 261 34 DB<3> -4950 -1100 94 VIN1 450 -1100 154 VRN 5850 -1100 214 COM<34> 8165 299 35 DB<4> -4860 -1100 95 VIN1 540 -1100 155 VEE 5940 -1100 215 COM<35> 8165 337 36 DB<5> -4770 -1100 96 VIN1 630 -1100 156 VEE 6030 -1100 216 COM<36> 8165 375 37 DB<6> -4680 -1100 97 VIN1 720 -1100 157 VEE 6120 -1100 217 COM<37> 8165 413 38 DB<7> -4590 -1100 98 VIN1 810 -1100 158 VEE 6210 -1100 218 COM<38> 8165 451 39 DB<8> -4500 -1100 99 VIN2 900 -1100 159 DUMMY 6300 -1100 219 COM<39> 8165 489 40 DB<9> -4410 -1100 100 VIN2 990 -1100 160 C31M 6390 -1100 220 COM<40> 8165 527 41 DB<10> -4320 -1100 101 VIN2 1080 -1100 161 C31M 6480 -1100 221 COM<41> 8165 565 42 DB<11> -4230 -1100 102 VIN2 1170 -1100 162 C31M 6570 -1100 222 COM<42> 8165 603 43 DB<12> -4140 -1100 103 VIN45 1260 -1100 163 DUMMY 6660 -1100 223 COM<43> 8165 641 44 DB<13> -4050 -1100 104 VIN45 1350 -1100 164 C31P 6750 -1100 224 COM<44> 8165 679 45 DB<14> -3960 -1100 105 VOUT45 1440 -1100 165 C31P 6840 -1100 225 COM<45> 8165 717 46 DB<15> -3870 -1100 106 VOUT45 1530 -1100 166 C31P 6930 -1100 226 COM<46> 8165 755 47 VSS -3780 -1100 107 C11P 1620 -1100 167 DUMMY 7020 -1100 227 COM<47> 8165 793 48 VSS -3690 -1100 108 C11P 1710 -1100 168 VRP 7110 -1100 228 DUMMY 8165 831 49 VSS -3600 -1100 109 C11P 1800 -1100 169 VRP 7200 -1100 229 DUMMY 8165 869 50 VSS -3510 -1100 110 C11M 1890 -1100 170 VCC 7290 -1100 230 DUMMY 8018 1045 51 VSS -3420 -1100 111 C11M 1980 -1100 171 VCC 7380 -1100 231 DUMMY 7980 1045 52 VSS -3330 -1100 112 C11M 2070 -1100 172 DUMMY 7470 -1100 232 COM<48> 7942 1045 53 VSS -3240 -1100 113 C12P 2160 -1100 173 VSS 7560 -1100 233 COM<49> 7904 1045 54 VSS -3150 -1100 114 C12P 2250 -1100 174 V0IN 7650 -1100 234 COM<50> 7866 1045 55 VSS -3060 -1100 115 C12P 2340 -1100 175 V0IN 7740 -1100 235 COM<51> 7828 1045 56 VSS -2970 -1100 116 C12M 2430 -1100 176 DUMMY 7830 -1100 236 COM<52> 7790 1045 57 VSS -2880 -1100 117 C12M 2520 -1100 177 DUMMY 7920 -1100 237 COM<53> 7752 1045 58 VSS -2790 -1100 118 C12M 2610 -1100 178 DUMMY 8165 -1069 238 COM<54> 7714 1045 59 VSS -2700 -1100 119 V1IN 2700 -1100 179 DUMMY 8165 -1031 239 COM<55> 7676 1045 60 VSS -2610 -1100 120 V1IN 2790 -1100 180 COM<0> 8165 -993 240 COM<56> 7638 1045 7 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Table 2. Pad Center Coordinates (Continued) [Unit: µm] X Y NO X Y NO X Y NO 241 NO COM<57> NAME 7600 1045 301 SEGA<17> NAME 5320 1045 361 SEGA<37> NAME 3040 1045 421 SEGA<57> NAME X 760 Y 1045 242 243 COM<58> COM<59> 7562 7524 1045 1045 302 303 SEGC<18> SEGB<18> 5282 5244 1045 1045 362 363 SEGC<38> SEGB<38> 3002 2964 1045 1045 422 423 SEGC<58> SEGB<58> 722 684 1045 1045 244 245 COM<60> COM<61> 7486 7448 1045 1045 304 305 SEGA<18> SEGC<19> 5206 5168 1045 1045 364 365 SEGA<38> SEGC<39> 2926 2888 1045 1045 424 425 SEGA<58> SEGC<59> 646 608 1045 1045 246 247 COM<62> DUMMY 7410 7372 1045 1045 306 307 SEGB<19> SEGA<19> 5130 5092 1045 1045 366 367 SEGB<39> SEGA<39> 2850 2812 1045 1045 426 427 SEGB<59> SEGA<59> 570 532 1045 1045 248 SEGC<0> 7334 1045 308 SEGC<20> 5054 1045 368 SEGC<40> 2774 1045 428 SEGC<60> 494 1045 249 250 SEGB<0> SEGA<0> 7296 7258 1045 1045 309 310 SEGB<20> SEGA<20> 5016 4978 1045 1045 369 370 SEGB<40> SEGA<40> 2736 2698 1045 1045 429 430 SEGB<60> SEGA<60> 456 418 1045 1045 251 252 SEGC<1> SEGB<1> 7220 7182 1045 1045 311 312 SEGC<21> SEGB<21> 4940 4902 1045 1045 371 372 SEGC<41> SEGB<41> 2660 2622 1045 1045 431 432 SEGC<61> SEGB<61> 380 342 1045 1045 253 254 SEGA<1> SEGC<2> 7144 7106 1045 1045 313 314 SEGA<21> SEGC<22> 4864 4826 1045 1045 373 374 SEGA<41> SEGC<42> 2584 2546 1045 1045 433 434 SEGA<61> SEGC<62> 304 266 1045 1045 255 SEGB<2> 7068 1045 315 SEGB<22> 4788 1045 375 SEGB<42> 2508 1045 435 SEGB<62> 228 1045 256 257 SEGA<2> SEGC<3> 7030 6992 1045 1045 316 317 SEGA<22> SEGC<23> 4750 4712 1045 1045 376 377 SEGA<42> SEGC<43> 2470 2432 1045 1045 436 437 SEGA<62> SEGC<63> 190 152 1045 1045 258 259 SEGB<3> SEGA<3> 6954 6916 1045 1045 318 319 SEGB<23> SEGA<23> 4674 4636 1045 1045 378 379 SEGB<43> SEGA<43> 2394 2356 1045 1045 438 439 SEGB<63> SEGA<63> 114 76 1045 1045 260 261 SEGC<4> SEGB<4> 6878 6840 1045 1045 320 321 SEGC<24> SEGB<24> 4598 4560 1045 1045 380 381 SEGC<44> SEGB<44> 2318 2280 1045 1045 440 441 SEGC<64> SEGB<64> 38 0 1045 1045 262 SEGA<4> 6802 1045 322 SEGA<24> 4522 1045 382 SEGA<44> 2242 1045 442 SEGA<64> -38 1045 263 264 SEGC<5> SEGB<5> 6764 6726 1045 1045 323 324 SEGC<25> SEGB<25> 4484 4446 1045 1045 383 384 SEGC<45> SEGB<45> 2204 2166 1045 1045 443 444 SEGC<65> SEGB<65> -76 -114 1045 1045 265 266 SEGA<5> SEGC<6> 6688 6650 1045 1045 325 326 SEGA<25> SEGC<26> 4408 4370 1045 1045 385 386 SEGA<45> SEGC<46> 2128 2090 1045 1045 445 446 SEGA<65> SEGC<66> -152 -190 1045 1045 267 268 SEGB<6> SEGA<6> 6612 6574 1045 1045 327 328 SEGB<26> SEGA<26> 4332 4294 1045 1045 387 388 SEGB<46> SEGA<46> 2052 2014 1045 1045 447 448 SEGB<66> SEGA<66> -228 -266 1045 1045 269 SEGC<7> 6536 1045 329 SEGC<27> 4256 1045 389 SEGC<47> 1976 1045 449 SEGC<67> -304 1045 270 271 SEGB<7> SEGA<7> 6498 6460 1045 1045 330 331 SEGB<27> SEGA<27> 4218 4180 1045 1045 390 391 SEGB<47> SEGA<47> 1938 1900 1045 1045 450 451 SEGB<67> SEGA<67> -342 -380 1045 1045 272 273 SEGC<8> SEGB<8> 6422 6384 1045 1045 332 333 SEGC<28> SEGB<28> 4142 4104 1045 1045 392 393 SEGC<48> SEGB<48> 1862 1824 1045 1045 452 453 SEGC<68> SEGB<68> -418 -456 1045 1045 274 275 SEGA<8> SEGC<9> 6346 6308 1045 1045 334 335 SEGA<28> SEGC<29> 4066 4028 1045 1045 394 395 SEGA<48> SEGC<49> 1786 1748 1045 1045 454 455 SEGA<68> SEGC<69> -494 -532 1045 1045 276 SEGB<9> 6270 1045 336 SEGB<29> 3990 1045 396 SEGB<49> 1710 1045 456 SEGB<69> -570 1045 277 278 SEGA<9> SEGC<10> 6232 6194 1045 1045 337 338 SEGA<29> SEGC<30> 3952 3914 1045 1045 397 398 SEGA<49> SEGC<50> 1672 1634 1045 1045 457 458 SEGA<69> SEGC<70> -608 -646 1045 1045 279 280 SEGB<10> SEGA<10> 6156 6118 1045 1045 339 340 SEGB<30> SEGA<30> 3876 3838 1045 1045 399 400 SEGB<50> SEGA<50> 1596 1558 1045 1045 459 460 SEGB<70> SEGA<70> -684 -722 1045 1045 281 282 SEGC<11> SEGB<11> 6080 6042 1045 1045 341 342 SEGC<31> SEGB<31> 3800 3762 1045 1045 401 402 SEGC<51> SEGB<51> 1520 1482 1045 1045 461 462 SEGC<71> SEGB<71> -760 -798 1045 1045 283 SEGA<11> 6004 1045 343 SEGA<31> 3724 1045 403 SEGA<51> 1444 1045 463 SEGA<71> -836 1045 284 285 SEGC<12> SEGB<12> 5966 5928 1045 1045 344 345 SEGC<32> SEGB<32> 3686 3648 1045 1045 404 405 SEGC<52> SEGB<52> 1406 1368 1045 1045 464 465 SEGC<72> SEGB<72> -874 -912 1045 1045 286 287 SEGA<12> SEGC<13> 5890 5852 1045 1045 346 347 SEGA<32> SEGC<33> 3610 3572 1045 1045 406 407 SEGA<52> SEGC<53> 1330 1292 1045 1045 466 467 SEGA<72> SEGC<73> -950 -988 1045 1045 288 289 SEGB<13> SEGA<13> 5814 5776 1045 1045 348 349 SEGB<33> SEGA<33> 3534 3496 1045 1045 408 409 SEGB<53> SEGA<53> 1254 1216 1045 1045 468 469 SEGB<73> SEGA<73> -1026 -1064 1045 1045 290 SEGC<14> 5738 1045 350 SEGC<34> 3458 1045 410 SEGC<54> 1178 1045 470 SEGC<74> -1102 1045 291 292 SEGB<14> SEGA<14> 5700 5662 1045 1045 351 352 SEGB<34> SEGA<34> 3420 3382 1045 1045 411 412 SEGB<54> SEGA<54> 1140 1102 1045 1045 471 472 SEGB<74> SEGA<74> -1140 -1178 1045 1045 293 294 SEGC<15> SEGB<15> 5624 5586 1045 1045 353 354 SEGC<35> SEGB<35> 3344 3306 1045 1045 413 414 SEGC<55> SEGB<55> 1064 1026 1045 1045 473 474 SEGC<75> SEGB<75> -1216 -1254 1045 1045 295 296 SEGA<15> SEGC<16> 5548 5510 1045 1045 355 356 SEGA<35> SEGC<36> 3268 3230 1045 1045 415 416 SEGA<55> SEGC<56> 988 950 1045 1045 475 476 SEGA<75> SEGC<76> -1292 -1330 1045 1045 297 SEGB<16> 5472 1045 357 SEGB<36> 3192 1045 417 SEGB<56> 912 1045 477 SEGB<76> -1368 1045 298 299 300 SEGA<16> SEGC<17> SEGB<17> 5434 5396 5358 1045 1045 1045 358 359 360 SEGA<36> SEGC<37> SEGB<37> 3154 3116 3078 1045 1045 1045 418 419 420 SEGA<56> SEGC<57> SEGB<57> 874 836 798 1045 1045 1045 478 479 480 SEGA<76> SEGC<77> SEGB<77> -1406 -1444 -1482 1045 1045 1045 8 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Table 2. Pad Center Coordinates (Continued) [Unit: µm] Y NO Y NO NAME Y NO 481 482 NO SEGA<77> SEGC<78> NAME -1520 -1558 X 1045 1045 541 542 SEGA<97> SEGC<98> NAME -3800 -3838 X 1045 1045 601 602 SEGA<117> SEGC<118> -6080 -6118 X 1045 1045 661 662 COM<104> COM<103> NAME -8165 -8165 X Y 565 527 483 SEGB<78> -1596 1045 543 SEGB<98> -3876 1045 603 SEGB<118> -6156 1045 663 COM<102> -8165 489 484 485 SEGA<78> SEGC<79> -1634 -1672 1045 1045 544 545 SEGA<98> SEGC<99> -3914 -3952 1045 1045 604 605 SEGA<118> SEGC<119> -6194 -6232 1045 1045 664 665 COM<101> COM<100> -8165 -8165 451 413 486 487 SEGB<79> SEGA<79> -1710 -1748 1045 1045 546 547 SEGB<99> SEGA<99> -3990 -4028 1045 1045 606 607 SEGB<119> SEGA<119> -6270 -6308 1045 1045 666 667 COM<99> COM<98> -8165 -8165 375 337 488 489 SEGC<80> SEGB<80> -1786 -1824 1045 1045 548 549 SEGC<100> SEGB<100> -4066 -4104 1045 1045 608 609 SEGC<120> SEGB<120> -6346 -6384 1045 1045 668 669 COM<97> COM<96> -8165 -8165 299 261 490 491 SEGA<80> SEGC<81> -1862 -1900 1045 1045 550 551 SEGA<100> SEGC<101> -4142 -4180 1045 1045 610 611 SEGA<120> SEGC<121> -6422 -6460 1045 1045 670 671 COM<95> COM<94> -8165 -8165 223 185 492 493 SEGB<81> SEGA<81> -1938 -1976 1045 1045 552 553 SEGB<101> SEGA<101> -4218 -4256 1045 1045 612 613 SEGB<121> SEGA<121> -6498 -6536 1045 1045 672 673 COM<93> COM<92> -8165 -8165 147 109 494 495 SEGC<82> SEGB<82> -2014 -2052 1045 1045 554 555 SEGC<102> SEGB<102> -4294 -4332 1045 1045 614 615 SEGC<122> SEGB<122> -6574 -6612 1045 1045 674 675 COM<91> COM<90> -8165 -8165 71 33 496 SEGA<82> -2090 1045 556 SEGA<102> -4370 1045 616 SEGA<122> -6650 1045 676 COM<89> -8165 -5 497 498 SEGC<83> SEGB<83> -2128 -2166 1045 1045 557 558 SEGC<103> SEGB<103> -4408 -4446 1045 1045 617 618 SEGC<123> SEGB<123> -6688 -6726 1045 1045 677 678 COM<88> COM<87> -8165 -8165 -43 -81 499 500 SEGA<83> SEGC<84> -2204 -2242 1045 1045 559 560 SEGA<103> SEGC<104> -4484 -4522 1045 1045 619 620 SEGA<123> SEGC<124> -6764 -6802 1045 1045 679 680 COM<86> COM<85> -8165 -8165 -119 -157 501 502 SEGB<84> SEGA<84> -2280 -2318 1045 1045 561 562 SEGB<104> SEGA<104> -4560 -4598 1045 1045 621 622 SEGB<124> SEGA<124> -6840 -6878 1045 1045 681 682 COM<84> COM<83> -8165 -8165 -195 -233 503 504 SEGC<85> SEGB<85> -2356 -2394 1045 1045 563 564 SEGC<105> SEGB<105> -4636 -4674 1045 1045 623 624 SEGC<125> SEGB<125> -6916 -6954 1045 1045 683 684 COM<82> COM<81> -8165 -8165 -271 -309 505 506 SEGA<85> SEGC<86> -2432 -2470 1045 1045 565 566 SEGA<105> SEGC<106> -4712 -4750 1045 1045 625 626 SEGA<125> SEGC<126> -6992 -7030 1045 1045 685 686 COM<80> COM<79> -8165 -8165 -347 -385 507 508 SEGB<86> SEGA<86> -2508 -2546 1045 1045 567 568 SEGB<106> SEGA<106> -4788 -4826 1045 1045 627 628 SEGB<126> SEGA<126> -7068 -7106 1045 1045 687 688 COM<78> COM<77> -8165 -8165 -423 -461 509 SEGC<87> -2584 1045 569 SEGC<107> -4864 1045 629 SEGC<127> -7144 1045 689 COM<76> -8165 -499 510 511 SEGB<87> SEGA<87> -2622 -2660 1045 1045 570 571 SEGB<107> SEGA<107> -4902 -4940 1045 1045 630 631 SEGB<127> SEGA<127> -7182 -7220 1045 1045 690 691 COM<75> COM<74> -8165 -8165 -537 -575 512 513 SEGC<88> SEGB<88> -2698 -2736 1045 1045 572 573 SEGC<108> SEGB<108> -4978 -5016 1045 1045 632 633 DUMMY COM<128> -7258 -7296 1045 1045 692 693 COM<73> COM<72> -8165 -8165 -613 -651 514 515 SEGA<88> SEGC<89> -2774 -2812 1045 1045 574 575 SEGA<108> SEGC<109> -5054 -5092 1045 1045 634 635 COM<127> COM<126> -7334 -7372 1045 1045 694 695 COM<71> COM<70> -8165 -8165 -689 -727 516 517 SEGB<89> SEGA<89> -2850 -2888 1045 1045 576 577 SEGB<109> SEGA<109> -5130 -5168 1045 1045 636 637 COM<125> COM<124> -7410 -7448 1045 1045 696 697 COM<69> COM<68> -8165 -8165 -765 -803 518 519 SEGC<90> SEGB<90> -2926 -2964 1045 1045 578 579 SEGC<110> SEGB<110> -5206 -5244 1045 1045 638 639 COM<123> COM<122> -7486 -7524 1045 1045 698 699 COM<67> COM<66> -8165 -8165 -841 -879 520 521 SEGA<90> SEGC<91> -3002 -3040 1045 1045 580 581 SEGA<110> SEGC<111> -5282 -5320 1045 1045 640 641 COM<121> COM<120> -7562 -7600 1045 1045 700 701 COM<65> COM<64> -8165 -8165 -917 -955 522 SEGB<91> -3078 1045 582 SEGB<111> -5358 1045 642 COM<119> -7638 1045 702 COM<63> -8165 -993 523 524 SEGA<91> SEGC<92> -3116 -3154 1045 1045 583 584 SEGA<111> SEGC<112> -5396 -5434 1045 1045 643 644 COM<118> COM<117> -7676 -7714 1045 1045 703 704 DUMMY DUMMY -8165 -8165 -1031 -1069 525 526 SEGB<92> SEGA<92> -3192 -3230 1045 1045 585 586 SEGB<112> SEGA<112> -5472 -5510 1045 1045 645 646 COM<116> COM<115> -7752 -7790 1045 1045 527 528 SEGC<93> SEGB<93> -3268 -3306 1045 1045 587 588 SEGC<113> SEGB<113> -5548 -5586 1045 1045 647 648 COM<114> COM<113> -7828 -7866 1045 1045 529 530 SEGA<93> SEGC<94> -3344 -3382 1045 1045 589 590 SEGA<113> SEGC<114> -5624 -5662 1045 1045 649 650 COM<112> COM<111> -7904 -7942 1045 1045 531 532 SEGB<94> SEGA<94> -3420 -3458 1045 1045 591 592 SEGB<114> SEGA<114> -5700 -5738 1045 1045 651 652 DUMMY DUMMY -7980 -8018 1045 1045 533 534 SEGC<95> SEGB<95> -3496 -3534 1045 1045 593 594 SEGC<115> SEGB<115> -5776 -5814 1045 1045 653 654 DUMMY DUMMY -8165 -8165 869 831 535 SEGA<95> -3572 1045 595 SEGA<115> -5852 1045 655 COM<110> -8165 793 536 537 SEGC<96> SEGB<96> -3610 -3648 1045 1045 596 597 SEGC<116> SEGB<116> -5890 -5928 1045 1045 656 657 COM<109> COM<108> -8165 -8165 755 717 538 539 540 SEGA<96> SEGC<97> SEGB<97> -3686 -3724 -3762 1045 1045 1045 598 599 600 SEGA<116> SEGC<117> SEGB<117> -5966 -6004 -6042 1045 1045 1045 658 659 660 COM<107> COM<106> COM<105> -8165 -8165 -8165 679 641 603 9 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD PIN DESCRIPTION Table 3. Power Supply Pins Name I/O VDD Supply VDD3R Supply VDD1 Supply VSS,VSSA VSSB,VSSO VCC GND Description Power supply(Logic) Internal regulator power supply This pin is connected to VDD. Regulated power supply input pin for internal digital and DDRAM block. This pin is connected to REG_OUT outside the chip with stabilization capacitor. When the internal regulator is not used, VDD1 should be tied to VDD directly. Ground I LCD common high selected driving voltage input pin V1IN I LCD segment high selected driving voltage input pin VMIN I LCD common/segment non-selected driving voltage input pin V0IN I LCD segment low selected driving voltage input pin VEE,VEES I LCD common low selected driving voltage input pin The relationship between VCC, V1, VM, V0 and VEE: VCC > V1 > VM > V0(=VSS) > VEE (V1 – VM = VM – V0, VCC –VM = VM – VEE) VIN1,VIN1A I Power supply for 1’st booster circuit and VM amp VIN2 I Power supply for 2’nd booster circuit VOUT45 O 1’st booster output pin VIN45 I Power supply for V1. Connect to VOUT45 or VIN1 C11+ C11C12+ C12- O External capacitor connection pins used for 1’st booster circuit V1OUT O LCD segment high driving voltage output pin V1T I INTRS I Thermistor resistor connection pin External resister select pin for temperature compensation circuit – INTRS = L : External resistor mode, INTRS = H : Internal resistor mode VMOUT O LCD common/segment non-selected driving voltage output pin DC2OUT O Power output pin for 2’nd booster input DC2IN I Power supply for 2’nd booster. Connect to DC2OUT pin C21+ C21C22+ C22C23+ C23- O External capacitor connection pins used for 2’nd booster circuit -VR O LCD common low selected driving voltage output pin C31+ C31- O External capacitor connection pins used for 3’rd booster circuit +VR O LCD common high selected driving voltage output pin 10 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Table 4. MPU Interface Pins Name I/O /RST I Description Reset input pin. When /RST is “L”, initialization is executed. MPU interface select pin PS MPU[1:0] /CS1 CS2 D/I I PS MPU[1] MPU[0] Description H L L 8080-series 8bit interface H L H 8080-series 16bit interface H H L 6800-series 8bit interface H H H 6800-series 16bit interface L L X 3 pin SPI(Write only) L H X 4 pin SPI(Write only) I Chip select input pins Data / instruction I/O is enabled only when /CS1 is “L” and CS2 is “H”. When chip select is non-active, DB0 to DB15 may be high impedance. I Data / Instruction select input pin − D/I = “H”: DB0 to DB15 are display data − D/I = “L”: DB0 to DB7 are instruction data Read / Write execution control pin /WR (R/W) I PS MPU MPU Type /WR Description H H 6800-series R/W Read/Write control input pin − R/W = “H”: read − R/W = “L”: write H L 8080-series /WR Write enable clock input pin The data on DB0 to DB15 are latched at the rising edge of the /WR signal. Read / Write execution control pin MPU[1] /RD (E) I DB[15:8] DB[7]/SDI DB[6]/SCL DB[5:0] I/O CDIR I MPU type /RD H 6800series E L 8080series /RD Description Read / Write control input pin − R/W = “H”: When E is “H”, DB0 to DB15 are in an output status. − R/W = “L”: The data on DB0 to DB15 are latched at the falling edge of the E signal. Read enable clock input pin When /RD is “L”, DB0 to DB15 are in an output status. -DB[15:0]: 16-bit bi-directional data bus. -SDI: Serial data input pin. The data is latched at the rising edge of SCL. -SCL: Serial clock input pin. Common direction select pin. 11 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Table 5. Oscillator and Power Regulator Pins Name I/O OSC1 OSC2 OSC3 OSC4 O OSC5 I REG_OUT O Description CR oscillator output pin When the internal CR oscillator is used, connect to OSC1, OSC3 through a resistor. OSC1 – OSC2: Using in normal display mode, partial display mode 0 OSC3 – OSC4: Using in partial display mode 1 When an external oscillator is used, OSC1 pin is connected to VDD or VSS. External clock input pin When an external input is used, it is input to this pin. But the internal oscillator is used, this pin is connected to VDD or VSS. Internal voltage regulator output pin The regulator output port from this pin is used as a power supplier for an internal digital block via VDD1 pins. Table 6. Timing signal Pins for monitoring Name I/O Description CL O Shift clock output pin PM O Field delimiter output pin FR O Liquid crystal alternating current output pin Table 7. LCD driver output pins Name I/O Description SEGA0 to 127 O LCD driving segment output (Red or Blue) SEGB0 to 127 O LCD driving segment output (Green) SEGC0 to127 O LCD driving segment output (Blue or Red) COM0 to 128 O LCD common outputs Table 8. Test pins Name I/O TEST [4:0] I Description Don’t use these pins. IC maker’s test pins. Fix “High” in normal mode. 12 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD FUNCTIONAL DESCRIPTION MPU INTERFACE Chip Select Input There are /CS1 and CS2 pins for chip selection. The S6B33A2 can interface with an MPU only when /CS1 is “L” and CS2 is “H”. When these pins are set to any other combination, D/I, /RD, and /WR inputs are disabled and DB0 to DB15 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel/Serial Interface The S6B33A2 has four types of interface with an MPU, which are two serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in Table9. Table 9. Parallel / Serial Interface Mode. PS MPU[1] /CS1 CS2 MPU bus type L 8080-Series MPU H /CS1 CS2 H 6800-Series MPU L L /CS1 H 3–Pin SPI CS2 4-Pin SPI Parallel Interface (PS=”H”) The 8-bit/16-bit bi-directional data bus is used in parallel interface. The type of MPU is selected by MPU[1] and the mode of data-bus is controlled by MPU[0] as shown in below. In accessing internal registers (D/I = “L”), only DB[7:0] are valid. Table 10. Microprocessor Selection for Parallel Int erface MPU[1] L H MPU[0] L H L H /CS1 CS2 /RD /WR /CS1 CS2 E R/W /CS1 CS2 /RD /WR Data Bus DB[7:0] DB[15:0] DB[7:0] DB[15:0] MPU bus type 8080-series MPU 6800-series MPU Table 11. Parallel Data Transfer 6800-series 8080-series D/I Description /RD /WR /RD /WR H H H L H Read display data H H L H L Write display data L H H L H Read out internal status register L H L H L Write instruction data 13 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD /CS1 CS2 D/I R/W E DB Command Write Data Write Status Read Data Read Figure 8. 6800-Series MPU Interface protocol (MPU[1]=”H”) /CS1 CS2 D/I /WR /RD DB Command Write Figure 9. Data Write Status Read Data Read 8080-Series MPU Interface Protocol (MPU[1]=”L”) Serial Interface(PS=”L”) Communication with the microprocessor occurs via a clock-synchronized serial peripheral interface when PS is low. When using the serial interface, read operations are not allowed. When the chip select inputs are valid (/CS1 = “L” & CS2 = “H”), the serial data is sent most significant bit first on the rising edge of a serial clock going into DB6 and processed as 8 bit parallel data on the eighth clock. Since the clock signal is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. And Invalid, the internal shift register and the counter are reset. The serial interface type is selected by setting PS as shown in Table12. 14 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Table 12. Microprocessor Selection for Serial Interface PS MPU[1] /CS1 CS2 D/I L /CS1 CS2 D/I H /CS1 CS2 S/W L Serial Data Serial Clock DB[7] DB[6] SPI Mode 3-Pin 4-Pin 3-Pin SPI Interface (PS = “L” & MPU[1] = “L”) In 3-Pin SPI Interface mode, the pre-defined instruction called Display Data Length is used to indicate whether serial data input is display or instruction data instead of D/I pin. The data is handled as instruction data until the Display Data Length instruction is issued. This Display Data Length instruction consists of three bytes instruction. The first byte instruction enables the next two instructions to be valid, and the data of the next two bytes indicate that a specified number of display data bytes(1 to 65536) are to be transmitted. For details, refer the Figure 8. Chip Select /CS1 = L, CS2 = H 1 2 23 24 1 2 79 80 SCL(DB6) 2 bytes SDI(DB7) Internal D/I 9 bytes 11111100 00000000 00001001 DDL_SET DDL_H = 0 DDL_L = 9 (Initial : 80h,00h) = 32,768 9 bytes display data User's display data (Initial 50688 bytes) Figure 10. 3-Pin SPI Timing (D/I is not used) 4-Pin Serial Interface (PS=”L” & MPU[1]=”H”) In 4-pin SPI interface mode, D/I pin is used for indicating whether serial data input is display or instruction data. Data is display data when D/I is high and instruction data when D/I is low. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. Chip Select /CS1=L, CS2=H l SID (DB7) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB7 SCL(DB6) D/I Figure 11. 4-Pin Serial Interface Timing 15 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DISPLAY DATA RAM The on-chip display data RAM of S6B33A2 is a static RAM that is stored the data for the display. It is a 1,536x 128 structure. It is controlled by 2 addresses, X and Y. And, RAM area selection and automatic address count up functions are accomplished by the internal instructions. DDRAM Address Area Selection A part of DDRAM address area of S6B33A2 can be accessed by X and Y address area settings. After setting RAM area, the addresses become the start address. Y-address area X-address area Figure 12. DDRAM Address Area Table 13. X address Control DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 0 1 0 0 0 1 0 P1 0 X start address set(Initial Status = 00H) P2 X end address set(Initial Status = 7FH) Table 14. Y address Control DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 0 1 1 0 0 1 1 P1 0 Y start address set (Initial status = 00H) P2 0 Y end address set (Initial status =7FH) 16 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD RAM Addressing Count up By selecting the X address and Y address area by the internal instructions, the address counts up from its start address to end address after data access operation. When one address is equal to the end address, it returns to the start address. At this time, the other address is increased by 1. Y address count mode (Y address = 00h to7Fh, X address = 00h to 7Fh, 16 bit access mode) Y-address 00h 01h X-address 02h 03h 7Fh 00 01 02 03 04 05 06 07 08 0 128 1 2 3 4 5 6 7 8 7Fh 127 255 256 384 383 511 16256 16383 Figure 13. Y address count mode X address count mode (Y address =00h to 7Fh, X address = 00h to 7Fh, 16 bit access mode) Y-address 00h 01h 02h 03h 04h 05h 06h 07h 08h 0 128 256 384 512 640 768 896 1024 1 2 3 7Fh 16256 7Fh 127 255 383 511 639 767 895 1023 1151 16383 00h 01h X-address 02h 03h Figure 14. X address count mode 17 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD YA Address XA Address 00H 01H 02H 03H 04H 05H 06H 07H 08H - - - - - - - 79H 7AH 7BH 7CH 7DH 7EH 7FH 00H ------01H ------02H ------03H ------04H ------05H ------06H ------07H ------08H ------09H ------0AH ------0BH ------0CH ------0DH ------0EH ------0FH ----------- ----70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH ------------------------------------------------------------------------------------------------- 4K color D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Red Green Blue Figure 15. Display Data RAM Map 18 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Partial Display Mode The S6B33A2 realizes the partial display function with low duty driving for saving power consumption and showing the various display duties. It is set as display start/end line number. Area Scroll Function The S6B33A2 realizes the specific area scroll function. (1/128 duty case). Example of Scrolling up 0 Fixed 15 lines 14 15 100 Lines 115 Fixed 18 lines 127 Example of Scrolling down 0 LCD Panel Fixed area Scroll area Display area 14 15 115 127 Figure 16. Area scroll examples (duty = 1/128, center scroll mode) 19 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Display Direction SDIR The direction of segment display is selected by SDIR which is a bit in internal register. SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 Y=0 x=0 SEGA127 SEGB127 9 SEGC127 Y=1 (D3~D0) (D7~D0) (D3~D0) (D7~D0) 1st 2nd 1st 2nd Y = 127 (D3~D0) (D7~D0) 1st 2nd Figure 17. 8-bit data bus mode when SDIR = “0” SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 Y=0 (D11~D0) x=0 SEGA127 SEGB127 SEGC127 Y=1 (D11~D0) Y = 127 (D11~D0) Figure 18. 16-bit data bus mode when SDIR = “0” SEGA0 SEGB0 SEGC0 x=0 SEGA1 SEGB1 SEGC1 Y = 127 SEGA127 SEGB127 SEGC127 Y = 126 Y=0 (D3~D0) (D7~D0) (D3~D0) (D7~D0) (D3~D0) (D7~D0) 1st 2nd 1st 2nd 1st 2nd Figure 19. 8-bit data bus mode when SDIR = “1” SEGA0 SEGB0 SEGC0 x=0 Y = 127 (D11~D0) SEGA1 SEGB1 SEGC1 SEGA127 SEGB127 SEGC127 Y = 126 (D11~D0) Y=0 (D11~D0) Figure 20. 16-bit data bus mode when SDIR = “1” 20 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD CDIR The direction of common scanning is selected by CDIR pin. COM 62 SEG128RGB Driver COM 0 COM128 COM63 128Display Lines <CDIR=0> COM 0 <CDIR=1> Line number 0 COM 0 COM 1 Display Area COM 127 COM 128 Line number 127 Display Area Line number 127 COM 128 Line number 0 21 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD * i = 0 to 127 SWP=1 RAM DATA SEGAi SEGBi Gray Scale control Gray Scale control SEGCi Gray Scale control D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 MPU I/F DATA[11:0] D0 MPU I/F DATA[11:0] R3 SWP = 0 SWP = 1 B0 * i = 0 to 127 SWP=0 RAM DATA D11 SEGAi SEGBi Gray Scale control Gray Scale control D1 R2 D2 R1 SEGCi Gray Scale control D3 D4 D5 D6 D7 D8 R0 G3 G2 G1 G0 B3 D9 B2 D10 D11 B1 B0 SEGAi SEGBi SEGCi RED GREEN BLUE Color D11 ~ D8 D7 ~ D4 D3 ~ D0 Assigned Bit BLUE GREEN RED Color D3~ D0 D7 ~ D4 D11 ~ D8 Figure 21. The relationship between SEG outputs and RGB color Assigned Bit 22 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD On-Chip Regulator Configuration Value of external Capacitance REG_OUT REG_OUT Item Value Unit C1 1.0 to 4.7 µF Floating C1 VDD1 VDD1 VDD VDD VDD VDD VDD: 2.4 ~ 3.3V VDD: 1.7 ~ 3.3V Figure 22. Regulator Application Oscillator Circuit When internal oscillator is used(EXT=0), the selection of oscillator resistor is determined by display mode. Normal display mode/ Partial display mode 0 : resistor1 between OSC1 and OSC2 Partial display mode 1 : resistor2 between OSC3 and OSC4 When external clock is used (EXT=1), clock frequency should be adjusted to display mode which is selected. Example of external oscillator application Ext. VSS When external clock mode (EXT = “H”) is used, it is not possible to use the partial mode1 OSC5 OSC4 OSC3 OSC2 OSC1 Figure 23. External oscillator application 23 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Example of internal oscillator application VSS/VDD VSS/VDD R1 OSC5 OSC4 OSC3 OSC2 R2 OSC1 When partial display mode 1 is not used. OSC5 OSC4 R1 OSC3 OSC2 OSC1 When partial display mode 1 is used. Figure 24. Internal oscillator application Discharge Circuit Driving voltage level discharge time at stand by ON. T[ms] Internal STB signal +VR V1 VM V+[mV] VSS V-[mV] -VR The relation between voltage level and discharge time from when “Stand By ON” command is inputted. LEVEL CONDITION T[ms] △V+,△V-[mV] +VR,V1,VM,-VR +VR=10.5V, V1=3.0V, VM=1.5V, -VR=-7.5V at T=0 100 300 < 50 < 20 24 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD INSTRUCTION DESCRIPTION Table 15. Instruction Table Instruction Name DB15 DB7 ~DB8 D/I /WR /RD DB6 DB5 DB4 DB3 DB2 DB1 DB0 Non Operation 0 0 1 * Oscillation Mode Set 0 0 1 Driver Output Mode Set 0 0 1 DC-DC Select 0 0 DCDC Clock Division Set 0 DCDC and AMP ON/OFF set 0 Temperature Compensation Set Contrast Control(1) Contrast Control(2) Hex. Parameter 0 0 0 0 0 0 0 0 00 - * 0 0 0 0 0 0 1 0 02 1Byte * 0 0 0 1 0 0 0 0 10 1Byte 1 * 0 0 1 0 0 0 0 0 20 1Byte 0 1 * 0 0 1 0 0 1 0 0 24 1Byte 0 1 * 0 0 1 0 0 1 1 0 26 1Byte 0 0 1 * 0 0 1 0 1 0 0 0 28 1Byte 0 0 1 * 0 0 1 0 1 0 1 0 2A 1Byte 0 0 1 * 0 0 1 0 1 0 1 1 2B 1Byte Standby Mode OFF 0 0 1 * 0 0 1 0 1 1 0 0 2C - Standby Mode ON 0 0 1 * 0 0 1 0 1 1 0 1 2D - Addressing Mode Set 0 0 1 * 0 0 1 1 0 0 0 0 30 1Byte ROW Vector Mode Set 0 0 1 * 0 0 1 1 0 0 1 0 32 1Byte N-line Inversion Set 0 0 1 * 0 0 1 1 0 1 0 0 34 1Byte Red palette Set 0 0 1 * 0 0 1 1 1 0 0 0 38 8Byte Green palette Set 0 0 1 * 0 0 1 1 1 0 1 0 3A 8Byte Blue palette Set 0 0 1 * 0 0 1 1 1 1 0 0 3C 4Byte Entry Mode Set 0 0 1 * 0 1 0 0 0 0 0 0 40 1Byte X-address Area Set 0 0 1 * 0 1 0 0 0 0 1 0 42 2Byte Y-address Area Set 0 0 1 * 0 1 0 0 0 0 1 1 43 2Byte Display OFF 0 0 1 * 0 1 0 1 0 0 0 0 50 - Display ON 0 0 1 * 0 1 0 1 0 0 0 1 51 - Specified Display Pattern Set 0 0 1 * 0 1 0 1 0 0 1 1 53 1Byte Partial Display Mode Set 0 0 1 * 0 1 0 1 0 1 0 1 55 1Byte Partial Display Start Line Set 0 0 1 * 0 1 0 1 0 1 1 0 56 1Byte Partial Display End Line Set 0 0 1 * 0 1 0 1 0 1 1 1 57 1Byte Area Scroll Mode Set 0 0 1 * 0 1 0 1 1 0 0 1 59 4Byte Scroll Start Line Set 0 0 1 * 0 1 0 1 1 0 1 0 5A 1Byte Display Format Select(Mode0) 0 0 1 * 0 1 1 0 1 1 1 0 60 - Display Format Select(Mode1) 0 0 1 * 0 1 1 0 1 1 1 1 61 - Set Display Data Length X X X * 1 1 1 1 1 1 0 0 FC 2Byte Display Data Write 1 0 1 Display Data Write - - Display Data Read 1 1 0 Display Data Read - - Status Read 0 1 0 Status Data Read - - Test Mode0 0 0 1 * 1 1 1 1 1 1 1 1 FF - Test Mode1 0 0 1 * 1 1 1 1 1 1 1 0 FE - *: Don’t care Parameter: The number of parameter bytes that follows instruction data. 25 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Non Operation (00H) This instruction is Non operation. D/I /WR /RD DB7 0 0 1 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 0 0 0 0 0 DIV2 EXT OSC Oscillation Mode Set (02H) Setting internal function mode. D/I /WR /RD 0 0 1 DIV2: Display clock selecting DIV2 = 0: Display clock = OSC clock (Initial status) DIV2= 1: Display clock = OSC/2 clock EXT: External clock selecting EXT = 0: Internal clock mode (Initial status) EXT = 1: External clock mode OSC: Internal oscillator ON/OFF OSC = 0: Internal oscillator OFF(Initial status) OSC = 1: Internal oscillator ON Driver Output Mode Set(10H) This instruction sets the display direction. D/I /WR /RD 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 SDIR SWP SDIR: Segment direction This bit is for controlling the direction of segment driver. SDIR = 0 (Initial status) SWP: Swap segment output SEGAi and SEGCi This bit is for swapping the output of segment driver. SWP = 0 (Initial status) 26 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC-DC Select (20H) Selects DC-DC step-up of the common driver in normal and partial mode D/I /WR /RD 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 DC(2) DC(1) DC(1) : 1’st DC-DC booster boosting step select for V1 generation in normal mode and partial mode 0. DC(2) : 1’st DC-DC booster boosting step select for V1 generation in partial mode 1. DC(2) : In partial mode 1 DC(1) : In normal mode, partial mode 0 DB1 DC-DC step up DB0 DC-DC step up 0 X1.0 0 X1.0 1 X1.5 1 X1.5 27 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC-DC Select and power supply for V1 Op-Amp. Even if VIN45 is connected to VOUT45 or VIN1, a setup by software must be able to be performed. Power supply for V1 Op.Amp. is decided by Hardware setting and Software setting. The example of usage is shown below. Figure28. Example : Hardware Setting Software Setting Hardware Setting : VIN45 connected to VOUT45 : Power supply for V1 Op.Amp. uses VIN1 ( not VOUT45). Software Setting VIN45 VOUT45 + VSS C11+ C11- V1 1st Booster Circuit R1 C12+ EV_256 C12- R1 VIN1 Reference voltage generator & Temperature Compensation Control Circuit V1 generation circuit Hardware setting : VIN45 connected to (1) VIN1 (when 1’st boosting is not used) (2) VOUT45 (when 1’st boosting is used) Software setting : DC-DC Select(20H) - DC(1), DC(2) Set value “00” Power supply for V1 Op.Amp. uses VIN1 directly. Set value “01” or “10” Power supply for V1 Op.Amp. uses VOUT45. 28 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DCDC Clock Division (24H) This instruction sets the internal booster clock frequency. D/I /WR /RD DB7 DB6 DB5 0 0 1 0 0 0 0 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 0 0 1 DIV(2) DIV(1) DIV(1) : DC-DC Charge Pump Division Ratio in Normal Mode Display and Partial Display Mode0 - DIV(1) = 10 (Initial status) DIV(2) : Division Ratio in Partial Display Mode1 - DIV(2) = 10 (Initial status) DB5 DB4 DIV(2) DB1 DB0 DIV(1) 0 0 fPCK = fOSC/2x 0 0 fPCK = fOSC/2x 0 1 fPCK = fOSC/4x 0 1 fPCK = fOSC/4x 1 0 fPCK = fOSC/6x 1 0 fPCK = fOSC/6x 1 1 fPCK = fOSC/8x 1 1 fPCK = fOSC/8x Note: fOSC = ( ROUNDUP (Duty/3) + dummy) x 4 x 4 x frame frequency DC/DC and AMP ON/OFF Set (26H) This instruction set up the DC/DC and Op-amp in common start up setting. D/I /WR /RD 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 1 1 0 0 0 AMP DCDC3 DCDC2 DCDC1 0 0 AMP : Built-in OP-AMP ON/OFF. - AMP=0 :OP-AMP OFF(Initial status) - AMP=1 :OP-AMP ON st DCDC1: Built-in 1 Booster ON/OFF (Initial status) st - DCDC1= 0: 1 Booster OFF (Initial status) st - DCDC1= 1: 1 Booster ON st DCDC2: Built-in 1 Booster ON/OFF (Initial status) nd - DCDC2= 0: 2 Booster OFF (Initial status) nd - DCDC2= 1: 2 Booster ON st DCDC3: Built-in 1 Booster ON/OFF (Initial status) rd - DCDC3= 0: 3 Booster OFF (Initial status) rd - DCDC3= 1: 3 Booster ON 29 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Temperature Compensation Set (28H) This Instruction sets up the driving voltage slope for temperature compensation. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 0 0 1 DB2 DB1 DB0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 TCS TCS: Temperature compensation slope set TCS = 00 : 0.00%/degC TCS = 01 : -0.05%/degC TCS = 10 : -0.10%/degC TCS = 11 : -0.15%degC 00: 0.00 %/degC Driving voltage 01: -0.05 %/degC 10: -0.10 %/degC 11: -0.15 %/degC Temperature 30 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Temperature Compensation If external temperature compensation is needed, circuit diagram is described as below. To use temperature compensation, two resistors and one thermistor are needed. Internal External Chip V1-i + V1-o - V1-t INTRS 31 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Contrast Control (1) (2AH) This instruction updates the contrast control value in normal display mode and partial display mode 0. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 0 0 0 1 0 1 0 1 0 1 DB0 0 Contrast control value (0 to 255) The relation between V1 voltage (typ.) and Contrast(1) set value ( 3bit step case) Contrast(1) Contrast(1) Contrast(1) Contrast(1) Contrast(1) V1[V] V1[V] V1[V] V1[V] V1[V] (HEX) (HEX) (HEX) (HEX) (HEX) 00h 2.000 30h 2.244 60h 2.488 90h 2.731 C0h 2.975 08h 2.041 38h 2.284 68h 2.528 98h 2.772 C8h 3.016 10h 2.081 40h 2.325 70h 2.569 A0h 2.813 D0h 3.056 18h 2.122 48h 2.366 78h 2.609 A8h 2.853 D8h 3.097 20h 2.163 50h 2.406 80h 2.650 B0h 2.894 E0h 3.138 28h 2.203 58h 2.447 88h 2.691 B8h 2.934 E8h 3.178 Contrast(1) (HEX) F0h F8h FFh V1[V] 3.219 3.259 3.300 Contrast Control (2) (2BH) This instruction updates the contrast control value in partial display mode 1. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 0 0 0 1 0 0 1 0 DB2 DB1 DB0 0 0 1 Contrast control value (0 to 255) The relation between V1 voltage (typ.) and Contrast(2) set value ( 3bit step case) Contrast(1) (HEX) 00h 08h 10h 18h 20h 28h V1[V] 2.000 2.041 2.081 2.122 2.163 2.203 Contrast(1) (HEX) 30h 38h 40h 48h 50h 58h V1[V] 2.244 2.284 2.325 2.366 2.406 2.447 Contrast(1) (HEX) 60h 68h 70h 78h 80h 88h V1[V] 2.488 2.528 2.569 2.609 2.650 2.691 Contrast(1) (HEX) 90h 98h A0h A8h B0h B8h V1[V] 2.731 2.772 2.813 2.853 2.894 2.934 Contrast(1) (HEX) C0h C8h D0h D8h E0h E8h V1[V] 2.975 3.016 3.056 3.097 3.138 3.178 Contrast(1) (HEX) F0h F8h FFh V1[V] 3.219 3.259 3.300 32 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Standby Mode OFF (2CH) This instruction releases the standby mode. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 1 0 1 1 0 0 The internal statuses during standby off are as following: All common and segment output: refer to following Oscillator circuit: On (EXT = 0, OSC=1),OFF (others) Displaying clocks (FR, PM, CL, CK): In operation Function and Pin condition at standby OFF Function/Pin Condition DC/DC booster(1’st,2’nd,3’rd) ON(Operate) COM outputs +VR /VM / VSS /–VR SEG outputs V1 /VSS Standby Mode ON (2DH) This instruction enters the standby mode to reduce the power consumption to the static power consumption value (Initial status). The following instructions, standby off and display on, cause returning to the normal operation status. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 1 0 1 1 0 1 The internal statuses during standby on are as following: All common and segment output: refer to following table Oscillator circuit: OFF Displaying clocks (FR, PM, CL, CK) are held. Function and Pin condition at standby ON Function/Pin Condition DC/DC booster(1’st,2’nd,3’rd) OFF SEG and COM outputs VSS LCD driving power output condition at Standby ON. Level Condition +VR VSS V1 VSS VM VSS -VR VSS 33 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Addressing Mode Set (30H) D/I /WR /RD 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 0 0 0 0 GSM DSG SGF SGP SGM GSM: Gray Scale Mode 0 : 4,096 Color mode(Initial status) 1 : 256 Color mode 1. 8 bit mode : DB[7:0] :RRRGGGBB 2.16bit mode: DB[15:0] :RRRGGGBBRRRGGGBB 3. 3bits of R and G, 2bits of B are expanded to 4 bit internally by red, green and blue palette set instruction DSG : Duty Adjust Setting 0 : Dummy subgroup is one subgroup (Initial status) 1 : Dummy subgroup is none SGF : SG Frame Inversion mode setting 0: SG Frame inversion OFF (Initial status) 1: SG Frame inversion ON SGM : SG inversion mode setting 0: SG inversion OFF (Initial status) 1: SG inversion ON SGP : SG Phase mode setting 00 : Same phase in all pixels 01 : Different phase by 1pixel-unit 10 : Different phase by 2pixel-unit 11 : Different phase by 4pixel-unit Row Vector Mode Set (32H) Setting ROW function. D/I WRB RDB 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 1 0 0 0 0 0 INC VEC INC: Row Vector Increment Mode. This Parameter set up Row vector increment period DB3 DB2 DB1 Row Vector Increment Period 0 0 0 Every subgroup 0 0 1 Every 2subgroup 0 1 0 Every 4subgroup 0 1 1 Every 8subgroup 1 0 0 Every 16subgroup 1 0 1 Every 16subgroup 1 1 0 Every 16subgroup 1 1 1 Every subframe VEC: ROW Vector Sequence Mode - 0: R1->R2->R3->R4 -> R1….. (initial status) - 1: R1->R3->R2->R4 -> R1….. 34 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD N-block inversion Set (34H) This instruction set up N block inversion for AC driving. D/I /WR /RD DB7 DB6 DB5 0 0 1 0 0 0 FIM FIP 0 DB4 DB3 DB2 DB1 DB0 1 1 1 1 1 N-block inversion FIM: Forcing Inversion Mode FIM = 0: Forcing Inversion OFF (Initial status) FIM = 1: Forcing Inversion ON FIP: Forcing Inversion Period FIP = 0: Forcing Inversion Period is one frame FIP = 1: Forcing Inversion Period is two frames N-block Inversion : This parameter indicates the basic period of polarity inversion. The whole period of polarity inversion is decided by FIM, FIP and this parameter. DB7 DB6 DB5 DB4 – DB0 Polarity Inversion Period X x x 0 every frame 0 x x 1 every 1 block : : : : : 0 x x 31 every 31 blocks 1 0 x 1 every 1 block and every frame : : : : 1 0 x 31 every 31 blocks and every frame 1 1 x 1 every 1 block and every 2 frames : : : : 1 1 x 31 : : every 31 blcks and every 2 frames 35 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Red palette Set (38H) Setting red gray scale data for 256 Color mode. D/I /WR /RD DB7 DB6 0 0 1 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 1 1 0 0 0 0 RAM data “000” to GS data 0 0 0 0 RAM data “001” to GS data 0 0 0 0 RAM data “010” to GS data 0 0 0 0 RAM data “011” to GS data 0 0 0 0 RAM data “100” to GS data 0 0 0 0 RAM data “101” to GS data 0 0 0 0 RAM data “110” to GS data 0 0 0 0 RAM data “111” to GS data DB5 DB4 DB3 DB2 DB1 DB0 1 0 1 0 Green palette Set (3AH) Setting green gray scale data for 256 Color mode. D/I /WR /RD DB7 DB6 0 0 1 0 0 1 1 0 0 0 0 RAM data “000” to GS data 0 0 0 0 RAM data “001” to GS data 0 0 0 0 RAM data “010” to GS data 0 0 0 0 RAM data “011” to GS data 0 0 0 0 RAM data “100” to GS data 0 0 0 0 RAM data “101” to GS data 0 0 0 0 RAM data “110” to GS data 0 0 0 0 RAM data “111” to GS data Blue palette Set (3CH) Setting blue gray scale data for 256 Color mode. D/I 0 /WR 0 /RD 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 1 0 0 0 0 0 0 RAM data “000” to GS data 0 0 0 0 RAM data “001” to GS data 0 0 0 0 RAM data “010” to GS data 0 0 0 0 RAM data “011” to GS data 36 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Entry Mode Set (40H) Setting internal function mode. D/I /WR /RD 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 0 0 0 0 0 0 0 0 0 0 HL X/Y RMW HL: Exchange higher and lower byte only for “Display Data Write/Read” in 256 color & 16-bit data bus . HL = 0 : Exchange status(initial status) HL = 1 : Not exchange status X/Y: Memory address counter mode setting X/Y = 0: Y address counter mode (Initial status) X/Y = 1: X address counter mode (Don’t use in 256 color & 16bit data bus mode) RMW: Read modify write mode ON/OFF select RMW = 0: Read modify write OFF (Initial status) RMW = 1: Read modify write ON. When this mode is on, X(Y) address of on-chip display RAM is increment not in reading display data but in writing display data. X Address Area Set (42H) This instruction and parameter set up the X address areas of the on-chip display data RAM. D/I /WR /RD 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 0 0 0 1 0 0 X start address set (Initial Status = 00H) 0 X end address set (Initial Status = 7FH) The current X address of the on-chip display data RAM is the X start address by setting this instruction. In X address count mode (X/Y = “H”), the X address is increased from X start address to X end address. When X address is equal to the X end address, the Y address is increased by 1 and the X address returns to X start address. The X start and X end addresses must be set as a pair and X start address must be less than X end address. Address Area Set (43H) This instruction and parameter set up the Y address areas of the on-chip display data RAM. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 0 0 0 1 1 0 0 0 0 DB1 DB0 1 1 0 Y start address set (Initial Status = 00H) 0 Y end address set (Initial Status = 7FH) The current Y address of the on-chip display data RAM is the Y start address by setting this instruction. In Y address count mode (X/Y = “L”), the Y address is increased from Y start address to Y end address. When Y address is equal to the Y end address, the X address is increased by 1 and the Y address returns to Y start address. The Y start and Y end address must be set as a pair and Y start address must be less than Y end address. 37 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Display OFF (50H) Turn the display OFF(Initial status). When display is off, all segment and common output are VSS level. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 0 0 0 0 Function and Pin condition at Display OFF Function/Pin st Condition nd rd DC/DC booster(1 ,2 ,3 ) ON(Operate) SEG and COM outputs VSS Display ON (51H) Turns the display ON. In case of being standby mode, this instruction does not work. This instruction is executed after standby mode off. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 0 0 0 1 Function and Pin condition at Display ON Function/Pin Condition st nd rd DC/DC booster(1 ,2 ,3 ) ON(Operate) COM outputs +VR /VM /-VR SEG outputs V1 /VSS Specified Display Pattern Set (53H) This instruction sets the specified display pattern. D/I /WR /RD 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 SDP SDP : Specified Display Pattern set - SDP = 00 : Normal display - SDP = 01 : Reverse display : Display data reversing mode setting without the contents of the display RAM SDP = 10 : Whole display pattern becomes OFF regardless of the RAM data. SDP = 11 : Whole display pattern becomes ON regardless of the RAM data. 38 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Partial Display Mode Set (55H) D/I /WR /RD 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 PDM PT PT: Partial Display ON/OFF PT = 0: Partial display OFF = Normal mode (Initial status) PT = 1: Partial display ON PDM: Partial Display mode set PDM = 0: Partial mode 0 : Duty ratio is same as Normal display mode(initial status) PDM = 1: Partial mode 1 : Duty ratio is changed from Normal display mode(66 duty fixed) Applied parameter in PDM0 and PDM1 are summarized as below PDM Contrast Duty Bias DC-DC Select OSC PCK 0 Contrast control(1) Normal Bias(1) DC-DC(1),DC(1) OSC1-OSC2 DIV(1) 1 Contrast control(1) 1/66 Bias(2) DC-DC(1),DC(2) OSC3-OSC4 DIV(2) Partial Start Line Display Area Partial Start Line M line N line Partial End Line Max. 66 line Partial End Line PDM 0 No display Area PDM 1 : No COM Scanning field (COM = Vm fixed) Except Partial Display Area : COM Timing is existing, but COM = Vm fixed Partial Display Area : Real display field Operation in Partial Display Mode 0 (PDM=0) On scanning except partial display area -SEG output select V0 or V1 level depend on “FR” value. Refer to 44 -All of COM output is fixed VM level. On scanning partial display area -It is equal to be in normal mode Operation in Partial Display Mode 1 (PDM=1) Display area is from partial start line to partial end line. (COM driver output is fixed VM except display area, only max66 line output COM signal. On scanning except partial display area -SEG output select V0 or V1 level depend on “FR” value. Refer to Page44 -All of COM output is fixed VM level. On scanning partial display area -It is equal to be in normal mode 39 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Partial Display Mode0 In case of COM 6 to COM11 Partial display +VR VM -VR <COM0-2> <COM3-5> <COM6-8> <COM9-11> <COM12-14> Normal Display Mode Item Duty Contrast Oscillator Partial Display Mode 0 Partial Display Area Out of Partial Display Area Same as normal display mode Same as normal display mode ( Contrast(1) setting ) Same as normal display mode ( OSC1 – OSC2 ) SEG Output level Same as normal mode (V1,V0) COM Output level Same as normal mode (+VR,VM,-VR) Depends on Internal “FR” signal See page 44 VM fixed 40 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Partial display mode1 In case of COM 6 to COM11 Partial display +VR VM -VR <COM0-2> <COM3-5> <COM6-8> <COM9-11> <COM12-14> Normal Display Mode Item Partial Display Area Partial Display Mode 1 Out of Partial Display Area Duty 1/66duty Contrast Contrast(2) setting Oscillator ( OSC3 – OSC4 ) setting value SEG Output level Same as normal mode (V1,V0) COM Output level Same as normal mode (+VR, VM, -VR) Depends on “FR” signal See page 44 VM fixed Out of Display Area VM fixed 41 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Partial Display Start Line Set (56H), Partial Display End Line Set(57H) These 2 instructions set the partial display area and it is possible to display a part. Partial Display Start Line Set (56H) D/I /WR /RD 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 1 0 1 1 0 0 Partial start line Partial Display End Line Set (57H) D/I /WR /RD 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 1 0 1 1 1 0 COM 0 COM 1 COM 2 COM 3 COM 126 COM 127 COM 128 Partial end line line 0 line 1 line 2 line 3 : : : line 126 line 127 line 128 Parameter set appoints display line number. At PDM 0, Parameter Size is able to be in a number of Display lines. But that is not able to be over max 66 line at PDM 1. Partial end line must set bigger number than Partial start line. 42 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Example of Segment Voltage in non-display area N Frame Subframe 0 1 N+1 2 3 0 +VR VM COM VM VM VM VM Display Off -VR Partial Display Addressing Duty internal polarity counter (FR) V1 SEG V0 V1 V0 V1 V0 V1 V1 V0 V1 V0 V0 43 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Area scroll Set (59H) This instruction sets up area scroll field (start line, end line, Lower fixed line number), and it is possible to make screen to display as partial scroll field. D/I 0 /WR 0 /RD 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 Scroll area start line 0 Scroll area end line 0 Lower fixed number SCM Note: In lower and center scroll mode, scroll area end line must be smaller than duty - lower fixed number. SCM: Scroll mode setting DB1 DB0 Mode 0 0 Entire display(Initial status) 0 1 Upper scroll display 1 0 Lower scroll display 1 1 Center scroll display Entire Display Upper Display Lower Display Center Display 44 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Scroll Start Line Set (5AH) This instruction and parameter set up scroll start line. On this instruction, scroll start line becomes the first of area scroll field. Scroll operation is occurred every issue of this instruction. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 0 1 0 1 0 Scroll start line <Example> -SCM : 2’b11 (Center display mode) -Scroll area start line : 6 -Scroll area end line : 119 -Lower fixed number : 8 -Scroll start line : 40 <DUTY BLOCK> COM0 COM6 <RAM BLOCK> Upper fix Xadr=0 Xadr=6 <DISPLAY> Upper fIx COM0 Addr0 COM6 Addr5 Addr40 Xadr=40 Scroll display COM120 COM127 Lower fix Scroll area Xadr=120 Xadr=127 Lower fix Addr119 Addr6 COM120 COM127 Addr39 Addr120 Addr127 RAM Address. 45 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Normal Mode Set partial start line Set partial end line Set partial mode 0 Set scroll mode Set scroll area start line Set scroll area end line Set lower fixed line no. Set scroll start line Set scroll mode Set scroll area start line Set scroll area end line Set lower fixed line Set scroll start line Set partial start line Set partial end line Set partial mode 0 Scroll Mode Scroll/Partial Mode 0 Set scroll mode Set scroll area start line Set scroll area end line Set lower fixed line no. Set scroll start line Set scroll mode Set scroll area start line Set scroll area end line Set lower fixed line no. Set scroll start line Release partial mode Partial Mode 0 Release partial mode Normal Mode Data Format Select (60H/61H) D/I WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 0 0 0 0 DFS DFS: 4,096 Color Mode Data Format Select - 0 : 4,096 Color Data Format A (Initial Status) 8 bit mode : DB[7:0] : XXXXRRRR (1’st write) DB[7:0] : GGGGBBBB(2’nd write) 16 bit mode : DB[15:0] :XXXXRRRRGGGGBBBB (12 bit) - 1 : 4,096 Color Data Format B 8 bit mode : DB[7:0] : RRRRGGGG(1’st write) DB[7:0] : BBBBRRRR (2’nd write) DB[7:0] : GGGGBBBB(3’rd write) 16 bit mode : DB[15:0] :RRRRGGGGBBBBXXXX (12 bit) 46 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Display Data Write/Read D/I /WR /RD 1 0 1 Display RAM write in data 1 1 0 Display RAM read out data 1. 4,096 Color mode (1) 16bit access mode 15 DB15 ~ DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 2 cycle X (2) 8bit access mode 7 X X X R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 6 5 4 3 2 1 0 X X X X R3 R2 R1 R0 st 1 cycle nd st 1 cycle nd cycle G3 G2 G1 G0 B3 B2 B1 B0 rd cycle X X X X R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 cycle R2 (3) 8bit access mode R1 R0 G2 G1 G0 B1 B0 R2 R1 R0 G2 G1 G0 B1 B0 7 6 5 4 3 2 1 0 R2 R1 R0 G2 G1 G0 B1 B0 2 3 th 4 cycle 2. 256 color mode (1) 16bit access mode st st 1 cycle Status Read D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 BSY X/Y 0 PDM PT STB REV DP This instruction indicates the internal status of the S6B33A2. DP: ( 0 : Display OFF Status, 1 : Display ON Status ) REV: ( 0 : Display Image Non-Reversing, 1 : Display Image Reversing ) STB: ( 0 : Standby Mode OFF Status, 1 : Standby Mode ON Status ) PT: ( 0 : Partial Display Mode OFF Status, 1 : Partial Display Mode ON Status ) PDM: ( 0 : Partial Display Mode 0, 1 : Partial Display Mode 1 ) X/Y: ( 0 : Y-address Count Mode, 1 : X-address Count Mode ) BSY: ( 0 : No Busy, 1 : Busy ) 47 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Set Display Data Length This Instruction is only used in 3-pin SPI MPU interface mode(PS=”L”, MPU[1]=”L”). It consists of two continuous commands, the first byte control the data direction(write mode only) and inform the LCD driver the second and third bytes will be number of data bytes will be write. When DI is not used, the Display Data Length instruction is used to indicate that a specified number of display data bytes are to be transmitted. The next byte after the display data string is handled as command data. D/I /WR 0 0 /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 1 1 1 1 0 0 1 Number of display data upper 8bits (DDL_H) Number of display data lower 8bits (DDL_L) Test Mode1 (FFH) This Instruction is for testing IC. User is not permitted to access. If access ,have to reset. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 1 1 1 1 1 1 DB1 DB0 1 0 Test Mode2 (FEH) This Instruction is for testing IC. User is not permitted to access. If access ,have to reset. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 0 0 1 1 1 1 1 1 1 48 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD INSTRUCTION PARAMETER Table 16. Instruction Parameter Instruction Hex Para. Oscillation Mode Set 02H 1 Driver Output Mode Set 10H 1 DC-DC Set 20H 1 PCK Generation Mode Set 24H 1 DCDC and AMP ON/OFF Set 26H 1 Temperature Compensation Set 28H 1 Contrast Control (1) 2AH 1 Contrast Control(2) 2BH 1 Addressing Mode Set 30H 1 ROW Vector Mode Set 32H 1 N-line Inversion Set 34H 1 Red palette Set 38H 8 Green palette Set 3AH 8 Blue palette Set 3CH 4 Entry Mode Set 40H 1 X-address Area Set 42H 2 Y-address Area Set 43H 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 EXT OSC * * * * * * 0 0 0 0 0 0 0 0 SDIR SWP * * * * * * 0 0 0 0 0 0 0 0 DC(2) DC(1) 0 0 0 0 0 0 0 0 0 0 DIV(2) 0 0 DIV(1) * * 1 0 * * 1 0 0 0 0 0 AMP DCDC3 DCDC2 DCDC1 * * * * 0 0 0 0 0 0 0 0 0 0 TCS * * * * * * 0 0 Contrast control value in normal and partial display mode0(0 to 255) 0 0 0 0 0 0 0 0 Contrast control value in partial display mode 1(0 to 255) 0 0 0 0 0 0 0 0 0 GSM DSG SGF SGP SGM 0 * * 0 0 0 0 0 0 0 0 0 0 INC VEC * * * * 0 0 0 0 FIM FIP 0 N-block Inversion 0 0 * 0 0 0 0 0 0 0 0 0 RAM data “000” to GS data 0 0 0 0 RAM data “001” to GS data 0 0 0 0 RAM data “010” to GS data 0 0 0 0 RAM data “011” to GS data 0 0 0 0 RAM data “100” to GS data 0 0 0 0 RAM data “101” to GS data 0 0 0 0 RAM data “110” to GS data 0 0 0 0 RAM data “111” to GS data 0 0 0 0 RAM data “000” to GS data 0 0 0 0 RAM data “001” to GS data 0 0 0 0 RAM data “010” to GS data 0 0 0 0 RAM data “011” to GS data 0 0 0 0 RAM data “100” to GS data 0 0 0 0 RAM data “101” to GS data 0 0 0 0 RAM data “110” to GS data 0 0 0 0 RAM data “111” to GS data 0 0 0 0 RAM data “000” to GS data 0 0 0 0 RAM data “001” to GS data 0 0 0 0 RAM data “010” to GS data 0 0 0 0 RAM data “011” to GS data 0 0 0 0 0 HL X/Y RMW * * * * * 0 0 0 0 X Start address set * 0 0 0 0 0 0 0 0 X end address set * 1 1 1 1 1 1 1 0 Y start address set * 0 0 0 0 0 0 0 0 Y end address set * 1 1 1 1 1 1 1 49 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Set Display Data Length FCH 2 Specified Display Pattern Set 53H 1 Partial Display Mode Set 55H 1 Partial Display Start Line Set 56H 1 Partial Display End Line Set 57H 1 Area Scroll Mode Set 59H 4 Scroll Start Line Set 5AH 1 Number of display data upper word 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 0 0 * 0 1 0 0 Number of display data lower word 0 0 0 0 SDP * * * * 0 0 0 0 0 0 PDM PT * * * * 0 0 Partial start line 0 0 0 0 0 0 Partial end line 0 0 0 0 0 0 0 0 0 0 SCM * * * * 0 0 Scroll area start line 0 0 0 0 0 0 Scroll area end line 1 1 1 1 1 Lower Fixed number 0 0 0 0 0 0 Scroll start line 0 0 0 0 0 0 50 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Reset Operation When /RST becomes “L”, following procedure is occurred. - X address: 0 - Y address: 0 - Display OFF - Read Modify Write Mode OFF - Function Mode Set OSC = 0: Oscillator OFF EXT = 0: Internal Oscillator Mode REV = 0: Reversing mode OFF X/Y = 0: Y-address Count Mode HL = 0 Standby Mode ON - PCK Generation mode Set DIV(1) = 10: fPCK = fOSC/6x DIV(2) = 10: fPCK = fOSC/6x - DC-DC Select DC(1) = 0: X1 step-up DC(2) = 0: X1 step-up - DC/DC and AMP ON/OFF Set AMP =0: Built-in OP-AMP OFF st DCDC1 =0: Built-in 1 booster OFF nd DCDC2 =0: Built-in 2 booster OFF rd DCDC3 =0: Built-in 3 booster OFF - N-block inversion FIM =0: Forcing Inversion OFF FIP =0: Forcing Inversion Period in one frame N-block inversion = 00H: frame inversion - Partial Display Mode PT = 0: Partial Display Mode OFF PDM = 0: Partial Mode 0 - Partial Display Area Set Partial start line = 00H Partial end line = 00H -Area Scroll Set Mode = 00H : Entire Display Scroll Mode Area Start Line: 00H Area End Line: 7FH Lower Fixed Line Number: 00H - Scroll Start Line Set Scroll Start Line: 00H - Addressing Mode Set GSM =0: 4,096 color mode DSG = 0: Mode 0 SGF = 0: SG Frame Inversion OFF SGM = 0: SG Reverse Mode OFF SGP=00:Same phase in all pixel 51 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Item Symbol Supply Voltage range VDD LCD Supply Voltage range |VCC – VEE| Input Voltage range Vin Operating Temperature range TOPR Storage Temperature range TSTR Rating Unit to V -0.3 +4.0 20 - 0.3 to V VDD +0.3 V °C -30 to +70 -55 to °C +150 OPERATING VOLTAGE Item Symbol Min. Typ. Max. Unit Supply Voltage (1) VDD 1.8 - 3.3 V Supply Voltage (2) 2Vr - - 20 V Supply Voltage (3) VIN 2.4 3.0 3.6 V 52 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC CHARACTERISTICS (1) (Vss = 0V, VDD = 1.8 to 3.3V, Ta = -30 to 70 °C) Item Symbol Operating voltage Condition Min Typ Max Unit Remarks VDD 1.8 - 3.3 V VDD Operating voltage VIN1 2.4 - 3.6 V VCI Operating voltage DC2IN 1.66 - 2.75 V DC2IN Operating voltage VIN2 2.4 - 5.4 V VIN2 Operating voltage VIN45 2.4 - 5.4 V VIN45 Operating voltage 2Vr 4.0 - 20 V +VR, -VR 1.0 1.65 V VM 7.0 11.55 V VCC VEE -8.25 -5.0 V VEE High VIH 0.8VDD - VDD Low VIL VSS - 0.2VDD High VOH IOH = 0.5mA 0.8VDD - VDD Low VOL IOL = 0.5mA VSS - 0.2VDD Input leakage current IIL VIN = VDD or VSS -1.0 - +1.0 µA Output leakage current IOZ VIN = VDD or VSS -3.0 - +3.0 µA 50.688 56.32 61.952 kHz OSC1 - OSC2 26.496 29.44 32.384 kHz OSC3 - OSC4 2Vr = |(+VR)- (-VR)| VM Driving voltage input range Input voltage Output voltage Oscillator Frequency Tolerance Oscillator Frequency Range VCC External power supply mode V V Normal or Partial 0 FOSC1 Partial 1 FOSC2 Normal or Partial 0 FOSC1 (*1) 35.200 70.400 kHz OSC1 - OSC2 Partial 1 FOSC2 (*2) 18.400 36.800 kHz OSC3 - OSC4 3.3 1.65 V Driving voltage input range R1=? (fFR=80Hz target), DSG=0, 128 display lines R1=? (fFR=80Hz target), DSG=0, 66 display lines V1 2.0 VM 1.0 - (*1) Minimum oscillator frequency range is defined at fFR=50Hz and display line number=128 Maximum oscillator frequency range is defined at fFR=100Hz and display line number=128 (*2) Minimum oscillator frequency range is defined at fFR=50Hz and display line number=66 Maximum oscillator frequency range is defined at fFR=100Hz and display line number=66 53 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC CHARACTERISTICS (2) (Vss = 0V, VDD = 1.8 to 3.3V, VIN1=2.4 to 3.6V, Ta = -30 to 70 °C) Item Symbol Condition Min Typ Max Unit Remarks SEG RON-Seg V1=3.3 V, VM=1.65V, V0=0V, Ta = 25°C, Iload=100uA - 1.5 3.0 kΩ SEGn COM RON-Com - 1.0 1.5 kΩ COMn - 400 - µΑ - 270 - µΑ Driver output resistance Normal Mode IDD1 Current consumption Partial1 Mode IDD2 VCC=12 V, VM=1.5V, VEE=-9.0V, Ta = 25°C, Iload=100uA VDD=3V VIN1=3.0V, V1=3.3V, Bias(1)=1/6, DC(1)=x1.5, Ta=25°C, Display line=128 DSG=0 (1dummy) fOSC1=49.3kHz (fFR=70Hz) Low current mode, No load, No access, All white pattern VDD=1.8V VIN1=3.0V, V1=3.3V, Bias(1)=1/6, DC(1)=x1.5, Ta=25°C, Display line=128 DSG=0 (1dummy) fOSC1=49.3kHz (fFR=70Hz) Low current mode, No load, No access, All white pattern VDD=3V VIN1=3.0V, V1=3.3V, Bias(2)=1/6, DC(2)=x1.5, Ta=25°C, Display line=66 DSG=0 (1dummy) fOSC1=25.8kHz (fFR=70Hz) Low current mode, No load, No access, All white pattern VDD - 240 - µΑ - 180 - µΑ VDD=1.8V VIN1=3.0V, V1=3.3V, Bias(2)=1/6, DC(2)=x1.5, Ta=25°C, Display line=66 DSG=0 (1dummy) fOSC1=25.8kHz (fFR=70Hz) Low current mode, No load, No access, All white pattern * : “IDD1 and IDD2” are determined from lowest power consumption for dc-dc converter. 54 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC CHARACTERISTICS (3) Item (Vss = 0V, VDD = 1.8 to 3.3V, VIN1=2.4 to 3.6V, Ta = -30 to 70 °C) Condition Min Typ Max Unit Remarks Symbol ∆ (+VR) ∆ (V1) Voltage shift range(*1) ∆ (VM) ∆ (-VR) Low current mode Isource = 80uA High current mode Isource = 150 or 250uA Low current mode Isource = 250uA High current mode Isource = 500 or 1000uA Low current mode Isource,sink = 250uA High current mode Isource,sink = 500 or 1000uA Low current mode Isink = 80uA High current mode Isink = 150 or 250uA - - 100 mV +VR - - 20 mV V1 - - 20 mV VM - - 100 mV -VR (*1) Voltage shift means output voltage deference between output current = Iload and no-load. Refer to the following figure. (in case of source current mode) No-load Vx Vx Current = I Load Vy I=0 Vshift = |Vx-Vy| Vy I=ILoad Item Symbol Condition Min Typ Max Unit Remarks Tolerance of Bias ratio ∆ (+VR)_0 ∆ (-VR)_0(*1) No load -100 - +100 mV +VR -VR (*1) Tolerance of bias ratio definition ∆ (+VR)_0 = ((+VR) - VM ) – VM *6 ∆ (-VR)_0 = ( VM - (-VR)) – VM *6 55 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC CHARACTERISTICS (4) (Vss = 0V, VDD = 1.8 to 3.3V, VIN1=2.4 to 3.6V, Ta = -30 to 70 °C) Item Temperature compensation Tolerance of Contrast step of V1 Voltage range Symbol Condition Min Typ Max Unit Remarks ∆Vt VDD=VIN1=V1=3.0V, -20 to 70 °C -0.02 - +0.02 %/°C V1 2.539 5.078 7.617 mV V1 V1 3.25 3.3 3.35 V V1 VM 1.60 1.65 1.70 V VM V1 1.95 2.00 2.05 V V1 VM 0.95 1.00 1.05 V VM ∆Vstep Contrast set = FFh ∆V1 ∆VM Contrast set = 00h Condition Item Load current ||+VR-VM| -|VM -(-VR)|| Offset Voltage +VR I Load = +100uA (+VR) I Load = -100uA (-VR) A I Load = +100uA ( V1, VM ) B I Load = +100uA (+VR) I Load = -100uA (-VR) ||V1-VM| -|VM-V0|| +100uA +VR=7.0~11.55 V V1=2.0~3.3V VM=1.0~1.65V -VR=-8.25~-5 V V1 Vx Unit Ref 100 mV Fig.1 50 mV Fig.2 +100uA (both Case A and B) Va |Vx-Vy| < 100mV VM Max Voltage range -100uA (Case B) VM +100uA (Case A) Vy -VR Vb -100uA Fig. 1: Offset voltage definition (+VR,VM,-VR) V0 |Va-Vb| < 50mV Fig. 2: Offset voltage definition (V1,VM,V0) 56 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC CHARACTERISTICS (5) (Vss = 0V, VDD = 1.8 to 3.3V, VIN1=2.4 to 3.6V, Ta = -30 to 70 °C) Range Item Voltage Level Min Max (DC(1) and DC(2) = X1.5) V1OUT 2.0 V 3.3 V(*1) VMOUT 1.0 V 1.65 V(*2) DC2OUT 1.67 V 2.75 V(*3) (*1) This definition is shown as below VIN45 V1OUT Output VIN45 ΔV V1OUT Δ V > 0.3 V (External VIN45) VIN45 VIN45 - ΔV Fig. 1 Δ V > 0.5 V (VIN45 = VOUT45) If V1OUT input voltage is set over VIN45, V1OUT output voltage must be clipped near VIN45. In this case, V1OUT output level must not be unstable. Refer to Fig.1 (*2) This definition is shown as below VIN1 V1OUT Input VMOUT Output VIN1 ΔV VMOUT Δ V > 0.3 V If VMOUT input voltage is set over VIN1, VMOUT output voltage must be clipped near VIN1. In this case, VMOUT output level must not be unstable. Refer to Fig.2 (*3) This definition is shown as below VIN2 VIN1 VIN1 - ΔV Fig. 2 VMOUT Input DC2OUT Output VIN2 ΔV DC2OUT Δ V > 0.3 V (External VIN2) Δ V > 0.5 V (VIN2 = VOUT45) If DC2OUT input voltage is set over VIN2, DC2OUT output voltage must be clipped near VIN2. In this case, VMOUT output level must not be unstable. Refer to Fig.3 VIN2 - ΔV VIN2 DC2OUT Input Fig.3 57 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD AC CHARACTERISTICS Read / Write Characteristics (8080-series MPU) D/I tAS80 tAH80 /CS1 (CS2) tCY80 tPW L80(R), 0.9V DD /RD, /WR tPWL80(W) tPWH80(R), tPW H80(W) 0.1V DD tDS80 tDH80 DB0 to DB7 (Write) tACC80 tOD80 DB0 to DB7 (Read) ** tPWL80(W) and tPWL80(R) is specified in the overlapped period when CS1B is low (CS2 is high) and /WR(/RD) is low. Figure 27. Parallel Interface (8080-series MPU) Timing Diagram Table 17. AC Characteristics (8080-series Parallel Mode) (VDD = 1.8 to 3.3V, Ta = -30 to +70°C) Min. Max. Unit Item Signal Symbol Condition Address setup time Address hold time D/I tAS80 tAH80 1.8V/3.3V 0 1.8V/3.3V 0 tCY80 1.8V 470 3.3V 180 System cycle time Pulse width low for write Pulse width High for write /WR (/WR) tPWLW tPWHW 1.8V 160 3.3V 70 Pulse width low for read Pulse width high for read /RD tPWLR tPWHR 1.8V 160 3.3V 70 tDS80 tDH80 1.8V/3.3V 70/35 1.8V/3.3V 15/10 tACC80 tOD80 1.8V/3.3V 170/90 CL = 100 pF - Data setup time Data hold time Read access time Output disable time (/RD) DB0 to DB15 - ns ns - ns - ns - ns - ns NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 10 ns or less. (tr + tf) < (tCY80 - tPWLW - tPWHW ) for write, (tr + tf) < (tCY80 - tPWLR - tPWHR ) for read 58 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Read / Write Characteristics (6800-series Microprocessor) D/I,R/W tAS68 tAH68 /CS1 (CS2) tCY68 tEW H68(R), tEWH68(W) E t EWL68(R), tEWL68(W) 0.9VDD 0.1VDD tDS68 tDH68 DB0 to DB7 (Write) tACC68 tOD68 DB0 to DB7 (Read) ** tEWH68(W) and t EWH68(R) is specified in the overlapped period when /CS1 is low (CS2 is high) and E is high. Figure 28. Parallel Interface (6800-series MPU) Timing Diagram Table 18. AC Characteristics (6800-series Parallel Mode) (V DD = 1.8 to 3.3V, Ta = -30 to +70°C) Item Signal Symbol Condition Min. Max. Unit Address setup time Address hold time D/I R/W tAS68 tAH68 1.8V/3.3V 0 1.8V/3.3V 0 - ns tCY68 1.8V 470 - 3.3V 180 - ns - ns - ns System cycle time Enable width high for write Enable width low for write /RD (E) tEWHW tEWLW 1.8V 160 3.3V 70 Enable width high for read Enable width low for read /RD (E) tEWHR tEWLR 1.8V 160 3.3V 70 tDS68 tDH68 1.8V/3.3V 70/35 1.8V/3.3V 15/10 TACC68 tOD68 1.8V/3.3V 170/90 - CL = 100 pF - - Data setup time Data hold time Read access time Output disable time DB0 to DB15 ns ns NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 10 ns or less. (tr + tf) < (tCY68 - tEWHW - tEWLW ) for write, (tr + tf) < (tCY68 - tEWHR - tEWLR ) for read 59 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Serial Data Interface Timing t CSS /CS1 t SCYC (CS2) 0.1VDD t CSH 0.1VDD tSHW tr tSLW SCL tf t SAS tSAH D/I t SDS SDI tSDH 0.9VDD 0.9VDD 0.1VDD 0.1VDD Table 19. Serial Data Interface Timing (V DD = 1.8 to 3.3V, Ta = -30 to +70°C) Item Signal Symbol SCL Cycle Time SCL tCSC 50 us SCL High Pulse Width SCL tSHW 20 ns SCL Low Pulse Width SCL tSLW 20 ns SDI Setup time SDI tSDS 20 ns SDI Hold time SDI tSDH 20 ns D/I Setup time D/I tSAS 20 ns D/I Hold time D/I tSAH 20 ns tCSS 20 ns tCHS 20 ns Chip Select Setup time Chip Select Hold time /CS1 (CS2) /CS1 (CS2) Condition Min. Max. Unit 60 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Reset Input Timing tRW /RST tR During reset Internal status Reset complete Figure 29. Reset Input Timing Diagram Table 20. AC Characteristics (Reset mode) (V DD = 1.8 to 3.3V, Ta = -30 to +70°C) Item Signal Symbol Reset low pulse width /RST Reset time - Condition Min. Max. Unit tRW 1000 - ns tR - 1000 ns 61 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD SYSTEM APPLICATION DIAGRAM Internal Power Mode External Components Name R1,R2 C1,C2,C3 D1 VDD VDD or REG_OUT VDD1 REG_OUT C1 VSS MPU Values of external Capacitors and D1 Item Capacitance C1 C2 C3 1.0 to 4.7µF 1.0 to 2.2µF 1.0 to 2.2µF Vforward = Max. 0.3V at 1mA Vreverse = Min. 15V DB15 to DB0 DB15DB0 /RD /RD /WR /WR /CS1 /CS1 CS2 CS2 D/I D/I D1 Maximum rating voltage of capacitors Maximum Item rating voltage R1 OSC1 R2 REG_OUT to VSS VOUT45 to VSS C11P to C11M C12P to C12M VMOUT to VSS DC2OUT to VSS V1OUT to VSS C21P to C21M C22P to C22M C23P to C23M VSS to VRN C31P to C31M VRP to VSS OSC2 OSC3 OSC4 OSC5 S6B33A2 VIN1 VIN1 C2 C2 C3 Device Resistors Capacitors Schottky barrier diode 3V 8V 6V 6V 3V 5V 6V 5V 10V 13V 13V 17V 18V VIN2 C11P C11M VIN2 C12P DC2OUT C12M DC2IN VOUT45 C21P VIN45 C21M C3 C2 C22P C22M V1OUT C3 V1IN VMOUT C3 C23P C2 C2 C23M VRN VEE C3 VMIN C31P V0IN C31M C2 VRP VCC C3 62 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD External Power Mode VDD VDD1 VDD or REG_OUT REG_OUT C VSS DB15 to DB0 DB15 to DB0 MPU /RD /RD /WR /WR /CS1 /CS1 CS2 CS2 D/I D/I R1 R2 OSC1 OSC2 OSC3 OSC4 OSC5 VIN1 VIN1 S6B33A2 00 VIN2 VIN2 C11P DC2OUT C11M DC2IN C12P C12M C21P C21M VOUT45 VIN45 C22P C22M C23P C23M V1IN V1OUT V1IN VMIN VMOUT VRN VEE VEE VMIN V0IN C31P C31M VRP VCC VCC 63