DRV8823 www.ti.com SLVS913D – JANUARY 2009 – REVISED JANUARY 2010 4-BRIDGE SERIAL INTERFACE MOTOR DRIVER Check for Samples: DRV8823 FEATURES 1 • PWM motor Driver with Four H-Bridges – Drives Two Stepper Motors, One Stepper and Two DC Motors, or Four DC Motors – Up to 1.5-A Current Per Winding – Low On-Resistance – Programmable Maximum Winding Current – Three-Bit Winding Current Control Allows up to Eight Current Levels – Selectable Slow or Mixed Decay Modes 8-V to 32-V Operating Supply Voltage Range Internal Charge Pump for Gate Drive Built-in 3.3-V Reference 2 • • • • • • Serial Digital Control Interface Fully Protected Against Undervoltage, Overtemperature, and Overcurrent Thermally Enhanced Surface Mount Package APPLICATIONS • • • • • • Printers Scanners Office Automation Machines Gaming Machines Factory Automation Robotics DESCRIPTION/ORDERING INFORMATION The DRV8823 provides an integrated motor driver solution for printers and other office automation equipment applications. The motor driver circuit includes four H-bridge drivers. Each of the motor driver blocks employ N-channel power MOSFETs configured as an H-bridge to drive the motor windings. A simple serial interface allows control of all functions of the motor driver with only a few digital signals. A low-power sleep function is also provided. The motor drivers provide PWM current control capability. The current is programmable, based on an externally supplied reference voltage and an external current sense resistor. In addition, eight current levels (set via the serial interface) allow microstepping with bipolar stepper motors. Internal shutdown functions are provided for over current protection, short circuit protection, under voltage lockout and overtemperature. The DRV8823 is packaged in a 48 pin HTSSOP package (Eco-friendly : RoHS & no Sb/Br). ORDERING INFORMATION (1) TA –40°C to 85°C (1) (2) PACKAGE (2) PowerPad™ (HTSSOP) - DCA ORDERABLE PART NUMBER Reel of 2000 DRV8823DCAR Tube of 40 DRV8823DCA TOP-SIDE MARKING DRV8823 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPad, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2010, Texas Instruments Incorporated DRV8823 SLVS913D – JANUARY 2009 – REVISED JANUARY 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM CP1 Dig. VCC V3P3 Charge Pump and Gate Drive Regulator 3.3V Regulator 0.47uF 6.3V CP2 0.01uF 35V +24 VCP VGD 0.1uF 16V +24 VCP VM ABVREF AOUT1 PWM H-bridge driver A Step Motor AOUT2 AISEN +24 VM SDATA BOUT1 PWM H-bridge driver B SCLK BOUT2 SCS SSTB Serial Interface & Logic BISEN +24 RESETn VM SLEEPn COUT1 PWM H-bridge driver C Step Motor COUT2 CISEN +24 VM DOUT1 PWM H-bridge driver D CDVREF DOUT2 DISEN OCP Thermal Shut down Oscillator UVLO RESET GND 2 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): DRV8823 DRV8823 www.ti.com SLVS913D – JANUARY 2009 – REVISED JANUARY 2010 TERMINAL FUNCTIONS NAME NO. I/O (1) DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS POWER AND GROUND VM (4 pins) 1, 2, 23, 24 - Motor supply voltage (multiple pins) Connect all VM pins together to motor supply voltage. Bypass to GND with several 0.1-mF, 35-V ceramic capacitors. V3P3 16 - 3.3 V regulator output Bypass to GND with 0.47-mF, 6.3-V ceramic capacitor. GND 10 - 15, 34 - 39 - Power ground (multiple pins) Connect all PGND pins to GND and solder to copper heatsink areas. CP1 7 IO CP2 8 IO Charge pump flying capacitor Connect a 0.01-mF capacitor between CP1 and CP2 VCP 9 IO Charge pump storage capacitor Connect a 0.1-mF, 16 V ceramic capacitor to VM Sets current trip threshold. MOTOR DRIVERS ABVREF 17 I Bridge A & B current set reference voltage AOUT1 5 O Bridge A output 1 AOUT2 3 O Bridge A output 2 Connect to first coil of bipolar stepper motor 1, or DC motor winding. ISENA 4 - Bridge A current sense Connect to current sense resistor for bridge A. BOUT1 48 O Bridge B output 1 BOUT2 46 O Bridge B output 2 Connect to second coil of bipolar stepper motor 1, or DC motor winding. ISENB 47 - Bridge B current sense Connect to current sense resistor for bridge B. Sets current trip threshold. CDVREF 18 I Bridge C & D current set reference voltage COUT1 27 O Bridge C output 1 COUT2 25 O Bridge C output 2 ISENC 26 - Bridge C current sense Connect to current sense resistor for bridge C. DOUT1 22 O Bridge D output 1 DOUT2 20 O Bridge D output 2 Connect to second coil of bipolar stepper motor 2, or DC motor winding. ISEND 22 - Bridge D current sense Connect to current sense resistor for bridge D. Connect to first coil of bipolar stepper motor 2, or DC motor winding. SERIAL INTERFACE SDATA 31 I Serial data input Data is clocked in on rising edge of SCLK. SCLK 33 I Serial input clock Logic high enables serial data to be clocked in. SCS 45 I Serial chip select Logic high latches serial data. SSTB 30 I Serial data strobe Active low resets serial interface and disables outputs. RESETn 43 I Reset input Active low input disables outputs and charge pump. SLEEPn 42 I Sleep input 19, 28, 29, 32 I Test inputs TEST PINS TEST (1) Do not connect these pins - used for factory test only. Directions: I = input, O = output, OZ = 3-state output, OD = open-drain output, IO = input/output, PU = internal pullup Logic inputs To logic ESD Hysteresis Internal pulldown Figure 1. Logic Inputs Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): DRV8823 3 DRV8823 SLVS913D – JANUARY 2009 – REVISED JANUARY 2010 www.ti.com DCA PACKAGE VM VM AOUT2 AISEN AOUT1 NC CP1 CP2 VCP PGND PGND Solder these PGND pins to copper PGND heatsink area PGND PGND V3P3 ABVREF CDVREF TEST DOUT2 DISEN DOUT1 VM VM ABSOLUTE MAXIMUM RATINGS (1) 1 2 3 48 47 46 4 5 45 44 6 43 7 8 42 41 9 10 40 39 11 12 13 38 37 36 14 15 35 34 16 17 33 32 18 19 20 31 30 29 21 28 27 22 23 24 26 25 BOUT1 BISEN BOUT2 SCS NC RESETn SLEEPn NC NC PGND PGND Solder these PGND pins to copper PGND heatsink area PGND PGND SCLK TEST SDATA SSTB TEST TEST COUT1 CISEN COUT2 (2) over operating free-air temperature range (unless otherwise noted) VM Power supply voltage range –0.3 to 34 V VI Logic input voltage range (3) –0.5 to 5.75 V IO(peak) Peak motor drive output current, t < 1 ms IO Motor drive output current (4) PD Continuous total power dissipation TJ Operating virtual junction temperature range –40 to 150 °C TA Operating ambient temperature range –40 to 85 °C Tstg Storage temperature range –60 to 150 °C (1) (2) (3) (4) Internally limited 1.5 A See Dissipation Ratings Table Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Input pins may be driven in this voltage range regardless of presence or absence of VM. Power dissipation and thermal limits must be observed. DISSIPATION RATINGS RqJA DERATING FACTOR ABOVE TA = 25°C TA < 25°C TA = 70°C TA = 85°C Low-K (1) 75.7°C/W 13.2 mW/°C 1.65 W 1.06 W 0.86 W Low-K (2) 32°C/W 31.3 mW/°C 3.91 W 2.50 W 2.03 W 30.3°C/W 33 mW/°C 4.13 W 2.48 W 2.15 W 22.3°C/W 44.8 mW/°C 5.61 W 3.59 W 2.91 W BOARD High-K (3) High-K (1) (2) (3) (4) 4 (4) PACKAGE DCA The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with no backside copper. The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with 25-cm2 2-oz copper on back side. The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with no backside copper and solid 1-oz internal ground plane. The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with 25-cm2 1-oz copper on back side and solid 1-oz internal ground plane. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): DRV8823 DRV8823 www.ti.com SLVS913D – JANUARY 2009 – REVISED JANUARY 2010 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VM Motor power supply voltage range IMOT Continuous motor drive output current (1) VREF VREF input voltage (1) NOM 8 MAX UNIT 32 V 1.5 A 4 V TYP MAX UNIT 1 1 Power dissipation and thermal limits must be observed. ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN POWER SUPPLIES IVM VM operating supply current VM = 24 V, no loads 5 8 mA VUVLO VM undervoltage lockout voltage VM rising 6.5 8 V VCP Charge pump voltage Relative to VM 12 VV3P3 VV3P3 output voltage 3.20 3.30 V 3.40 V 0.7 V LOGIC-LEVEL INPUTS (INTERNAL PULLDOWNS) VIL Input low voltage VIH Input high voltage VHYS Input hysteresis IIN Input current (internal pulldown current) 2 0.3 V 0.45 VIN = 3.3 V 0.6 V 100 mA OVERTEMPERATURE PROTECTION TTSD Thermal shutdown temperature Die temperature 150 °C MOTOR DRIVERS Rds(on) Motor #1 FET on resistance (each individual FET) VM = 24 V, IO = 0.8 A, TJ = 25°C 0.25 VM = 24 V, IO = 0.8 A, TJ = 85°C 0.31 Rds(on) Motor #2 FET on resistance (each individual FET) VM = 24 V, IO = 0.8 A, TJ = 25°C 0.30 VM = 24 V, IO = 0.8 A, TJ = 85°C 0.38 IOFF Off-state leakage current fPWM Motor PWM frequency (1) tBLANK ITRIP blanking time (2) tF Output fall time 50 300 ns tR Output rise time 50 300 ns IOCP Overcurrent protect level 1.5 4.5 A tOCP Overcurrent protect trip time tMD Mixed decay percentage 45 50 0.37 0.45 mA 55 kHz ms 2.5 Measured from beginning of PWM cycle Ω ±12 3.75 3 Ω ms 75 % CURRENT CONTROL IREF xVREF input current ΔICHOP (1) (2) Chopping current accuracy xVREF = 3.3 V –3 3 xVREF = 2.5 V, derived from V3P3; 71% 100% current –5 5 xVREF = 2.5 V, derived from V3P3; 20% 56% current –10 10 mA % Factory option 100 kHz. Factory options for 2.5 ms, 5 ms or 6.25 ms. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): DRV8823 5 DRV8823 SLVS913D – JANUARY 2009 – REVISED JANUARY 2010 www.ti.com TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT 1 tCYC Clock cycle time 62 ns 2 tCLKH Clock high time 25 ns 3 tCLKL Clock low time 25 ns 4 tSU(SDATA) Setup time, SDATA to SCLK 5 ns 5 tH(DATA) Hold time, SDATA to SCLK 1 ns 6 tSU(SCS) Setup time, SCS to SCLK 5 ns 7 tH(SCS) Hold time, SCS to SCLK 1 ns 1 SCLK 2 3 SDATA Data in valid 4 5 6 7 SCS 6 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): DRV8823 DRV8823 www.ti.com SLVS913D – JANUARY 2009 – REVISED JANUARY 2010 FUNCTIONAL DESCRIPTION PWM Motor Drivers The DRV8823 contains four H-bridge motor drivers with current-control PWM circuitry. A block diagram showing drivers A and B of the motor control circuitry (as typically used to drive a bipolar stepper motor) is shown below. Drivers C and D are the same as A and B (though the rds(on) of the output FETs is different). VM OC P VM VC P, VGD A OU T1 From Serial Interface Predrive AEN B L Step Motor APH A SE A OU T2 A BD EC A Y PW M OC P A I[2:0] 3 + A I[2:0] ISEN A A =5 DAC 3 A BVR EF VM OC P VM V CP, VGD BOU T1 Predrive B EN BL B OU T2 BPH A SE PW M OC P ISEN B + B I[2:0] A =5 DAC 3 Figure 2. Block Diagram Note that there are multiple VM motor power supply pins. All VM pins must be connected together to the motor supply voltage. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): DRV8823 7 DRV8823 SLVS913D – JANUARY 2009 – REVISED JANUARY 2010 www.ti.com Bridge Control The xENBL bits in the serial interface registers enable current flow in each H-bridge when set to "1". The xPHASE bits in the serial interface registers control the direction of current flow through each H-bridge. The following table shows the logic: xPHASE xOUT1 xOUT2 1 H L 0 L H Current Regulation The motor driver employs fixed-frequency PWM current regulation (also called "current chopping"). When a winding is activated, the current through it rises until it reaches a threshold, then the current is switched off until the next PWM period. The PWM frequency is fixed at 50 kHz. It may also be set to 100 kHz via factory option. The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input from the VREF pin. The full-scale (100%) chopping current is calculated as follows: 5 (1) Example: If a 0.5-Ω sense resistor is used and the VREFx pin is 2.5 V, the full-scale (100%) chopping current is 2.5 V/(5 * 0.5 Ω) = 1 A. Three serial interface register bits per H-bridge (xI2, xI1 and xI0) are used to scale the current in each bridge as a percentage of the full-scale current set by the VREF input pin and sense resistance. The function of the bits is shown below: xI2 xI1 xI0 Relative Current (% full-scale chopping current) 0 0 0 20 0 0 1 38 0 1 0 56 0 1 1 71 1 0 0 83 1 0 1 92 1 1 0 98 1 1 1 100 Blanking Time After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time before enabling the current sense circuitry. This blanking time is fixed at 3.75 ms. Note that the blanking time also sets the minimum on time of the PWM. 8 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): DRV8823 DRV8823 www.ti.com SLVS913D – JANUARY 2009 – REVISED JANUARY 2010 Decay Mode During PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 3 as case 1. The current flow direction shown indicates positive current flow in the step table below. Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay. In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast-decay mode is shown in Figure 3 as case 2. In slow-decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is shown in Figure 3 as case 3. VM 1 Drive current 1 xOUT2 xOUT1 3 2 Fast decay (reverse) 3 Slow decay (brake) 2 Figure 3. Decay Mode The DRV8823 supports slow decay and also a mixed decay mode. Mixed decay mode begins as fast decay, but at a fixed period of time (75% of the PWM cycle) switches to slow decay mode for the remainder of the fixed PWM period. Slow or mixed decay mode is selected by the state of the xDECAY bits in the serial interface registers. If the xDECAY bit is 0, slow decay is selected. If the xDECAY bit is 1, mixed decay is selected. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): DRV8823 9 DRV8823 SLVS913D – JANUARY 2009 – REVISED JANUARY 2010 www.ti.com Protection Circuits The DRV8823 is fully protected against undervoltage, overcurrent and overtemperature events. Overcurrent Protection (OCP) All of the drivers in DRV8823 are protected with an OCP (Over-Current Protection) circuit. The OCP circuit includes an analog current limit circuit, which acts by removing the gate drive form each output FET if the current through it exceeds a preset level. This circuit will limit the current to a level that is safe to prevent damage to the FET. A digital circuit monitors the analog current limit circuits. If any analog current limit condition exists for longer than a preset period, all drivers in the device will be disabled. The device is re-enabled upon the removal and re-application of power at the VM pins. Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all drivers in the device will be shut down. The device will remain disabled until the die temperature has fallen to a safe level. After the temperature has fallen, the device may be re-enabled upon the removal and re-application of power at the VM pin. Undervoltage Lockout (UVLO) If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled. Operation will resume when VM rises above the UVLO threshold. The indexer logic will be reset to its initial condition in the event of an undervoltage lockout. Shoot-Through Current Prevention The gate drive to each FET in the H-bridge is controlled to prevent any cross-conduction (shoot through current) during transitions. Serial Data Transmission Data transfers consist of sixteen bits of serial data, shifted into the SDATA pin LSB first. On serial writes to DRV8823, additional clock edges following the final data bit will continue to shift data bits into the data register; therefore, the last 16 bits presented will be latched and used. One of two registers is selected by setting bits in an address field in the four upper bits in the serial data transferred (ADDR in the tables below). One 16-bit register is used to control motor #1 (bridges A & B), and a second 16-bit register is used to control motor 2 (bridges C & D). Data can only be transferred into the serial interface if the SCS input pin is active high. Data is initially clocked in to a temporary holding register. This data is latched into the motor driver on the rising edge of the SSTB pin. If the SSTB pin is tied high at all times, the data will be latched in after all 16 bits have been transferred. 10 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): DRV8823 DRV8823 www.ti.com SLVS913D – JANUARY 2009 – REVISED JANUARY 2010 Data Format Table 1. Motor 1 Command (Bridges A & B) D15 D12 Bit Name D11 ADDR BDECAY (= 0000) Reset Value x D10 D9 D8 B12 B11 B10 0 0 0 0 D7 D6 D5 BPHASE BENBL ADECAY 0 0 D4 D3 D2 A12 A11 A10 0 0 0 0 0 0 D1 D0 APHASE AENBL Table 2. Motor 2 Command (Bridges C & D) Bit D15 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name ADDR (= 0001) DDECAY D12 D11 D10 DPHASE DENBL CDECAY C12 C11 C10 CPHASE CENBL Reset Value x 0 0 0 0 0 0 0 0 0 0 0 0 Serial Data Timing SCS Note 1 SCLK Note 2 SDATA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D 10 D11 D12 D13 D14 D 15 SSTB Figure 4. Serial Data Timing Diagram Note 1: Any amount of time is allowed between clocks, or groups of clocks, as long as SCS stays active. This allows 8- or 16-bit transfers. Note 2: If more than 16 clock edges are presented while transferring data (while SCS is still high), data will continue to be shifted into the data register. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): DRV8823 11 DRV8823 SLVS913D – JANUARY 2009 – REVISED JANUARY 2010 www.ti.com THERMAL INFORMATION Thermal Protection The DRV8823 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 150°C, the device will be disabled until the temperature drops to a safe level. Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. Power Dissipation Power dissipation in the DRV8823 is dominated by the power dissipated in the output FET resistance, or RDS(ON). Average power dissipation when running a stepper motor can be roughly estimated by Equation 2. PTOT = 4 · RDS(ON) · (IOUT(RMS)) 2 (2) where PTOT is the total power dissipation, RDS(ON) is the resistance of each FET, and IOUT(RMS) is the RMS output current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7x the full-scale output current setting. The factor of 4 comes from the fact that there are two motor windings, and at any instant two FETs are conducting winding current for each winding (one high-side and one low-side). Remember that the DRV8823 has two stepper motor drivers, so the power dissipation of each must be added together to determine the total device power dissipation. The maximum amount of power that can be dissipated in the DRV8823 is dependent on ambient temperature and heatsinking. The thermal dissipation ratings table in the datasheet can be used to estimate the temperature rise for typical PCB constructions. Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink. Heatsinking The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers. For details about how to design the PCB, refer to TI application report SLMA002, " PowerPAD™ Thermally Enhanced Package" and TI application brief SLMA004, " PowerPAD™ Made Easy", available at www.ti.com. In general, the more copper area that can be provided, the more power can be dissipated. Figure 5 shows thermal resistance vs. copper plane area for both a single-sided PCB with 2-oz copper heatsink area, and a 4-layer PCB with 1-oz copper and a solid ground plane. Both PCBs are 76 mm x 114 mm, and 1.6 mm thick. It can be seen that the heatsink effectiveness increases rapidly to about 20 cm2, then levels off somewhat for larger areas. Six pins on the center of each side of the package are also connected to the device ground. A copper area can be used on the PCB that connects to the PowerPAD™ as well as to all the ground pins on each side of the device. This is especially useful for single-layer PCB designs. 12 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): DRV8823 DRV8823 www.ti.com SLVS913D – JANUARY 2009 – REVISED JANUARY 2010 70 65 Thermal Resistance (RqJA) - °C/W 60 55 50 45 Low-K PCB (2 layer) 40 35 30 High-K PCB (4 layer with ground plane) 25 20 0 10 20 30 40 50 60 70 80 90 2 Backside Copper Area - cm Figure 5. Thermal Resistance vs. Copper Plane Area Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): DRV8823 13 PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) DRV8823DCA ACTIVE HTSSOP DCA 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV8823DCAR ACTIVE HTSSOP DCA 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV8823DCAR Package Package Pins Type Drawing SPQ HTSSOP 2000 DCA 48 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.8 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8823DCAR HTSSOP DCA 48 2000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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