STMICROELECTRONICS STFV4N150

STFV4N150
N-CHANNEL 1500V - 5Ω - 4A TO-220FH
Very High Voltage PowerMESH™ MOSFET
Figure 1: Package
Table 1: General Features
TYPE
STFV4N150
■
■
■
■
■
■
■
VDSS
RDS(on)
ID
Pw
1500 V
<7Ω
4A
40 W
TYPICAL RDS(on) = 5 Ω
AVALANCHE RUGGEDNESS
GATE CHARGE MINIMIZED
VERY LOW INTRINSIC CAPACITANCES
HIGH SPEED SWITCHING
FULLY PLASTIC TO-220 PACKAGE
CREEPAGE DISTANCE PATH IS > 4mm
DESCRIPTION
Using the well consolidated high voltage MESH
OVERLAY™ process, STMicroelectronics has designed an advanced family of Power MOSFETs
with outstanding performances. The strengthened
layout coupled with the Company’s proprietary
edge termination structure, gives the lowest
RDS(on) per area, unrivalled gate charge and
switching characteristics. The creepage path is
what makes this package unique from TO-220FP.
The creepage distance path between each lead
and between the leads and the heatsink has been
increased to >4.0mm, making this package met all
stringent safety norms in high voltage applications.
TO-220FH
Figure 2: Internal Schematic Diagram
APPLICATIONS
■ SWITCH MODE POWER SUPPLIES
Table 2: Order Codes
SALES TYPE
MARKING
PACKAGE
PACKAGING
STFV4N150
FV4N150
TO-220FH
TUBE
Rev. 1
July 2005
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STFV4N150
Table 3: Absolute Maximum ratings
Symbol
VDS
VDGR
VGS
Parameter
Value
Unit
Drain-source Voltage (VGS = 0)
1500
V
Drain-gate Voltage (RGS = 20 kΩ)
1500
V
Gate- source Voltage
± 30
V
ID
Drain Current (continuous) at TC = 25°C
4
A
ID
Drain Current (continuous) at TC = 100°C
2.5
A
Drain Current (pulsed)
12
A
Total Dissipation at TC = 25°C
40
W
0.32
W/°C
-55 to 150
°C
IDM ()
PTOT
Derating Factor
Tj
Tstg
Operating Junction Temperature
Storage Temperature
( ) Pulse width limited by safe operating area
(*) Limited only by maximum temperature allowed
Table 4: Thermal Data
Rthj-case
Thermal Resistance Junction-case Max
3.12
°C/W
Rthj-amb
Thermal Resistance Junction-ambient Max
62.5
°C/W
Max Value
Unit
4
A
350
mJ
Table 5: Avalanche Characteristics
Symbol
Parameter
IAR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max)
EAS
Single Pulse Avalanche Energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)
Table 6: On /Off
Symbol
Parameter
Test Conditions
Drain-source
Breakdown Voltage
ID = 1 mA, VGS = 0
IDSS
Zero Gate Voltage
Drain Current (VGS = 0)
VDS = Max Rating
VDS = Max Rating,TC = 125°C
IGSS
Gate-body Leakage
Current (VDS = 0)
VGS = ± 30 V
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static Drain-source On
Resistance
VGS = 10 V, ID = 2 A
V(BR)DSS
2/10
Min.
Typ.
Max.
1500
3
Unit
V
10
500
µA
µA
± 100
nA
4
5
V
5
7
Ω
STFV4N150
ELECTRICAL CHARACTERISTICS (CONTINUED)
Table 7: Dynamic
Symbol
gfs (1)
Parameter
Test Conditions
Forward Transconductance
VDS = 30 V , ID = 2 A
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
td(on)
tr
td(off)
tf
Qg
Qgs
Qgd
Min.
Typ.
Max.
Unit
3.5
S
VDS = 25 V, f = 1 MHz,
VGS = 0
1300
120
12
pF
pF
pF
Turn-on Delay Time
Rise Time
Turn-off-Delay Time
Fall Time
VDD = 750 V, ID = 2 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 17)
35
30
45
45
ns
ns
ns
ns
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 600 V, ID = 4 A,
VGS = 10 V
(see Figure 20)
30
10
9
50
nC
nC
nC
Typ.
Max.
Unit
4
12
A
A
2
V
Table 8: Source Drain Diode
Symbol
Parameter
ISD
ISDM (2)
Source-drain Current
Source-drain Current (pulsed)
VSD (1)
Forward On Voltage
ISD = 4 A, VGS = 0
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 4 A, di/dt = 100 A/µs
VDD = 45V
(see Figure 18)
510
3
12
ns
µC
A
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 4 A, di/dt = 100 A/µs
VDD = 45V, Tj = 150°C
(see Figure 18)
650
4
12.6
ns
µC
A
trr
Qrr
IRRM
trr
Qrr
IRRM
Test Conditions
Min.
(1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(2) Pulse width limited by safe operating area.
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STFV4N150
Figure 3: Safe Operating Area
Figure 6: Thermal Impedance
Figure 4: Output Characteristics
Figure 7: Transfer Characteristics
Figure 5: Transconductance
Figure 8: Static Drain-source On Resistance
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STFV4N150
Figure 9: Gate Charge vs Gate-source Voltage
Figure 12: Capacitance Variations
Figure 10: Normalized Gate Thereshold Voltage vs Temperature
Figure 13: Normalized On Resistance vs Temperature
Figure 11: Source-Drain Diode Forward Characteristics
Figure 14: Normalized BVdss vs Temperature
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STFV4N150
Figure 15: Maximum Avalanche Energy vs
Temperature
6/10
STFV4N150
Figure 16: Unclamped Inductive Load Test Circuit
Figure 19: Unclamped Inductive Waveform
Figure 17: Switching Times Test Circuit For
Resistive Load
Figure 20: Gate Charge Test Circuit
Figure 18: Test Circuit For Inductive Load
Switching and Diode Recovery Times
7/10
STFV4N150
TO-220FH (Fully plastic High voltage) MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
4.4
4.6
0.173
0.181
B
2.5
2.7
0.098
0.106
D
2.5
2.75
0.098
0.108
E
0.45
0.7
0.017
0.027
F
0.75
1
0.030
0.039
F1
1.3
1.8
0.051
0.070
F2
1.3
1.8
0.051
0.070
G
4.95
5.2
0.195
0.204
G1
2.4
2.7
0.094
0.106
H
10
10.4
0.393
L2
16
L3
28.6
30.6
1.126
L4
9.8
10.6
0.385
L5
0.409
0.630
3.4
1.204
0.417
0.134
L6
15.9
16.4
0.626
0.645
L7
9
9.3
0.354
0.366
L8
14.5
15
0.570
L9
2.4
0.590
0.094
P011W
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STFV4N150
Table 9: Revision History
Date
Revision
07-Jul-2005
1
Description of Changes
First release.
9/10
STFV4N150
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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© 2005 STMicroelectronics - All Rights Reserved
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