VISHAY SI7392ADP

SPICE Device Model Si7392ADP
Vishay Siliconix
N-Channel Reduced Qg, Fast Switching WFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 73517
S-61151Rev. B, 26-Jun-06
www.vishay.com
1
SPICE Device Model Si7392ADP
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Simulated
Data
VGS(th)
VDS = VGS, ID = 250 µA
1.9
Measured
Data
Unit
Static
Gate Threshold Voltage
On-State Drain Current
a
Drain-Source On-State Resistancea
ID(on)
rDS(on)
V
VDS ≥ 5 V, VGS = 10 V
686
VGS = 10 V, ID = 12.5A
0.006
0.006
VGS = 4.5 V, ID = 10A
0.009
0.009
A
Ω
Forward Transconductancea
gfs
VDS = 15 V, ID = 12.5A
45
46
S
Diode Forward Voltagea
VSD
IS = 2.7A
0.73
0.73
V
1626
1465
360
360
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
VDS = 15 V, VGS = 0 V, f = 1 MHz
136
150
VDS = 15 V, VGS = 10 V, ID = 12.5A
22
25
11
12
VDS = 15 V, VGS = 4.5 V, ID = 12.5A
3.7
3.7
3.1
3.1
pF
nC
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com
2
Document Number: 73517
S-61151Rev. B, 26-Jun-06
SPICE Device Model Si7392ADP
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 73517
S-61151Rev. B, 26-Jun-06
www.vishay.com
3