SPICE Device Model Si6901DQ Vishay Siliconix Bi-Directional P-Channel 12-V (D-S) MOSFET CHARACTERISTICS • P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 72915 23-May-04 www.vishay.com 1 SPICE Device Model Si6901DQ Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Simulated Data VGS(th) VDS = VGS, ID = −250 µA 0.66 Measured Data Unit Static Gate Threshold Voltage On-State Drain Current b Drain-Source On-State Resistanceb Forward Transconductanceb ID(on) rDS(on) gfs V VDS = −5 V, VGS = −4.5 V 133 VGS = −4.5 V, ID = −5.4 A 0.027 0.026 VGS = −2.5 V, ID = −4.8 A 0.034 0.034 VGS = −1.8 V, ID = −3.5 A 0.045 0.046 VDS = −10 V, ID = −5.4 A 21 30 64 80 VDS = − 6 V, VGS = − 4.5 V, ID = − 5.4 A 10.5 10.5 34 34 A Ω S a Dynamic Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) 91 110 tr 230 310 354 210 46 270 Rise Time Turn-Off Delay Time Fall Time td(off) tf VDD = − 6 V, RL = 6 Ω ID ≅ − 1 A, VGEN = − 4.5 V, RG = 6 Ω nC ns Notes a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. www.vishay.com 2 Document Number: 72915 23-May-04 SPICE Device Model Si6901DQ Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 72915 23-May-04 www.vishay.com 3