PH3120L N-channel TrenchMOS logic level FET Rev. 03 — 30 March 2009 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits Higher operating power due to low thermal resistance Suitable for logic level gate drive sources Low conduction losses due to low on-state resistance 1.3 Applications DC-to-DC convertors Portable equipment Notebook computers Switched-mode power supplies 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - - 20 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1; see Figure 3 - - 100 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 62.5 W VGS = 4.5 V; ID = 50 A; VDS = 10 V; Tj = 25 °C; see Figure 11 - 12.8 - nC VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 9; see Figure 10 - 2.25 2.65 mΩ Dynamic characteristics QGD gate-drain charge Static characteristics RDSon drain-source on-state resistance PH3120L NXP Semiconductors N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D mb G S mbb076 1 2 3 4 SOT669 (LFPAK) 3. Ordering information Table 3. Ordering information Type number Package Name Description PH3120L LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads Version SOT669 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - 20 V VGS gate-source voltage -20 20 V ID drain current VGS = 10 V; Tmb = 25 °C; see Figure 1; see Figure 3 - 100 A VGS = 10 V; Tmb = 100 °C; see Figure 1 - 76 A IDM peak drain current tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3 - 300 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 62.5 W Tstg storage temperature -55 150 °C Tj junction temperature -55 150 °C Source-drain diode IS source current Tmb = 25 °C - 52 A ISM peak source current tp ≤ 10 µs; pulsed; Tmb = 25 °C - 152 A - 210 mJ Avalanche ruggedness EDS(AL)S non-repetitive VGS = 10 V; Tj(init) = 25 °C; ID = 46.2 A; Vsup ≤ 20 V; drain-source avalanche unclamped; tp = 0.32 ms; RGS = 50 Ω energy PH3120L_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 30 March 2009 2 of 12 PH3120L NXP Semiconductors N-channel TrenchMOS logic level FET 003aaa628 120 03aa15 120 I der (%) Pder (%) 80 80 40 40 0 0 0 Fig 1. 50 100 150 200 Tmb (°C) 0 50 100 150 200 Tmb (°C) Normalized continuous drain current as a function of mounting base temperature Fig 2. Normalized total power dissipation as a function of mounting base temperature 003aaa360 103 ID (A) Limit RDSon = VDS / ID 102 tp = 10 μ s 100 μ s 1 ms 10 ms DC 10 100 ms 1 10-1 1 102 10 VDS (V) Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PH3120L_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 30 March 2009 3 of 12 PH3120L NXP Semiconductors N-channel TrenchMOS logic level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - - 2 K/W 003aaa361 10 Zth(j-mb) (K/W) δ = 0.5 1 0.2 δ= P 0.1 0.05 0.02 tp T single pulse t tp T 10-1 10-5 Fig 4. 10-4 10-3 10-2 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration PH3120L_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 30 March 2009 4 of 12 PH3120L NXP Semiconductors N-channel TrenchMOS logic level FET 6. Characteristics Table 6. Symbol Characteristics Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage ID = 10 mA; VGS = 0 V; Tj = 25 °C 20 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 150 °C; see Figure 7; see Figure 8 0.65 - - V ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 7; see Figure 8 1 1.5 2 V VDS = 20 V; VGS = 0 V; Tj = 150 °C - - 500 µA VDS = 20 V; VGS = 0 V; Tj = 25 °C - 0.06 1 µA VGS = 15 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -15 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 9; see Figure 10 - 2.25 2.65 mΩ VGS = 4.5 V; ID = 25 A; Tj = 150 °C; see Figure 9; see Figure 10 - 5.1 6.3 mΩ VGS = 4.5 V; ID = 25 A; Tj = 25 °C; see Figure 9; see Figure 10 - 3 3.7 mΩ ID = 50 A; VDS = 10 V; VGS = 4.5 V; Tj = 25 °C; see Figure 11 - 48.5 - nC - 12.7 - nC - 12.8 - nC IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) tf VDS = 10 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 12 - 4457 - pF - 1480 - pF - 940 - pF - 34 - ns - 90 - ns turn-off delay time - 114 - ns fall time - 88 - ns VDS = 10 V; RL = 0.4 Ω; VGS = 4.5 V; RG(ext) = 4.7 Ω; Tj = 25 °C; ID = 25 A Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 13 - 0.77 1.2 V trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 20 V; Tj = 25 °C - 63 - ns PH3120L_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 30 March 2009 5 of 12 PH3120L NXP Semiconductors N-channel TrenchMOS logic level FET 003aaa362 20 ID (A) ID (A) VGS (V) = 2.1 4.5 10 15 003aaa363 40 2.5 30 2 10 20 Tj = 150 °C 25 °C 1.9 10 5 1.8 0 0 0 Fig 5. 0.2 0.4 0.6 0.8 VDS (V) 1 Output characteristics: drain current as a function of drain-source voltage; typical values 03aa33 2.5 1.5 Fig 6. 1 max 10-2 typ 10-3 Fig 7. 03aa36 typ max 10-5 10-6 0 60 120 Tj (°C) 180 Gate-source threshold voltage as a function of junction temperature 0 Fig 8. 1 2 VGS (V) 3 Sub-threshold drain current as a function of gate-source voltage PH3120L_3 Product data sheet 3 10-4 min 0.5 0 -60 VGS (V) Transfer characteristics: drain current as a function of gate-source voltage; typical values min 1 2 10-1 ID (A) VGS(th) (V) 2 0 © NXP B.V. 2009. All rights reserved. Rev. 03 — 30 March 2009 6 of 12 PH3120L NXP Semiconductors N-channel TrenchMOS logic level FET 003aaa364 40 1.9 RDSon (mΩ) 2 03aa27 2 2.1 a 30 1.5 20 1 0.5 10 VGS (V) = 2.5 4.5 10 0 0 Fig 9. 10 20 ID (A) 30 Drain-source on-state resistance as a function of drain current; typical values 003aaa367 10 VGS (V) 8 0 -60 0 60 120 Tj (°C) 180 Fig 10. Normalized drain-source on-state resistance factor as a function of junction temperature 003aaa365 104 C (pF) Ciss 103 Coss 6 Crss 4 2 0 0 25 50 75 QG (nC) 100 Fig 11. Gate-source voltage as a function of gate charge; typical values 102 10-1 10 VDS (V) 102 Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values PH3120L_3 Product data sheet 1 © NXP B.V. 2009. All rights reserved. Rev. 03 — 30 March 2009 7 of 12 PH3120L NXP Semiconductors N-channel TrenchMOS logic level FET 003aaa366 40 IS (A) 30 150 °C 20 Tj = 25 °C 10 0 0.2 0.4 0.6 0.8 VSD (V) 1 Fig 13. Source current as a function of source-drain voltage; typical values PH3120L_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 30 March 2009 8 of 12 PH3120L NXP Semiconductors N-channel TrenchMOS logic level FET 7. Package outline Plastic single-ended surface-mounted package (LFPAK); 4 leads A2 A E SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w M A b 1/2 X c e A (A 3) A1 C θ L detail X y C 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A A1 A2 A3 b b2 1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62 b3 b4 2.2 2.0 0.9 0.7 c D (1) c2 D1(1) E(1) E1(1) max 0.25 0.30 4.10 4.20 0.19 0.24 3.80 5.0 4.8 3.3 3.1 e H L L1 L2 w y θ 1.27 6.2 5.8 0.85 0.40 1.3 0.8 1.3 0.8 0.25 0.1 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-10-13 06-03-16 MO-235 Fig 14. Package outline SOT669 (LFPAK) PH3120L_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 30 March 2009 9 of 12 PH3120L NXP Semiconductors N-channel TrenchMOS logic level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PH3120L_3 20090330 Product data sheet - PH3120L_2 Modifications: PH3120L_2 (9397 750 14089) • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 20050120 PH3120L-01 (9397 750 12812) 20040304 Product data sheet - PH3120L-01 Preliminary data sheet - - PH3120L_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 30 March 2009 10 of 12 PH3120L NXP Semiconductors N-channel TrenchMOS logic level FET 9. Legal information 9.1 Data sheet status Document status [1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 9.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — is a trademark of NXP B.V. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PH3120L_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 30 March 2009 11 of 12 PH3120L NXP Semiconductors N-channel TrenchMOS logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 30 March 2009 Document identifier: PH3120L_3