PH1825AL N-channel TrenchMOS logic level FET Rev. 01 — 22 April 2009 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits 100% gate resistance tested 100% Ruggedness tested Optimimzed for use in DC-to-DC converters Very low switching and conduction losses Lead-free package Logic level compatible 1.3 Applications DC-to-DC converters Switched-mode power supplies Notebook computers Voltage regulators 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit - - 25 V - - 100 A VGS = 4.5 V; ID = 25 A; VDS = 12 V; see Figure 12; see Figure 13 - 8 - nC VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 10; see Figure 11 - 1.4 1.8 mΩ VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1; see Figure 3 [1] Dynamic characteristics QGD gate-drain charge Static characteristics RDSon [1] drain-source on-state resistance Continuous current is limited by package. PH1825AL NXP Semiconductors N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D mb G S mbb076 1 2 3 4 SOT669 (LFPAK) 3. Ordering information Table 3. Ordering information Type number Package Name Description PH1825AL LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads Version SOT669 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - 25 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 150 °C; RGS = 20 kΩ - 25 V VGS gate-source voltage -20 20 V ID drain current - 100 A - 100 A - 697 A VGS = 10 V; Tmb = 100 °C; see Figure 1 VGS = 10 V; Tmb = 25 °C; see Figure 1; see Figure 3 [1] IDM peak drain current tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3 Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 104 W Tstg storage temperature -55 150 °C Tj junction temperature -55 150 °C Source-drain diode IS source current Tmb = 25 °C; ISM peak source current tp ≤ 10 µs; pulsed; Tmb = 25 °C [1] - 100 A - 697 A - 239 mJ Avalanche ruggedness EDS(AL)S non-repetitive VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; Vsup ≤ 25 V; drain-source avalanche tp = 0.15 ms; RGS = 50 Ω; unclamped energy [1] Continuous current is limited by package. PH1825AL_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 22 April 2009 2 of 13 PH1825AL NXP Semiconductors N-channel TrenchMOS logic level FET 003aac992 180 03aa15 120 ID (A) Pder (%) 80 120 (1) 40 60 0 0 0 Fig 1. 50 100 150 T mb 0 (°C)200 Continuous drain current as a function of mounting base temperature 50 100 150 Fig 2. Normalized total power dissipation as a function of mounting base temperature 003aac991 103 ID (A) Limit R DS on = VDS / ID 10 200 Tmb (°C) tp = 10 μs 2 (1 ) 100 μs 1 ms 10 DC 10 ms 100 ms 1 10-1 10-1 Fig 3. 1 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage PH1825AL_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 22 April 2009 3 of 13 PH1825AL NXP Semiconductors N-channel TrenchMOS logic level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Rth(j-mb) thermal resistance from see Figure 4 junction to mounting base Min Typ Max Unit - - 1.2 K/W 003aac330 10 Zth (j-mb) (K/W) 1 δ = 0.5 0.2 10-1 0.1 0.05 0.02 10-2 δ= P tp T s ingle s hot t tp T 10-3 10-6 Fig 4. 10-5 10-4 10-3 10-2 10-1 tp (s ) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration PH1825AL_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 22 April 2009 4 of 13 PH1825AL NXP Semiconductors N-channel TrenchMOS logic level FET 6. Characteristics Table 6. Symbol Characteristics Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS VGS(th) IDSS IGSS RDSon RG drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 25 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 23.2 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 8; see Figure 9 1.3 1.7 2.15 V ID = 1 mA; VDS = VGS; Tj = 150 °C; see Figure 8; see Figure 9 0.65 - - V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 8; see Figure 9 - - 2.45 V VDS = 25 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 25 V; VGS = 0 V; Tj = 150 °C - - 100 µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 4.5 V; ID = 25 A; Tj = 25 °C; see Figure 10 - 2 2.7 mΩ VGS = 10 V; ID = 25 A; Tj = 150 °C; see Figure 10 - 2.4 3.1 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 10; see Figure 11 - 1.4 1.8 mΩ f = 1 MHz - 0.95 1.5 Ω ID = 25 A; VDS = 12 V; VGS = 4.5 V; see Figure 12; see Figure 13 - 31 - nC ID = 0 A; VDS = 0 V; VGS = 4.5 V - 24.5 - nC ID = 25 A; VDS = 12 V; VGS = 4.5 V; see Figure 12; see Figure 13 - 10.4 - nC - 5.4 - nC - 5 - nC drain leakage current gate leakage current drain-source on-state resistance gate resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGS(th) pre-threshold gate-source charge QGS(th-pl) post-threshold gate-source charge QGD gate-drain charge - 8 - nC VGS(pl) gate-source plateau voltage VDS = 12 V; see Figure 12; see Figure 13 - 2.54 - V Ciss input capacitance VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 14 - 4300 - pF VDS = 0 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C - 4800 - pF VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 14 - 1100 - pF - 390 - pF Coss output capacitance Crss reverse transfer capacitance PH1825AL_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 22 April 2009 5 of 13 PH1825AL NXP Semiconductors N-channel TrenchMOS logic level FET Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit td(on) turn-on delay time - 47 - ns tr rise time VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V; RG(ext) = 5.6 Ω - 72 - ns td(off) turn-off delay time - 54 - ns tf fall time - 29 - ns Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 15 - 0.82 1.2 V trr reverse recovery time - 43 - ns Qr recovered charge IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = 25 V - 53 - nC 003aac853 100 10 4.5 ID (A) VGS (V) = 3.2 003aac855 100 ID (A) 80 75 3.1 60 3 50 40 Tj = 150 °C 2.9 2.8 20 25 °C 25 2.7 2.6 0 0 0 Fig 5. 0.5 1 1.5 VDS (V) 2 Output characteristics: drain current as a function of drain-source voltage; typical values 0 Fig 6. 2 3 VGS (V) 4 Transfer characteristics: drain current as a function of gate-source voltage; typical values PH1825AL_1 Product data sheet 1 © NXP B.V. 2009. All rights reserved. Rev. 01 — 22 April 2009 6 of 13 PH1825AL NXP Semiconductors N-channel TrenchMOS logic level FET 003aac858 104 Ciss C (pF) 003aac325 10-3 ID (A) Crss 10-4 min typ max 103 10-5 10-6 102 10 Fig 7. -1 1 VGS (V) 0 10 Input and reverse transfer capacitances as a function of gate-source voltage; typical values Fig 8. 2 VGS (V) 3 Sub-threshold drain current as a function of gate-source voltage 003a a c337 3 1 003a a c338 2 a VGS (th) (V) 1.6 max 2 1.2 typ min 0.8 1 0.4 0 -60 Fig 9. 0 60 120 Tj (°C) 180 Gate-source threshold voltage as a function of junction temperature 0 -60 60 120 Tj (°C) 180 Fig 10. Normalized drain-source on-state resistance factor as a function of junction temperature PH1825AL_1 Product data sheet 0 © NXP B.V. 2009. All rights reserved. Rev. 01 — 22 April 2009 7 of 13 PH1825AL NXP Semiconductors N-channel TrenchMOS logic level FET 003aac854 20 2.7 RDSon (mΩ) 2.8 2.9 3 VGS (V) = 3.1 VDS 3.2 ID 15 VGS(pl) VGS(th) 10 VGS QGS1 5 QGS2 QGS 4.5 QGD QG(tot) 003aaa508 10 0 0 25 50 75 I D (A) 100 Fig 12. Gate charge waveform definitions Fig 11. Drain-source on-state resistance as a function of drain current; typical values. 003aac859 10 003aac857 104 I D = 25 A Tj = 25 °C VGS (V) 8 C (pF) Ciss 103 Coss 12 V 6 4 Crss 2 102 0 0 20 40 60 QG (nC) 80 Fig 13. Gate-source voltage as a function of turn-on gate chare; typical values. 10-1 10 2 VDS (V) 10 Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values PH1825AL_1 Product data sheet 1 © NXP B.V. 2009. All rights reserved. Rev. 01 — 22 April 2009 8 of 13 PH1825AL NXP Semiconductors N-channel TrenchMOS logic level FET 003aac856 100 IS (A) 80 60 40 20 150 °C Tj = 25 °C 0 0 0.25 0.5 0.75 V (V) 1 SD Fig 15. Source current as a function of source drain voltage; typical values. PH1825AL_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 22 April 2009 9 of 13 PH1825AL NXP Semiconductors N-channel TrenchMOS logic level FET 7. Package outline Plastic single-ended surface-mounted package (LFPAK); 4 leads A2 A E SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w M A b 1/2 X c e A (A 3) A1 C θ L detail X y C 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A A1 A2 A3 b b2 1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62 b3 b4 2.2 2.0 0.9 0.7 c D (1) c2 D1(1) E(1) E1(1) max 0.25 0.30 4.10 4.20 0.19 0.24 3.80 5.0 4.8 3.3 3.1 e H L L1 L2 w y θ 1.27 6.2 5.8 0.85 0.40 1.3 0.8 1.3 0.8 0.25 0.1 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-10-13 06-03-16 MO-235 Fig 16. Package outline SOT669 (LFPAK) PH1825AL_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 22 April 2009 10 of 13 PH1825AL NXP Semiconductors N-channel TrenchMOS logic level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PH1825AL_1 20090422 Product data sheet - - PH1825AL_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 22 April 2009 11 of 13 PH1825AL NXP Semiconductors N-channel TrenchMOS logic level FET 9. Legal information 9.1 Data sheet status Document status [1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 9.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — is a trademark of NXP B.V. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PH1825AL_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 22 April 2009 12 of 13 PH1825AL NXP Semiconductors N-channel TrenchMOS logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 22 April 2009 Document identifier: PH1825AL_1