NLAS7242 High-Speed USB 2.0 (480 Mbps) DPDT Switches The NLAS7242 is a DPDT switch optimized for high−speed USB 2.0 applications within portable systems. It features ultra−low on capacitance, CON = 7.5 pF (typ), and a bandwidth above 950 MHz. It is optimized for applications that use a single USB interface connector to route multiple signal types. The CON and RON of both channels are suitably low to allow the NLAS7242 to pass any speed USB data or audio signals going to a moderately resistive terminal such as an external headset. The device is offered in a UQFN10 1.4 mm x 1.8 mm package. http://onsemi.com MARKING DIAGRAM UQFN10 CASE 488AT Features • • • • • • • • • Optimized Flow−Through Pinout RON: 5.0 Typ @ VCC = 4.2 V CON: 7.5 pF Typ @ VCC = 3.3 V VCC Range: 1.65 V to 4.5 V Typical Bandwidth: 950 MHz 1.4 mm x 1.8 mm x 0.50 mm UQFN10 OVT on Common Signal Pins D+/D− up to 5.25 V 8 kV HBM ESD Protection on All Pins This is a Pb−Free Device 1 AD M G ORDERING INFORMATION Device NLAS7242MUTBG • High Speed USB 2.0 Data • Mobile Phones • Portable Devices USB CONNECTOR Device Code Date Code Pb−Free Device (Note: Microdot may be in either location) Typical Applications NLAS7242 = = = AD MG G Package UQFN0 (Pb−Free) Shipping† 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. HS USB XCVR FS USB XCVR or AUDIO AMP Figure 1. Application Diagram © Semiconductor Components Industries, LLC, 2009 August, 2009 − Rev. 4 1 Publication Order Number: NLAS7242/D NLAS7242 OE 8 VCC 9 HSD2+ HSD2− 7 6 5 HSD1+ 4 HSD1− 3 GND CONTROL S 10 1 2 D+ D− Figure 2. Pin Connections and Logic Diagram (Top View) Table 1. PIN DESCRIPTION Table 2. TRUTH TABLE Pin S Function Control Input OE HSD1+, HSD1−, HSD2+, HSD2−, D+, D− OE S HSD1+, HSD1− HSD2+, HSD2− 1 0 0 X 0 1 OFF ON OFF OFF OFF ON Output Enable Data Ports MAXIMUM RATINGS Symbol Pins VCC VCC VIS HSDn+, HSDn− Parameter Positive DC Supply Voltage Analog Signal Voltage D+, D− VIN S, OE ICC VCC TS Value Unit −0.5 to +5.5 V −0.5 to VCC + 0.3 V −0.5 to +5.25 Control Input Voltage, Output Enable Voltage Positive DC Supply Current Storage Temperature −0.5 to +5.5 V 50 mA −65 to +150 °C IIS_CON HSDn+, HSDn−, D+, D− Analog Signal Continuous Current−Closed Switch $300 mA IIS_PK HSDn+, HSDn−, D+, D− Analog Signal Continuous Current 10% Duty Cycle $500 mA Control Input Current, Output Enable Current $20 mA IIN S, OE Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol Pins VCC VIS HSDn+, HSDn− Min Max Unit Positive DC Supply Voltage Parameter 1.65 4.5 V Analog Signal Voltage GND VCC V GND 4.5 GND VCC V −40 +85 °C D+, D− VIN S, OE TA Control Input Voltage, Output Enable Voltage Operating Temperature Minimum and maximum values are guaranteed through test or design across the Recommended Operating Conditions, where applicable. Typical values are listed for guidance only and are based on the particular conditions listed for section, where applicable. These conditions are valid for all values found in the characteristics tables unless otherwise specified in the test conditions. ESD PROTECTION Symbol ESD Parameter Human Body Model − All Pins http://onsemi.com 2 Value Unit 8.0 kV NLAS7242 DC ELECTRICAL CHARACTERISTICS CONTROL INPUT, OUTPUT ENABLE VOLTAGE (Typical: T = 25°C) −40°C to +85°C Symbol Pins Parameter Test Conditions VCC (V) Min Typ Max Unit VIH S, OE Control Input, Output Enable HIGH Voltage (See Figure 11) 2.7 3.3 4.2 1.25 1.3 1.4 − − V VIL S, OE Control Input, Output Enable LOW Voltage (See Figure 11) 2.7 3.3 4.2 − − 0.35 0.4 0.5 V IIN S, OE Current Input, Output Enable Leakage Current 1.65 − 4.5 − − ±1.0 A 0 ≤ VIS ≤ VCC SUPPLY CURRENT AND LEAKAGE (Typical: T = 25°C, VCC = 3.3 V) −40°C to +85°C Symbol ICC Pins Parameter VCC (V) Min Typ Max Unit VCC Quiescent Supply Current 0 ≤ VIS ≤ VCC; ID = 0 A 0 ≤ VIS ≤ VCC − 0.5 V 1.65 − 3.6 3.6 − 4.5 − − − − 1.0 1.0 A OFF State Leakage 0 ≤ VIS ≤ VCC 1.65 − 4.5 − ±0.1 ±1.0 A Power OFF Leakage Current 0 ≤ VIS ≤ VCC 0 − − ±1.0 A IOZ IOFF D+, D− Test Conditions LIMITED VIS SWING ON RESISTANCE (Typical: T = 25°C) −40°C to +85°C Symbol Pins Parameter Test Conditions VCC (V) Min Typ Max Unit RON On−Resistance (Note 1) ION = 8 mA VIS = 0 V to 0.4 V 2.7 3.3 4.2 − 6.0 5.5 5.0 8.6 7.6 7.0 RFLAT On−Resistance Flatness (Notes 1 and 2) ION = 8 mA VIS = 0 V to 0.4 V 2.7 3.3 4.2 − 0.55 0.30 0.20 − RON On−Resistance Matching (Notes 1 and 3) ION = 8 mA VIS = 0 V to 0.4 V 2.7 3.3 4.2 − 0.60 0.60 0.60 − 1. Guaranteed by design. 2. Flatness is defined as the difference between the maximum and minimum value of On−Resistance as measured over the specified analog signal ranges. 3. RON = RON(max) − RON(min) between HSD1+ and HSD1− or HSD2+ and HSD2−. FULL VIS SWING ON RESISTANCE (Typical: T = 25°C) −40°C to +85°C Symbol Pins Parameter Test Conditions VCC (V) Min Typ Max Unit RON On−Resistance ION = 8 mA VIS = 0 V to VCC 2.7 3.3 4.2 − 10 8.0 7.0 13.5 9.75 8.50 RFLAT On−Resistance Flatness (Notes 4 and 5) ION = 8 mA VIS = 0 V to VCC 2.7 3.3 4.2 − 4.5 3.0 2.5 − RON On−Resistance (Note 4 and 6) ION = 8 mA VIS = 0 V to VCC 2.7 3.3 4.2 − 0.60 0.60 0.60 − 4. Guaranteed by design. 5. Flatness is defined as the difference between the maximum and minimum value of On−Resistance as measured over the specified analog signal ranges. 6. RON = RON(max) − RON(min) between HSD1+ and HSD1− or HSD2+ and HSD2−. http://onsemi.com 3 NLAS7242 AC ELECTRICAL CHARACTERISTICS TIMING/FREQUENCY (Typical: T = 25°C, VCC = 3.3 V, RL = 50 , CL = 35 pF, f = 1 MHz) −405C to +855C Symbol Pins tON Closed to Open tOFF Open to Closed VCC (V) Min Typ Max Unit Turn−ON Time (See Figures 4 and 5) 1.65 − 4.5 − 13.0 30.0 ns Turn−OFF Time (See Figures 4 and 5) 1.65 − 4.5 − 12.0 25.0 ns Break−Before−Make Time (See Figure 3) 1.65 − 4.5 2.0 − − ns 1.65 − 4.5 − 950 − MHz Parameter TBBM BW −3 dB Bandwidth (See Figure 10) Test Conditions CL = 5 pF ISOLATION (Typical: T = 25°C, VCC = 3.3 V, RL = 50 , CL = 5 pF) −405C to +855C Symbol Pins OIRR Open XTALK HSDn+ to HSDn− VCC (V) Min Typ Max Unit OFF−Isolation (See Figure 6) f = 240 MHz 1.65 − 4.5 − −22 − dB Non−Adjacent Channel Crosstalk f = 240 MHz 1.65 − 4.5 − −24 − dB Parameter Test Conditions CAPACITANCE (Typical: T = 25°C, VCC = 3.3 V, RL = 50 , CL = 5 pF) −405C to +855C Symbol Pins Parameter Min Typ Max Unit CIN S, OE Control Pin, Output Enable Input Capacitance VCC = 0 V, f = 1 MHz − 1.5 − pF VCC = 0 V, f = 10 MHz − 1.0 − CON D+ to HSD1+ or HSD2+ ON Capacitance VCC = 3.3 V; OE = 0 V, f = 1 MHz S = 0 V or 3.3 V − 7.5 − VCC = 3.3 V; OE = 0 V, f = 10 MHz S = 0 V or 3.3 V − 6.5 − HSD1n or HSD2n OFF Capacitance VCC = VIS = 3.3 V; OE = 0 V, S = 3.3 V or 0 V, f = 1 MHz − 3.8 − VCC = VIS = 3.3 V; OE = 0 V, S = 3.3 V or 0 V, f = 10 MHz − 2.0 − COFF Test Conditions http://onsemi.com 4 NLAS7242 VCC DUT VCC Input Output GND VOUT 0.1 F 50 35 pF tBMM Output 50 % OF DROOP VOLTAGE DROOP Switch Select Pin Figure 3. tBBM (Time Break−Before−Make) VCC Input DUT VCC 0.1 F 50% Output VOUT Open 50% 0V 50 VOH 90% 35 pF 90% Output VOL Input tON tOFF Figure 4. tON/tOFF VCC VCC Input DUT Output 50% 0V 50 VOUT Open 50% VOH 35 pF Output Input tOFF Figure 5. tON/tOFF http://onsemi.com 5 10% 10% VOL tON NLAS7242 50 Reference DUT Transmitted Input Output 50 Generator 50 Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction. ǒVVOUT Ǔ for VIN at 100 kHz IN VOUT Ǔ for VIN at 100 kHz to 50 MHz VONL = On Channel Loss = 20 Log ǒ VIN VISO = Off Channel Isolation = 20 Log Bandwidth (BW) = the frequency 3 dB below VONL VCT = Use VISO setup and test to all other switch analog input/outputs terminated with 50 Figure 6. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/VONL DETAILED DESCRIPTION High Speed (480Mbps) USB 2.0 Optimized Over Voltage Tolerant The NLAS7242 is a DPDT switch designed for USB applications within portable systems. The RON and CON of both switches are maintained at industry−leading low levels in order to ensure maximum signal integrity for USB 2.0 high speed data communication. The NLAS7242 switch can be used to switch between high speed (480Mbps) USB signals and a variety of audio or data signals such as full speed USB, UART or even a moderately resistive audio terminal. The NLAS7242 features over voltage tolerant I/O protection on the common signal pins D+/D−. This allows the switch to interface directly with a USB connector. The D+/D− pins can withstand a short to VBUS, up to 5.25 V, continuous DC current for up to 24 hours as specified in the USB 2.0 specification. This protection is achieved without the need for any external resistors or protection devices. http://onsemi.com 6 NLAS7242 NLAS7242 Figure 7. Board Schematic http://onsemi.com 7 NLAS7242 Figure 8. Signal Quality Figure 9. Near End Eye Diagram http://onsemi.com 8 NLAS7242 Near End Test Data: Std. N.C. N.O. Consecutive jitter range −54.37 73.21 ps Paired JK jitter range −59.14 59.56 ps Paired KJ jitter range −50.79 34.57 ps Consecutive jitter range −74.43 81.65 ps Paired JK jitter range −61.60 58.55 ps Paired KJ jitter range −55.31 48.43 ps Consecutive jitter range −82.55 80.33 ps Paired JK jitter range −53.50 71.65 ps Paired KJ jitter range −62.60 47.30 ps 0 −0.5 MAGNITUDE (dB) −1 −1.5 −2 −2.5 −3 −3.5 −4 −4.5 1.0E+6 10.0E+6 100.0E+6 1.0E+9 FREQUENCY (Hz) Figure 10. Magnitude vs. Frequency @ VCC = 3.3 V, All Temperatures ICC Leakage Current as a Function of VIN Voltage (255C) 2.50E−03 4.2 V 2.00E−03 3.3 V ICC 1.50E−03 1.00E−03 2.7 V 5.00E−04 0.00E+00 −5.00E−04 0 0.5 1 1.5 2 2.5 3 3.5 4 VIN (V) Figure 11. ICC vs. VIN, Select Pin, All VCC’s, 255C http://onsemi.com 9 4.5 Min Max −200 ps +200 ps −200 ps +200 ps −200 ps +200 ps NLAS7242 PACKAGE DIMENSIONS UQFN10 1.4x1.8, 0.4P CASE 488AT−01 ISSUE A EDGE OF PACKAGE D ÉÉ ÉÉ PIN 1 REFERENCE 2X 2X L1 E DETAIL A Bottom View (Optional) 0.10 C 0.10 C B TOP VIEW A1 0.05 C A1 C SIDE VIEW 3 9X EXPOSED Cu A 0.05 C 10X 5 SEATING PLANE ÉÉ ÉÉ DIM A A1 A3 b D E e L L1 L3 MOLD CMPD A3 DETAIL B Side View (Optional) 1.700 0.0669 0.663 0.0261 6 e 1 0.200 0.0079 10 X L3 b MILLIMETERS MIN MAX 0.45 0.60 0.00 0.05 0.127 REF 0.15 0.25 1.40 BSC 1.80 BSC 0.40 BSC 0.30 0.50 0.00 0.15 0.40 0.60 MOUNTING FOOTPRINT* e/2 L 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A 1 0.10 C A B 0.05 C 9X 0.563 0.0221 2.100 0.0827 NOTE 3 BOTTOM VIEW 0.400 0.0157 PITCH 10 X 0.225 0.0089 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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