PHILIPS HEF4014BT653

HEF4014B
8-bit static shift register
Rev. 8 — 21 November 2011
Product data sheet
1. General description
The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight
synchronous parallel inputs (D0 to D7), a synchronous serial data input (DS), a
synchronous parallel enable input (PE), a LOW-to-HIGH edge-triggered clock input (CP)
and buffered parallel outputs from the last three stages (Q5 to Q7).
Operation is synchronous and the device is edge-triggered on the LOW-to-HIGH
transition of CP. Each register stage is of a D-type master-slave flip-flop type. When PE is
HIGH, data is loaded into the register from D0 to D7 on the LOW-to-HIGH transition of CP.
When PE is LOW, data is shifted to the first position from DS, and all the data in the
register is shifted one position to the right on the LOW-to-HIGH transition of CP. The clock
input’s Schmitt trigger action makes it highly tolerant of slower clock rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits






Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
 Parallel-to-serial converter
 Serial data queueing
 General purpose register
4. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +85 C
Type number
Package
Name
Description
Version
HEF4014BP
DIP16
plastic dual in-line package; 16-leads (300 mil)
SOT38-4
HEF4014BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
HEF4014B
NXP Semiconductors
8-bit static shift register
5. Functional diagram
7
6
5
4
13
14
15
1
D0
D1
D2
D3
D4
D5
D6
D7
9 PE
11 DS
0D
CP
10 CP
1D
2D 3D 4D 5D 6D
SHIFT REGISTER
8 BITS
7D
Q5 Q6 Q7
2
12
3
001aae556
Fig 1.
Functional diagram
PE
D5
D0
D
DS
Q
FF 0
CP
D6
D
D7
D
Q
Q
D
FF 6
FF 5
CP
CP
Q
FF 7
CP
CP
Q5
Q6
Q7
001aae558
Fig 2.
Logic diagram
HEF4014B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
2 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
6. Pinning information
6.1 Pinning
HEF4014B
D7
1
16 VDD
Q5
2
15 D6
Q7
3
14 D5
D3
4
13 D4
D2
5
12 Q6
D1
6
11 DS
D0
7
10 CP
VSS
8
9
PE
001aae557
Fig 3.
Pin configuration DIP16 and SO16
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
Q5 to Q7
2, 12, 3
output
D0 to D7
7, 6, 5, 4, 13, 14, 15, 1
parallel data input
VSS
8
ground supply voltage
PE
9
parallel enable input
CP
10
clock input (LOW-to-HIGH edge-triggered)
DS
11
serial data input
VDD
16
supply voltage
HEF4014B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
3 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
7. Functional description
Table 3.
Function table[1]
Number of clock
transitions
Inputs
Outputs
CP
DS
PE
Q5
Q6
Q7
1

1D
L
X
X
X
2

2D
L
X
X
X
3

3D
L
X
X
X
6

X
L
1D
X
X
7

X
L
2D
1D
X
8

X
L
3D
2D
1D

X
X
no change
no change
no change

X
H
D5
D6
D7

X
X
no change
no change
no change
Serial operation
Parallel operation
1
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; nD = HIGH or LOW;
 = LOW-to-HIGH clock transition;  = HIGH-to-LOW clock transition;
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
Conditions
VI < 0.5 V or VI > VDD + 0.5 V
Min
Max
Unit
0.5
+18
V
-
10
mA
0.5
VDD + 0.5
V
-
10
mA
10
mA
IIK
input clamping current
VI
input voltage
IOK
output clamping current
II/O
input/output current
-
IDD
supply current
-
50
mA
Tstg
storage temperature
65
+150
C
Tamb
ambient temperature
40
+85
C
Ptot
total power dissipation
P
power dissipation
VO < 0.5 V or VO > VDD + 0.5 V
Tamb = 40 C to +85 C
DIP16 package
[1]
-
750
mW
SO16 package
[2]
-
500
mW
-
100
mW
per output
[1]
For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2]
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
HEF4014B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
4 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VDD
VI
Conditions
Min
Typ
Max
Unit
supply voltage
3
-
15
V
input voltage
0
-
VDD
V
Tamb
ambient temperature
in free air
40
-
+85
C
t/V
input transition rise and fall rate
VDD = 5 V
-
-
3.75
s/V
VDD = 10 V
-
-
0.5
s/V
VDD = 15 V
-
-
0.08
s/V
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
VIH
VIL
VOH
VOL
IOH
IOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
HIGH-level output current
LOW-level output current
Conditions
input leakage current
IDD
supply current
CI
input capacitance
HEF4014B
Product data sheet
Tamb = 40 C
Tamb = +25 C
Tamb = +85 C Unit
Min
Max
Min
Max
Min
Max
5V
3.5
-
3.5
-
3.5
-
V
10 V
7.0
-
7.0
-
7.0
-
V
15 V
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
V
IO < 1 A
IO < 1 A
IO < 1 A
5V
4.95
-
4.95
-
4.95
-
V
10 V
9.95
-
9.95
-
9.95
-
V
15 V
14.95
-
14.95
-
14.95
-
V
5V
-
0.05
-
0.05
-
0.05
V
10 V
-
0.05
-
0.05
-
0.05
V
15 V
-
0.05
-
0.05
-
0.05
V
VO = 2.5 V
5V
-
1.7
-
1.4
-
1.1
mA
VO = 4.6 V
5V
-
0.52
-
0.44
-
0.36 mA
VO = 9.5 V
10 V
-
1.3
-
1.1
-
0.9
mA
VO = 13.5 V
15 V
-
3.6
-
3.0
-
2.4
mA
VO = 0.4 V
5V
0.52
-
0.44
-
0.36
-
mA
VO = 0.5 V
10 V
1.3
-
1.1
-
0.9
-
mA
|IO < 1 A
VO = 1.5 V
II
VDD
15 V
3.6
-
3.0
-
2.4
-
mA
15 V
-
0.3
-
0.3
-
1.0
A
5V
-
20
-
20
-
150
A
10 V
-
40
-
40
-
300
A
15 V
-
80
-
80
-
600
A
-
-
-
-
7.5
-
-
pF
IO = 0 A
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
5 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
11. Dynamic characteristics
Table 7.
Dynamic characteristics
Tamb = 25 C; VSS = 0 V.
Symbol
Parameter
Conditions
tPHL
HIGH to LOW
propagation delay
CP to Qn;
see Figure 4
tPLH
LOW to HIGH
propagation delay
CP to Qn;
see Figure 4
transition time
Qn output;
see Figure 4
Extrapolation formula[1]
Min
Typ
Max
Unit
5V
103 ns + (0.55 ns/pF)CL
-
130
260
ns
10 V
44 ns + (0.23 ns/pF)CL
-
55
110
ns
15 V
32 ns + (0.16 ns/pF)CL
-
40
80
ns
5V
88 ns + (0.55 ns/pF)CL
-
115
230
ns
10 V
39 ns + (0.23 ns/pF)CL
-
50
100
ns
VDD
32 ns + (0.16 ns/pF)CL
-
40
80
ns
10 ns + (1.00 ns/pF)CL
-
60
120
ns
10 V
9 ns + (0.42 ns/pF)CL
-
30
60
ns
15 V
6 ns + (0.28 ns/pF)CL
-
20
40
ns
CP input;
5V
minimum width; 10 V
see Figure 5
15 V
70
35
-
ns
30
15
-
ns
24
12
-
ns
PE  CP;
see Figure 5
5V
40
10
-
ns
10 V
25
5
-
ns
15 V
15
0
-
ns
5V
+35
5
-
ns
10 V
+25
5
-
ns
15 V
25
0
-
ns
5V
+35
5
-
ns
10 V
+25
5
-
ns
15 V
25
0
-
ns
15 V
tt
pulse width
tW
set-up time
tsu
DS  CP;
see Figure 5
Dn  CP;
see Figure 5
hold time
th
PE  CP;
see Figure 5
DS  CP;
see Figure 5
Dn  CP;
see Figure 5
fclk(max)
maximum clock
frequency
see Figure 5
5V
[2]
5V
+25
5
-
ns
10 V
20
0
-
ns
15 V
15
0
-
ns
5V
30
15
-
ns
10 V
20
10
-
ns
15 V
15
7
-
ns
5V
30
15
-
ns
10 V
20
10
-
ns
15 V
15
7
-
ns
5V
6
13
-
MHz
10 V
15
30
-
MHz
15 V
20
40
-
MHz
[1]
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2]
tt is the same as tTHL and tTLH.
HEF4014B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
6 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C.
Symbol
PD
Parameter
VDD
dynamic power
dissipation
Typical formula for PD (W)
Where:
PD = 900  fi + (fo  CL)  VDD
5V
2
10 V
PD = 4300  fi + (fo  CL)  VDD2
15 V
PD = 12000 fi + (fo  CL)  VDD
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
2
VDD = supply voltage in V;
(CL  fo) = sum of the outputs.
12. Waveforms
VI
VM
CP input
VSS
tPHL
VOH
tPLH
90 %
VM
10 %
Qn output
VOL
tt
tt
001aaj456
Measurement points are given in Table 9.
Fig 4.
CP to Qn propagation delays and output transition times
VI
50 %
CP input
VSS
tsu
th
50 %
50 %
tsu
th
50 %
50 %
50 %
50 %
tW
50 %
fclk(max)
tr
VI
D input
VSS
tf
tsu
th
VI
PE input
50 %
50 %
VSS
tsu
th
50 %
50 %
VI
DS input
VSS
001aae559
The shaded areas indicate where change is permitted for predictable output performance.
Set-up and hold times are shown as positive values but may be specified as negative values.
Measurement points are given in Table 9.
Fig 5.
Minimum clock pulse width, and set-up and hold times for PE to CP, DS to CP, and D to CP
HEF4014B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
7 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
Table 9.
Measurement points
Supply voltage
Input
Output
VDD
VM
VM
5 V to 15 V
0.5VDD
0.5VDD
VDD
VI
VO
G
DUT
CL
RT
001aag182
Test data is given in Table 10;
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 6.
Test circuit
Table 10.
Test data
Supply voltage
Input
VDD
VI
tr, tf
CL
5 V to 15 V
VSS or VDD
 20 ns
50 pF
HEF4014B
Product data sheet
Load
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
8 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
ME
seating plane
D
A2
A
A1
L
c
e
Z
w M
b1
(e 1)
b
b2
MH
9
16
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
b2
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
0.76
inches
0.17
0.02
0.13
0.068
0.051
0.021
0.015
0.049
0.033
0.014
0.009
0.77
0.73
0.26
0.24
0.1
0.3
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
ISSUE DATE
95-01-14
03-02-13
SOT38-4
Fig 7.
EUROPEAN
PROJECTION
Package outline SOT38-4 (DIP16)
HEF4014B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
9 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig 8.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT109-1 (SO16)
HEF4014B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
10 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4014B v.8
20111121
Product data sheet
-
HEF4014B v.7
Modifications:
•
•
Legal pages updated.
Changes in “General description” and “Features and benefits”.
HEF4014B v.7
20110914
Product data sheet
-
HEF4014B v.6
HEF4014B v.6
20091102
Product data sheet
-
HEF4014B v.5
HEF4014B v.5
20090624
Product data sheet
-
HEF4014B v.4
HEF4014B v.4
20090122
Product data sheet
-
HEF4014B_CNV v.3
HEF4014B_CNV v.3
19950101
Product specification
-
HEF4014B_CNV v.2
HEF4014B_CNV v.2
19950101
Product specification
-
-
HEF4014B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
11 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
HEF4014B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
12 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
HEF4014B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
13 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
17. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 21 November 2011
Document identifier: HEF4014B