FAIRCHILD 74F257ASJ

Revised August 1999
74F257A
Quad 2-Input Multiplexer with 3-STATE Outputs
General Description
Features
The 74F257A is a quad 2-input multiplexer with 3-STATE
outputs. Four bits of data from two sources can be selected
using a Common Data Select input. The four outputs
present the selected data in true (non-inverted) form. The
outputs may be switched to a high impedance state with a
HIGH on the common Output Enable (OE) input, allowing
the outputs to interface directly with bus-oriented systems.
■ Multiplexer expansion by tying outputs together
■ Non-inverting 3-STATE outputs
■ Input clamp diodes limit high-speed termination effects
Ordering Code:
Order Number
Package Number
Package Description
74F257ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F257ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F257APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009507
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74F257A Quad 2-Input Multiplexer with 3-STATE Outputs
April 1988
74F257A
Unit Loading/Fan Out
Pin Names
Description
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
S
Common Data Select Input
1.0/1.0
20 µA/−0.6 mA
OE
3-STATE Output Enable Input (Active LOW)
1.0/1.0
20 µA/−0.6 mA
I0a–I0d
Data Inputs from Source 0
1.0/1.0
20 µA/−0.6 mA
I1a–I1d
Data Inputs from Source 1
1.0/1.0
20 µA/−0.6 mA
Za–Zd
3-STATE Multiplexer Outputs
150/40 (33.3)
−3 mA/24 mA (20 mA)
Functional Description
Truth Table
Output
U.L.
Select
The 74F257A is a quad 2-input multiplexer with 3-STATE
outputs. It selects four bits of data from two sources under
control of a Common Data Select input. When the Select
input is LOW, the I0x inputs are selected and when Select
is HIGH, the I1x inputs are selected. The data on the
selected inputs appears at the outputs in true (noninverted) form. The device is the logic implementation of a
4-pole, 2-position switch where the position of the switch is
determined by the logic levels supplied to the Select input.
The logic equation for the outputs is shown below:
Data
Output
Enable
Input
OE
S
I0
Inputs
I1
Z
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
L
X
L
Zn = OE • (In• S + Ion • S)
L
L
H
X
H
When the Output Enable input (OE) is HIGH, the outputs
are forced to a high impedance OFF state. If the outputs
are tied together, all but one device must be in the high
impedance state to avoid high currents that would exceed
the maximum ratings. Designers should ensure the Output
Enable signals to 3-STATE devices whose outputs are tied
together are designed so there is no overlap.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
−55°C to +125°C
Free Air Ambient Temperature
Junction Temperature under Bias
−55°C to +150°C
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Current Applied to Output
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
in LOW State (Max)
ESD Last Passing Voltage (Min)
4000V
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
VCC
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
−1.2
V
Min
VOH
Output HIGH
10% VCC
2.5
Voltage
10% VCC
2.4
5% VCC
2.7
V
Min
5% VCC
2.7
VOL
Output LOW
2.0
Units
VIH
V
Input HIGH
Input HIGH Current
Breakdown Test
ICEX
Output HIGH
Leakage Current
VID
Input Leakage
Test
IOD
Circuit Current
Input LOW Current
IOZH
Output Leakage Current
IOZL
Output Leakage Current
IOS
Output Short-Circuit Current
IZZ
Bus Drainage Test
ICCH
Power Supply Current
ICCL
ICCZ
IOH = −3 mA
IOH = −1 mA
0.5
V
Min
IOL = 24 mA
5.0
µA
Max
VIN = 2.7V
7.0
µA
Max
VIN = 7.0V
50
µA
Max
VOUT = VCC
V
0.0
3.75
µA
0.0
−0.6
mA
Max
VIN = 0.5V
50
µA
Max
VOUT = 2.7V
4.75
Output Leakage
IIL
IIN = −18 mA
IOH = −3 mA
10% VCC
Current
IBVI
Recognized as a LOW Signal
IOH = −1 mA
Voltage
IIH
Conditions
Recognized as a HIGH Signal
IID = 1.9 µA
All Other Pins Grounded
VIOD = 150 mV
All Other Pins Grounded
−50
µA
Max
VOUT = 0.5V
−150
mA
Max
VOUT = 0V
500
µA
0.0V
VOUT = 5.25V
9.0
15
mA
Max
VO = HIGH
Power Supply Current
14.5
22
mA
Max
VO = LOW
Power Supply Current
15
23
mA
Max
VO = HIGH Z
−60
3
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74F257A
Absolute Maximum Ratings(Note 1)
74F257A
AC Electrical Characteristics
Symbol
Parameter
TA = +25°C
TA = −55°C to +125°C
TA = 0°C to +70°C
VCC = 5.0V
VCC = 5.0V
VCC = 5.0V
CL = 50 pF
CL = 50 pF
CL = 50 pF
Min
Typ
Max
Min
Max
Min
Max
tPLH
Propagation Delay
2.5
4.5
5.5
2.0
7.0
2.0
6.0
tPHL
In to Zn
2.0
4.2
5.5
1.5
7.0
2.0
6.0
tPLH
Propagation Delay
4.0
5.0
9.5
3.5
11.5
3.5
10.5
tPHL
S to Zn
2.5
6.5
7.0
2.5
9.0
2.5
8.0
tPZH
Output Enable Time
2.0
5.9
6.0
2.0
8.0
2.0
7.0
2.5
5.5
7.0
2.5
9.0
2.5
8.0
tPZL
tPHZ
Output Disable Time
tPLZ
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2.0
4.3
6.0
2.0
7.0
2.0
7.0
2.0
4.5
6.0
2.0
8.5
2.0
7.0
4
Units
ns
ns
ns
74F257A
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
5
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74F257A Quad 2-Input Multiplexer with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
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1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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