Revised January 2004 74F652 Transceivers/Registers General Description Features These devices consist of bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function. ■ Independent registers for A and B buses ■ Multiplexed real-time and stored data ■ 74F652 non-inverting data path Ordering Code: Order Number Package Number Package Description 74F652SC (Note 1) M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74F652SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2004 Fairchild Semiconductor Corporation DS009581 www.fairchildsemi.com 74F652 Transceivers/Registers March 1988 74F652 Unit Loading/Fan Out Pin Names Description A0–A7, B0–B7 Input IIH/IIL HIGH/LOW Output IOH/IOL 1.0/1.0 20 µA/−0.6 mA 600/106.6 (80) −12 mA/64 mA (48 mA) A and B Inputs/ 3-STATE Outputs U.L. CPAB, CPBA Clock Inputs 1.0/1.0 20 µA/−0.6 mA SAB, SBA Select Inputs 1.0/1.0 20 µA/−0.6 mA OEAB, OEBA Output Enable Inputs 1.0/1.0 20 µA/−0.6 mA Function Table Inputs Inputs/Outputs (Note 2) OEAB OEBA CPAB CPBA SAB SBA L H L H X H H H L X L L L L H or L H or L H or L X H or L X X X X A0 thru A7 Input B0 thru B7 Input Operating Mode Isolation Store A and B Data X X Input Not Specified Store A, Hold B X X Input Output X X Not Specified Input Store A in Both Registers Hold A, Store B X X Output Input Store B in Both Registers X X L Output Input Real-Time B Data to A Bus Input Output L L X H or L X H H H X X L X H H H or L X H X H L H or L H or L H H Store B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus Output Output Stored A Data to B Bus and Stored B Data to A Bus H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Note 2: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. www.fairchildsemi.com 2 Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW-to-HIGH transitions at the appropriate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with the Octal bus transceivers and receivers. Note A: Real-Time Note B: Real-Time Transfer Bus B to Bus A Transfer Bus A to Bus B OEAB OEBA CPAB CPBA L L X X SAB SBA X L OEAB OEBA CPAB CPBA H Note C: Storage H X X SAB SBA L X Note D: Transfer Storage Data to A or B OEAB OEBA CPAB CPBA X H L X L H X X SAB SBA X X X X X X OEAB OEBA CPAB CPBA H L H or L H or L SAB SBA H X FIGURE 1. 3 www.fairchildsemi.com 74F652 Functional Description 74F652 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 4 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 4) −0.5V to +7.0V Input Current (Note 4) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 3: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output in LOW State (Max) Note 4: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V 0.55 VOH Output HIGH Voltage 10% VCC VOL Output LOW Voltage 10% VCC IIH Input HIGH 2.0 Current IBVI Input HIGH Current Breakdown Test IBVIT Input HIGH Current Breakdown (I/O) ICEX Output HIGH Leakage Current VID Input Leakage Test IOD VCC V Output Leakage Recognized as a LOW Signal Min IIN = −18 mA (Non I/O Pins) V Min IOH = −15 mA (An, Bn) V Min IOL = 64 mA (A n, Bn) VIN = 2.7V 5.0 µA Max 7.0 µA Max 0.5 mA Max 50 µA Max V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V (Non I/O Pins) 70 µA Max VOUT = 2.7V (An, Bn) −650 µA Max VOUT = 0.5V (An, Bn) −225 mA Max VOUT = 0V 500 µA 0.0V VOUT = 5.25V 4.75 Circuit Current Conditions Recognized as a HIGH Signal (Non I/O Pins) VIN = 7.0V VIN = 5.5V (An, Bn) VOUT = VCC IID = 1.9 µA All Other Pins Grounded VIIOD = 150 mV All Other Pins Grounded IIL Input LOW Current IIH + IOZH Output Leakage Current IIL + IOZL Output Leakage Current IOS Output Short-Circuit Current IZZ Bus Drainage Test ICCH Power Supply Current 105 135 mA Max VO = HIGH ICCL Power Supply Current 118 150 mA Max VO = LOW ICCZ Power Supply Current 115 150 mA Max VO = HIGH Z −100 5 www.fairchildsemi.com 74F652 Absolute Maximum Ratings(Note 3) 74F652 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Max Min Max 75 Min Max fMAX Max. Clock Frequency 90 tPLH Propagation Delay 2.0 tPHL Clock to Bus 2.0 8.0 2.0 9.5 2.0 9.0 tPLH Propagation Delay 1.0 7.0 1.0 8.0 1.0 7.5 tPHL Bus to Bus 1.0 6.5 1.0 8.0 1.0 7.0 tPLH Propagation Delay 2.0 8.5 2.0 11.0 2.0 9.5 tPHL SBA or SAB to A or B 2.0 8.0 2.0 10.0 2.0 9.0 7.0 2.0 90 8.5 2.0 Units MHz 8.0 ns ns ns AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to +125°C VCC = +5.0V VCC = +5.0V Min Max TA = 0°C to +70°C VCC = +5.0V Min Max Min tPZH Enable Time 2.0 9.5 2.0 10.0 2.0 10.0 tPZL *OEBA to A 2.0 12.0 2.0 10.0 2.0 12.5 tPHZ Disable Time 1.0 7.5 1.0 9.0 1.0 8.0 tPLZ *OEBA to A 2.0 8.5 1.0 9.0 2.0 9.0 tPZH Enable Time 2.0 9.5 2.0 10.0 2.0 10.0 tPZL OEAB to B 3.0 13.0 2.0 12.0 3.0 14.0 tPHZ Disable Time 2.0 9.0 1.0 9.0 2.0 10.0 tPLZ OEAB to B 2.0 10.5 1.0 12.0 2.0 11.0 tS(H) Setup Time, HIGH or 5.0 5.0 5.0 tS(L) LOW, Bus to Clock 5.0 5.0 5.0 tH(H) Hold Time, HIGH or 2.0 2.5 2.0 tH(L) LOW, Bus to Clock 2.0 2.5 2.0 tW(H) Clock Pulse Width 5.0 5.0 5.0 tW(L) HIGH or LOW 5.0 5.0 5.0 www.fairchildsemi.com 6 Units Max ns ns ns ns ns 74F652 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B 7 www.fairchildsemi.com 74F652 Transceivers/Registers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8