Revised April 2001 74LCX16652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs General Description Features The LCX16652 contains sixteen non-inverting bidirectional bus transceivers with 3-STATE outputs providing multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to the HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function (see Functional Description). ■ 5V tolerant inputs and outputs The LCX16652 is designed for low-voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX16652 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. ■ 2.3V–3.6V VCC specifications provided ■ 5.7 ns tPD max (VCC = 3.3V), 20 µA ICC max ■ Power down high impedance inputs and outputs ■ Supports live insertion/withdrawal (Note 1) ■ ±24 mA output drive (VCC = 3.0V) ■ Implements patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC and OE tied to GND through a resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number 74LCX16652MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Description 74LCX16652MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description A0–A15 Data Register A Inputs/3-STATE Outputs B0–B15 Data Register B Inputs/3-STATE Outputs CPABn, CPBAn Clock Pulse Inputs SABn, SBAn Select Inputs OEABn, OEBAn Output Enable Inputs © 2001 Fairchild Semiconductor Corporation DS012005 www.fairchildsemi.com 74LCX16652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs February 1994 74LCX16652 Connection Diagram Truth Table (Note 2) Inputs Inputs/Outputs OEAB OEBA1 CPAB1 CPBA1 SAB1 L H L H X H H H L X L L L L H or L H or L X H or L H or L SBA1 A0 thru A7 B0 thru B7 Input Input X X X X X X Input Not Specified X X Input Output X X Not Specified Input Operating Mode Isolation Store A and B Data Store A, Hold B Store A in Both Registers Hold A, Store B X X Output Input Store B in Both Registers X X L Output Input Real-Time B Data to A Bus Input Output L L X H or L X H H H X X L X H H H or L X H X H L H or L H or L H H Store B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus Output Output Stored A Data to B Bus and Stored B Data to A Bus H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Note 2: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. This also applies to data I/O (A and B: 8–15) and #2 control pins. www.fairchildsemi.com 2 Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW-to-HIGH transitions at the appropriate Clock Inputs (CPABn, CPBAn) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEABn and OEBAn. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SABn, SBAn) controls can multiplex stored and real-time. The examples below demonstrate the four fundamental bus-management functions that can be performed with the 74LCX16652. Real-Time Transfer Bus B to Bus A Real-Time Transfer Bus A to Bus B OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 L L X X X OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 L H H Transfer Storage Data to A or B L H or L H or L X L X Storage OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 H X H OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 H 3 X H L X L H X X X X X X X X www.fairchildsemi.com 74LCX16652 Functional Description 74LCX16652 Logic Diagram Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 4 Symbol Parameter Value VCC Supply Voltage −0.5 to +7.0 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Conditions Units V V Output in 3-STATE −0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 4) IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND +50 VO > VCC V mA mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions (Note 5) Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage IOH/IOL Output Current TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Min Max Operating 2.0 3.6 Data Retention 1.5 3.6 0 5.5 HIGH or LOW State 0 VCC 3-STATE 0 5.5 VCC = 3.0V − 3.6V ±24 VCC = 2.7V − 3.0V ±12 VCC = 2.3V − 2.7V ±8 Units V V V mA −40 85 °C 0 10 ns/V Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: Unused (inputs or I/O's) must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage IOH = −100 µA VCC TA = −40°C to +85°C (V) Min 2.3 − 2.7 1.7 2.7 − 3.6 2.0 Max V 2.3 − 2.7 0.7 2.7 − 3.6 0.8 2.3 − 3.6 VCC − 0.2 IOH = −8 mA 2.3 1.8 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 IOH = −24 mA 3.0 2.2 IOL = 100 µA 2.3 − 3.6 Units V V 0.2 IOL = 8 mA 2.3 0.6 IOL = 12 mA 2.7 0.4 IOL = 16 mA 3.0 0.4 V IOL = 24 mA 3.0 0.55 II Input Leakage Current 0 ≤ VI ≤ 5.5V 2.3 − 3.6 ±5.0 µA IOZ 3-STATE I/O Leakage 0 ≤ VO ≤ 5.5V 2.3 − 3.6 ±5.0 µA 0 10 µA VI = V IH or VIL IOFF Power-Off Leakage Current VI or VO = 5.5V 5 www.fairchildsemi.com 74LCX16652 Absolute Maximum Ratings(Note 3) 74LCX16652 DC Electrical Characteristics Symbol (Continued) Parameter VCC Conditions TA = −40°C to +85°C (V) ICC ∆ICC Quiescent Supply Current Increase in ICC per Input Min Units Max VI = VCC or GND 2.3 − 3.6 20 3.6V ≤ VI, VO ≤ 5.5V (Note 6) 2.3 − 3.6 ±20 VIH = VCC −0.6V 2.3 − 3.6 500 µA µA Note 6: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA = −40°C to +85°C, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V CL = 50 pF CL = 50 pF CL = 30 pF Min Max Min Max Min Max 5.7 1.5 6.2 1.5 6.8 1.5 6.2 1.5 6.8 1.5 7.0 1.5 7.4 Units fMAX Maximum Clock Frequency 170 tPHL Propagation Delay 1.5 tPLH Bus to Bus 1.5 5.7 tPHL Propagation Delay 1.5 6.2 tPLH Clock to Bus 1.5 6.2 1.5 7.0 1.5 7.4 tPHL Propagation Delay 1.5 6.5 1.5 7.0 1.5 7.8 tPLH Select to Bus 1.5 6.5 1.5 7.0 1.5 7.8 tPZL Output Enable Time 1.5 7.0 1.5 8.0 1.5 9.1 1.5 7.0 1.5 8.0 1.5 9.1 Output Disable Time 1.5 6.5 1.5 7.0 1.5 7.8 1.5 6.5 1.5 7.0 1.5 7.8 tS Setup Time 2.5 2.5 3.0 tH Hold Time 1.5 1.5 2.0 ns tW Pulse Width 3.0 3.0 3.5 ns tOSHL Output to Output Skew (Note 7) tPZH tPLZ tPHZ MHz ns ns ns ns ns 1.0 ns 1.0 tOSLH ns Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions VCC TA = 25°C (V) Typical CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 CL = 30 pF, VIH = 2.5V, VIL =0V 2.5 0.6 CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.8 CL = 30 pF, VIH = 2.5V, VIL =0V 2.5 −0.6 Units V V Capacitance Typical Units CIN Symbol Input Capacitance Parameter VCC = Open, VI = 0V or VCC 7 pF CI/O Input/Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 20 pF www.fairchildsemi.com Conditions 6 74LCX16652 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V tPZH,tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tR = tF = 3ns) Symbol VCC 3.3V ± 0.3V 2.7V 2.5V ± 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL + 0.3V VOL + 0.3V VOL + 0.15V Vy VOH − 0.3V VOH − 0.3V VOH − 0.15V 7 www.fairchildsemi.com 74LCX16652 Schematic Diagram Generic for LCX Family www.fairchildsemi.com 8 74LCX16652 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A 9 www.fairchildsemi.com 74LCX16652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10