IDT IDT8N4Q001

Quad-Frequency Programmable XO IDT8N4Q001 REV G
DATA SHEET
General Description
Features
The IDT8N4Q001 is a Quad-Frequency Programmable Clock
Oscillator with very flexible frequency programming capabilities. The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum high clock frequency and low phase noise performance.
The device accepts 2.5V or 3.3V supply and is packaged in a small,
lead-free (RoHS 6) 10-lead ceramic 5mm x 7mm x 1.55mm package.
•
•
Fourth generation FemtoClock® NG technology
•
Four power-up default frequencies (see part number order
codes), re-programmable by I2C
•
I2C programming interface for the output clock frequency and
internal PLL control registers
•
•
•
•
•
Frequency programming resolution is 435.9Hz ÷N
•
RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.263ps
(typical), integer PLL feedback configuration
•
•
•
Full 2.5V or 3.3V supply modes
Besides the four default power-up frequencies set by the FSEL0 and
FSEL1 pins, the IDT8N4Q001 can be programmed via the I2C
interface to output clock frequencies between 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz to a very high degree of
precision with a frequency step size of 435.9Hz ÷ N (N is the PLL
output divider). Since the FSEL0 and FSEL1 pins are mapped to four
independent PLL divider registers (P, MINT, MFRAC and N),
reprogramming those registers to other frequencies under control of
FSEL0 and FSEL1 is supported. The extended temperature range
supports wireless infrastructure, telecommunication and networking
end equipment requirements.
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
One 2.5V, 3.3V LVDS clock output
Two control inputs for the power-up default frequency
LVCMOS/LVTTL compatible control inputs
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.253ps
(typical), integer PLL feedback configuration
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
Block Diagram
FemtoClock® NG
VCO
1950-2600MHz
Q
nQ
÷N
DNU 1
fXTAL
SCLK
SDATA
OE
Configuration Register (ROM)
(Frequency, APR, Polarity)
Pullup
I2C Control
Pullup
6 Q
FSEL1 5
7
25
Pulldown
7 nQ
GND 3
2
Pulldown
8 VDD
OE 2
÷MINT, MFRAC
FSEL1
FSEL0
9 SDATA
PFD
&
LPF
10 SCLK
÷P
FSEL0 4
OSC
Pin Assignment
IDT8N4Q001
10-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
Pullup
IDT8N4Q001GCD
REVISION A
MARCH 6, 2012
1
©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Table 1. Pin Descriptions
Number
Name
Type
Description
1
DNU
2
OE
Input
3
GND
Power
5, 4
FSEL1, FSEL0
Input
6, 7
Q, nQ
Output
Differential clock output. LVDS interface levels.
8
VDD
Power
Power supply pin.
9
SDATA
Input
Pullup
I2C Data Input. LVCMOS/LVTTL interface levels.
10
SCLK
Input
Pullup
I2C Clock Input. LVCMOS/LVTTL interface levels.
Do not use.
Pullup
Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels.
Power supply ground.
Pulldown
Default frequency select pins. See the Default Frequency Order Codes section.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
5.5
pF
RPULLUP
Input Pullup Resistor
50
k
RPULLDOWN
Input Pulldown Resistor
50
k
Function Tables
Table 3A. OE Configuration
Input
OE
0
1 (default)
Output Enable
Outputs Q, nQ are in high-impedance state.
Outputs are enabled.
NOTE: OE is an asynchronous control.
Table 3B. Output Frequency Range
Output Frequency Ranges
15.476MHz to 866.67MHz
975MHz to 1,300MHz
NOTE: Supported output frequency range. The output frequency
can be programmed to any frequency in this range and to a precision
of 218Hz or better.
IDT8N4Q001GCD
REVISION A MARCH 6, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Block Diagram with Programming Registers
÷P
OSC
Output Divider N
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
Q
nQ
fXTAL MHz
2
Feedback Divider M (25 Bit)
MINT 
(7 bits)
7
MFRAC 
(18 bits)


18
7
27
Programming Registers
I2C Control
P0
MINT0
MFRAC0
N0
I C:
2 bits
7 bits
18 bits
7 bits
Def:
2 bits
7 bits
18 bits
7 bits
P1
MINT1
MFRAC1
N1
I C:
2 bits
7 bits
18 bits
7 bits
Def:
2 bits
7 bits
18 bits
7 bits
P2
MINT2
MFRAC2
N2
I2C:
2 bits
7 bits
18 bits
7 bits
Def:
2 bits
7 bits
18 bits
7 bits
P3
MINT3
MFRAC3
N3
I2C:
2 bits
7 bits
18 bits
7 bits
Def:
2 bits
7 bits
18 bits
7 bits
2
30
2
30
SCLK
SDATA
Pullup
Pullup
30
30
FSEL[1:0]
OE
34
00
34
01
34
34
10
34
11
34
Pulldown, Pulldown
Pullup
Def: Power-up default register setting for I2C registers
Pn, MINTn, MFRACn and Nn
IDT8N4Q001GCD
REVISION A MARCH 6, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Principles of Operation
The block diagram consists of the internal 3rd overtone crystal and
oscillator which provide the reference clock fXTAL of either 114.285
MHz or 100MHz. The PLL includes the FemtoClock NG VCO along
with the Pre-divider (P), the feedback divider (M) and the post divider
(N). The P, M, and N dividers determine the output frequency based
on the fXTAL reference and must be configured correctly for proper
operation. The feedback divider is fractional supporting a huge
number of output frequencies. The configuration of the feedback
divider to integer-only values results in an improved output phase
noise characteristics at the expense of the range of output
frequencies. In addition, internal registers are used to hold up to four
different factory pre-set P, M, and N configuration settings. These
default pre-sets are stored in the I2C registers at power-up. Each
configuration is selected via the the FSEL[1:0] pins and can be read
back using the SCLK and SDATA pins.
As identified previously, the configurations of P, M (MINT & MFRAC)
and N divider settings are stored the I2C register, and the
configuration loaded at power-up is determined by the FSEL[1:0]
pins.
Table 4. Frequency Selection
Input
The user may choose to operate the device at an output frequency
different than that set by the factory. After power-up, the user may
write new P, N and M settings into one or more of the four
configuration registers and then use the FSEL[1:0] pins to select the
newly programmed configuration. Note that the I2C registers are
volatile and a power supply cycle will reload the pre-set factory
default conditions.
FSEL1
FSEL0
Selects
Register
0 (def.)
0 (def.)
Frequency 0
P0, MINT0, MFRAC0, N0
0
1
Frequency 1
P1, MINT1, MFRAC1, N1
1
0
Frequency 2
P2, MINT2, MFRAC2, N2
1
1
Frequency 3
P3, MINT3, MFRAC3, N3
Frequency Configuration
An order code is assigned to each frequency configuration
programmed by the factory (default frequencies). For more
information on the available default frequencies and order codes,
please see the Ordering Information Section in this document. For
available order codes, see the FemtoClock NG Ceramic-Package
XO and VCXO Ordering Product Information document.
If the user does choose to write a different P, M, and N configuration,
it is recommended to write to a configuration which is not currently
selected by FSEL[1:0] and then change to that configuration after the
I2C transaction has completed. Changing the FSEL[1:0] controls
results in an immediate change of the output frequency to the
selected register values. The P, M, and N frequency configurations
support an output frequency range 15.476MHz to 866.67MHz and
975MHz to 1,300MHz.
For more information and guidelines on programming of the device
for custom frequency configurations, the register description, the
selection of fractional and integer-feedback configurations and the
serial interface description, see the FemtoClock NG Ceramic 5x7
Module Programming Guide.
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator.
The output frequency is determined by the 2-bit pre-divider (P), the
feedback divider (M) and the 7-bit post divider (N). The feedback
divider (M) consists of both a 7-bit integer portion (MINT) and an
18-bit fractional portion (MFRAC) and provides the means for
high-resolution frequency generation. The output frequency fOUT is
calculated by:
1
MFRAC + 0.5
f OUT = f XTAL  ------------  MINT + ----------------------------------- (1)
18
PN
2
The four configuration registers for the P, M (MINT & MFRAC) and N
dividers which are named Pn, MINTn, MFRACn and Nn with n = 0 to
3. “n” denominates one of the four possible configurations.
IDT8N4Q001GCD
REVISION A MARCH 6, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond 
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for 
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
3.63V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO (SDATA)
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA

10mA
15mA
Package Thermal Impedance, JA
49.4C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 5A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Power Supply Voltage
IDD
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
160
mA
Table 5B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Power Supply Voltage
IDD
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
155
mA

















IDT8N4Q001GCD
REVISION A MARCH 6, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Table 5C. LVCMOS/LVTTL DC Characteristic, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
IIH
IIL
Test Conditions
Minimum
FSEL[1:0], OE
VCC =3.3V +5%
FSEL[1:0], OE
Maximum
Units
1.7
VCC +0.3
V
VCC =2.5V +5%
1.7
VCC +0.3
V
FSEL[1:0]
VCC =3.3V +5%
-0.3
0.5
V
OE
VCC =3.3V +5%
-0.3
0.8
V
FSEL[1:0]
VCC =2.5V +5%
-0.3
0.5
V
OE
VCC =2.5V +5%
-0.3
0.8
V
OE
VDD = VIN = 3.465V or 2.625V
10
µA
SDATA, SCLK
VDD = VIN = 3.465V or 2.625V
5
µA
FSEL0, FSEL1
VDD = VIN = 3.465V or 2.625V
150
µA
Input Low Voltage
Input High Current
Input Low Current
Typical
OE
VDD = 3.465V or 2.625V,
VIN = 0V
-500
µA
SDATA, SCLK
VDD = 3.465V or 2.625V,
VIN = 0V
-150
µA
FSEL0, FSEL1
VDD = 3.465V or 2.625V,
VIN = 0V
-5
µA

Table 5D. LVDS DC Characteristics, VDD = 3.3V ± 5%or 2.5V, ± 5%TA = -40°C to 85°C
Symbol
Parameter
VOD
Differential Output Voltage
VOD
VOD Magnitude Change
VOS
Offset Voltage
VOS
VOS Magnitude Change
IDT8N4Q001GCD
REVISION A MARCH 6, 2012
Test Conditions
Minimum
Typical
Maximum
Units
247
350
454
mV
50
mV
1.375
V
50
mV
1.0
6
1.20
©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency Q, nQ
fI
Initial Accuracy
fS
fA
fT
Temperature Stability
Aging
Total Stability
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
tjit(per)
RMS Period Jitter; NOTE 1
RMS Phase Jitter (Random):
Fractional PLL feedback and
fXTAL=100.000MHz (2xxx order 
codes)
tjit(Ø)
RMS Phase Jitter (Random);
Integer PLL feedback and
fXTAL=100.00MHz (1xxx order codes)
RMS Phase Jitter (Random)
Fractional PLL feedback and
fXTAL=114.285MHz (0xxx order codes)
Test Conditions
Minimum
Output Divider, N = 3 to126
Output Divider, N = 2
Typical
Maximum
Units
15.476
866.67
MHz
975
1,300
MHz
Measured at 25°C
±10
ppm
Option code = A or B
±100
ppm
Option code = E or F
±50
ppm
Option code = K or L
±20
ppm
Frequency drift over 10 year life
±3
ppm
Frequency drift over 15 year life
±5
ppm
Option code A or B (10 year life)
±113
ppm
Option code E or F (10 year life)
±63
ppm
Option code K or L (10 year life)
±33
ppm
20
ps
2.85
4
ps
17 MHz fOUT 1300 MHz,
NOTE 2,3,4
0.440
0.995
ps
500 MHz fOUT 1300 MHz,
NOTE 2,3,4
0.240
0.390
ps
125 MHz fOUT 500 MHz,
NOTE 2,3,4
0.245
0.425
ps
17 MHz fOUT 125 MHz,
NOTE 2,3,4
0.350
0.555
ps
fOUT 156.25 MHz, NOTE 2, 3, 4
0.253
ps
fOUT 156.25 MHz,NOTE 2, 3, 5
0.263
ps
17 MHz fOUT 1300 MHz,
NOTE 2, 3, 4
0.475
0.990
ps
N(100)
Single-side band phase noise, 
100Hz from Carrier
156.25MHz
-94.7
dBc/Hz
N(1k)
Single-side band phase noise, 
1kHz from Carrier
156.25MHz
-121.5
dBc/Hz
N(10k)
Single-side band phase noise, 
10kHz from Carrier
156.25MHz
-130.9
dBc/Hz
N(100k)
Single-side band phase noise, 
100kHz from Carrier
156.25MHz
-137.2
dBc/Hz
N(1M)
Single-side band phase noise, 
1MHz from Carrier
156.25MHz
-138.9
dBc/Hz
N(10M)
Single-side band phase noise, 
10MHz from Carrier
156.25MHz
-153.7
dBc/Hz
PSNR
Power Supply Noise Rejection
50mV Sinusoidal Noise
1kHz - 50kHz
-54
dB
tR / tF
Output Rise/Fall Time
IDT8N4Q001GCD
REVISION A MARCH 6, 2012
20% to 80%
7
100
425
ps
©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
Symbol
Parameter
odc
Output Duty Cycle
tSTARTUP
Oscillator Start-Up Time
tSET
Output frequency settling time after
FSEL0 and FSEL1 values are changed
QUAD-FREQUENCY PROGRAMMABLE-XO
Test Conditions
Minimum
Typical
45
470
Maximum
Units
55
%
20
ms
µs
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
NOTE 2: Please refer to the phase noise plots.
NOTE 3: Please see the FemtoClockNG Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the
optimum configuration for phase noise. Integer PLL feedback is the default operation for the dddd = 1xxx order codes and configures
DSM_ENA = 0 and ADC_EN = 0..
NOTE 4: Integration range: 12kHz-20MHz.
NOTE 5: Integration range: 1kHz-40MHz.
IDT8N4Q001GCD
REVISION A MARCH 6, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Noise Power dBc
Hz
Typical Phase Noise at 156.25MHz (12kHz - 20MHz)
Offset Frequency (Hz)
RMS Phase Noise (Random) for Integer PLL Feedback and fXTAL=100.000MHz.
IDT8N4Q001GCD
REVISION A MARCH 6, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Parameter Measurement Information
SCOPE
3.3V±5%
POWER SUPPLY
+ Float GND –
SCOPE
Q
VDD
Q
VDD
2.5V±5%
POWER SUPPLY
+ Float GND –
nQ
nQ
2.5V LVDS Output Load AC Test Circuit
3.3V LVDS Output Load AC Test Circuit
Phase Noise Plot
Noise Power
VOH
VREF
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Offset Frequency
f1
f2
Histogram
Reference Point
Mean Period
(Trigger Edge)
(First edge after trigger)
RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers
Period Jitter
RMS Phase Jitter
nQ
nQ
Q
Q
t PW
➤
odc =
PERIOD
t PW
tcycle n
➤
t
➤
tcycle n+1
➤
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
x 100%
t PERIOD
Cycle-to-Cycle Jitter
Output Duty Cycle/Pulse Width/Period
IDT8N4Q001GCD
REVISION A MARCH 6, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Parameter Measurement Information (continued)
VDD
nQ
out
80%
VOD
Q
DC Input
LVDS
➤
80%
20%
20%
➤
tF
tR
out
VOS/Δ VOS
➤
Offset Voltage Setup
Output Rise/Fall Time
VDD
➤
out
➤
LVDS
100
VOD/Δ VOD
out
➤
DC Input
Differential Output Voltage Setup
IDT8N4Q001GCD
REVISION A MARCH 6, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Applications Information
Recommendations for Unused Input Pins
Inputs:
LVCMOS Select Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 1A can be used
with either type of output structure. Figure 1B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO • ZT
LVDS
Driver
ZT
LVDS
Receiver
Figure 1A. Standard Termination
Z O • ZT
LVDS
Driver
C
ZT
2 LVDS
ZT Receiver
2
Figure 1B. Optional Termination
LVDS Termination
IDT8N4Q001GCD
REVISION A MARCH 6, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Schematic Layout
Figure 2 shows an example of IDT8N4Q001 application schematic.
In this example, the device is operated at VDD = 3.3V. As with any
high speed analog circuitry, the power supply pins are vulnerable to
noise. To achieve optimum jitter performance, power supply isolation
is required.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
VDD
R1
SP
R2
SP
S C LK
SD A T A
BL M18 BB22 1SN 1
V DD
C1
10
9
U1
1
C2
3. 3V
2
F e rrite Be ad
C3
0. 1u F
10 uF
S C LK
SD A T A
0 .1 uF
OE
1
2
3
DNU
OE
GN D
VD D
nQ
Q
8
7
6
Q
F SEL0
FS EL1
+
Z o_ D if f = 10 0 Ohm
R5
100
nQ
4
5
-
LVDS Termination
F SEL0
F SE L1
VCC=3.3V
Logic Control Input Examples
Set Logic
Input to
'1'
VD D
RU 1
1K
Q
Set Logic
Input to
'0'
VD D
Z o_D if f = 100 Oh m
RU2
N ot Ins ta ll
To Logic
Input
pins
RD 1
N o t I nst all
R6
50
C4
0. 1u F
R7
50
To Logic
Input
pins
+
-
nQ
RD2
1K
Alternate
LVDS
Termination
Figure 2. IDT8N4Q001 Application Schematic
IDT8N4Q001GCD
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©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8N4Q001. 
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS844S42I is the sum of the core power plus the power dissipated in the load(s). The following is the power
dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 160mA = 554.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 49.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.554W * 49.4°C/W = 112.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 10 Lead Ceramic 5mm x 7mm Package, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
IDT8N4Q001GCD
REVISION A MARCH 6, 2012
0
1
2.5
49.4°C/W
44.2°C/W
41.0°C/W
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IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Reliability Information
Table 8. JA vs. Air Flow Table for a 10-lead Ceramic 5mm x 7mm Package
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
49.4°C/W
44.2°C/W
41.0°C/W
Transistor Count
The transistor count for IDT8N4Q001 is: 47,372
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IDT8N4Q001 REV G Data Sheet
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Package Outline and Package Dimensions
IDT8N4Q001GCD
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©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products
The programmable VCXO and XO devices support a variety of
devices options such as the output type, number of default frequencies, internal crystal frequency, power supply voltage, ambient
temperature range and the frequency accuracy. The device options,
default frequencies and default VCXO pull range must be specified
at the time of order and are programmed by IDT before the shipment.
The table below specifies the available order codes, including the
device options and default frequency configurations. Example part
number: the order code 8N3QV01FG-0001CDI specifies a
programmable, quad default-frequency VCXO with a voltage supply
of 2.5V, a LVPECL output, a 50 ppm crystal frequency accuracy,
contains a 114.285MHz internal crystal as frequency source,
industrial temperature range, a lead-free (6/6 RoHS) 10-lead ceramic
5mm x 7mm x 1.55mm package and is factory-programmed to the
default frequencies of 100MHz, 122.88MHz, 125MHz and
156.25MHz and to the VCXO pull range of minimum 100 ppm.
Other default frequencies and order codes are available from IDT on
request. For more information on available default frequencies, see
the FemtoClock NG Ceramic-Package XO and VCXO Ordering
Product Information document.
Part/Order Number
8N X
X
XXX X X - dddd XX X
X
Shipping Package
8: Tape & Reel
(no letter): Tray
FemtoClock NG
Ambient Temperature Range
“I”: Industrial: (TA = -40°C to 85°C)
(no letter) : (TA = 0°C to 70°C)
I/O Identifier
0: LVCMOS
3: LVPECL
4: LVDS
Package Code
CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm
Number of Default Frequencies
S: 1: Single
D: 2: Dual
Q: 4: Quad
Part Number
Function
#pins
OE fct. at
pin
001
XO
10
OE@2
003
XO
10
OE@1
V01
VCXO
10
OE@2
V03
VCXO
10
OE@1
V75
VCXO
6
OE@2
V76
VCXO
6
nOE@2
V85
VCXO
6
—
085
XO
6
OE@1
270
XO
6
OE@1
271
XO
6
OE@2
272
XO
6
nOE@2
273
XO
6
nOE@1
IDT8N4Q001GCD
REVISION A MARCH 6, 2012
Default-Frequency and VCXO Pull Range
See document FemtoClock NG Ceramic-Package XO and VCXO
Ordering Product Information.
dddd
fXTAL (MHz)
PLL feedback
Use for
0000 to 0999
114.285
Fractional
VCXO, XO
Integer
XO
Fractional
XO
1000 to 1999
2000 to 2999
100.000
Last digit = L: configuration pre-programmed and not changable
Die Revision
G
Option Code (Supply Voltage and Frequency-Stability)
A: VCC = 3.3V±5%, ±100ppm
B: VCC = 2.5V±5%, ±100ppm
E: VCC = 3.3V±5%, ±50ppm
F: VCC = 2.5V±5%, ±50ppm
K: VCC = 3.3V±5%, ±20ppm
L: VCC = 2.5V±5%, ±20ppm
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Table 9. Device Marking
Industrial Temperature Range (TA = -40°C to 85°C)
Marking
IDT8N4x001yG-
ddddCDI
Commercial Temperature Range (TA = 0°C to 70°C)
IDT8N4x001yG-
ddddCD
x = Number of Default Frequencies, y = Option Code, dddd=Default-Frequency and VCXO Pull Range
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
IDT8N4Q001GCD
REVISION A MARCH 6, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Revision History Sheet
Rev
Table
Page
A
9
18
IDT8N4Q001GCD
Description of Change
Date
Table 9 Device Marking, corrected marking.
REVISION A MARCH 6, 2012
19
3/6/12
©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
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Copyright 2012. All rights reserved.