EVALUATION KIT AVAILABLE MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO General Description Benefits and Features The MAX2870 is an ultra-wideband phase-locked loop (PLL) with integrated voltage control oscillators (VCOs) capable of operating in both integer-N and fractional-N modes. When combined with an external reference oscillator and loop filter, the MAX2870 is a high-performance frequency synthesizer capable of synthesizing frequencies from 23.5MHz to 6.0GHz while maintaining superior phase noise and spurious performance. The ultra-wide frequency range is achieved with the help of multiple integrated VCOs covering 3000MHz to 6000MHz, and output dividers ranging from 1 to 128. The device also provides dual differential output drivers, which can be independently programmable to deliver -4dBm to +5dBm output power. Both outputs can be muted by either software or hardware control. The MAX2870 is controlled by a 3-wire serial interface and is compatible with 1.8V control logic. The device is available in a lead-free, RoHS-compliant, 5mm x 5mm, 32-pin TQFN package, and operates over an extended -40NC to +85NC temperature range. S Integer and Fractional-N Modes S Manual or Automatic VCO Selection S 3000MHz to 6000MHz Fundamental VCO S Output Binary Buffers/Dividers for Extended Frequency Range 1/2/4/8/16/32/64/128 23.5MHz to 6000MHz S High-Performance PFD 105MHz in Integer-N Mode 50MHz in Fractional-N Mode S Reference Frequency Up to 200MHz S Operates from +3.0V to +3.6V Supply S Dual Programmable Outputs -4dBm to +5dBm S Analog and Digital Lock Detect Indicators S Hardware and Software Shutdown Control S Compatible with 1.8V Control Logic Applications Wireless Infrastructure Test and Measurement Satellite Communications Wireless LANs/CATV Ordering Information appears at end of data sheet. Military and Aerospace PMAR /LMAR/Public Safety Radio Clock Generation Typical Application Circuit appears at end of data sheet. For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX2870.related. Functional Diagram MUX_OUT MUX MAX2870 LD LOCK DETECT REF_IN X2 MUX R COUNTER MUX DIVIDE-BY-2 CHARGE PUMP CP_OUT CP_GND CLK TUNE SPI AND REGISTERS DATA LE VCO INTEGER FRAC MODULUS DIV-BY1/2/4/8/16 RFOUTA_P DIV-BY1/2/4/8 RFOUTA_N RFOUT_EN MAIN MODULATOR RFOUTB_P MUX RFOUTB_N N COUNTER MUX For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-6250; Rev 1; 7/12 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO ABSOLUTE MAXIMUM RATINGS VCC_to GND_........................................................-0.3V to +3.9V All Other Pins to GND_............................... -0.3V to VCC_ + 0.3V Continuous Power Dissipation (TA = +70NC) TQFN-EP Multilayer Board (derate 34.5mW/NC above +70NC)..........................2758.6mW Junction Temperature......................................................+150NC Operating Temperature Range........................... -40NC to +85NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s)............................... +300NC Soldering temperature (reflow)........................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) TQFN Junction-to-Ambient Thermal Resistance (BJA)...........29NC/W Junction-to-Case Thermal Resistance (BJC)...................1.7NC/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. DC ELECTRICAL CHARACTERISTICS (Measured using MAX2870 EV Kit. VCC_ = 3V to 3.6V, VGND_ = 0V, fREF_IN = 50MHz, fPFD = 25MHz, TA = -40NC to +85NC. Typical values measured at VCC_ = 3.3V; TA = +25NC; register settings 00780000,20000141,01005E42,00000013,610F423C,01400005; unless otherwise noted.) (Note 2) PARAMETER CONDITIONS Supply Voltage RFOUT_ Current Consumption Supply Current MIN TYP MAX UNITS 3 3.3 3.6 V IRFOUT_, minimum output power, single channel 8.5 IRFOUT_, maximum output power, single channel 25 29 Total, including RFOUT, both channel (Note 3) 144 180 Each output divide-by-2 10 15 ICCVCO + ICCRF (Note 3) 75 95 Both channels enabled, maximum output power Low-power sleep mode mA mA 1 AC ELECTRICAL CHARACTERISTICS (Measured using MAX2870 EV Kit. VCC_ = 3V to 3.6V, VGND_ = 0V, fREF_IN = 50MHz, fPFD = 25MHz, fRFOUT_ = 6000MHz, TA = -40NC to +85NC. Typical values measured at VCC_ = 3.3V, TA = +25NC, register settings 00780000,20000141,01005E42,00000 013,610F423C,01400005; unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS REFERENCE OSCILLATOR INPUT (REF_IN) REF_IN Input Frequency Range 10 200 MHz REF_IN Input Sensitivity 0.7 VCC_ VPP +60 FA REF_IN Input Capacitance 2 REF_IN Input Current -60 pF PHASE DETECTOR Phase Detector Frequency Maxim Integrated Integer-N mode 105 Fractional-N mode 50 MHz 2 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO AC ELECTRICAL CHARACTERISTICS (continued) (Measured using MAX2870 EV Kit. VCC_ = 3V to 3.6V, VGND_ = 0V, fREF_IN = 50MHz, fPFD = 25MHz, fRFOUT_ = 6000MHz, TA = -40NC to +85NC. Typical values measured at VCC_ = 3.3V, TA = +25NC, register settings 00780000,20000141,01005E42,00000 013,610F423C,01400005; unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS CHARGE PUMP Sink/Source Current CP[3:0] = 1111, RSET = 5.1kI 5.12 CP[3:0] = 0000, RSET = 5.1kI 0.32 RSET Range mA 2.7 10 kI 3000 6000 MHz RF OUTPUTS Fundamental Frequency Range Divided Frequency Range With output dividers (1/2/4/8/16/32/64/128) 23.4375 VCO Sensitivity 6000 MHz 100 MHz/V Frequency Pushing Open loop 0.7 MHz/V Frequency Pulling Open loop into 2:1 VSWR 70 KHz 2nd Harmonic Fundamental VCO output 40 dBc 3rd Harmonic Fundamental VCO output 34 dBc 2nd Harmonic VCO output divided-by-2 20 dBc 3rd Harmonic VCO output divided-by-2 21 dBc Maximum Output Power fRFOUT_ = 3000MHz (Note 4) 5 dBm Minimum Output Power fRFOUT_ = 3000MHz (Note 4) -4 dBm -40NC P TA P +85NC 1.5 3V P VCC_ P 3.6V (Note 4) 0.2 Output Power Variation (Note 4) Muted Output Power dB -31 dBm VCO AND FREQUENCY SYNTHESIZER NOISE VCO at 3000MHz VCO Phase Noise (Note 5) VCO at 4500MHz VCO at 6000MHz 10kHz offset -83.5 100kHz offset -111 1MHz offset -136 5MHz offset -149 10kHz offset -75 100kHz offset -104 1MHz offset -130 5MHz offset -145.5 10kHz offset -71.5 100kHz offset -100.5 1MHz offset -128.0 5MHz offset -143.5 dBc/Hz In-Band Noise Floor Normalized (Note 6) -223 dBc/Hz 1/f Noise Normalized (Note 7) -116 dBc/Hz In-Band Phase Noise (Note 8) -95 dBc/Hz Integrated RMS Jitter (Note 9) 0.45 ps -87 dBc Spurious Signals Due to PFD Frequency VCO Tune Voltage Maxim Integrated 0.5 2.5 V 3 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO DIGITAL I/O CHARACTERISTICS (VCC_ = +3V to +3.6V, VGND_ = 0V, TA = -40NC to +85NC. Typical values at VCC_ = 3.3V, TA = +25NC.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS 0.6 V SERIAL INTERFACE INPUTS (CLK, DATA, LE, CE, RFOUT_EN) Input Logic-Level Low Input Logic-Level High VOH 1.5 Input Current IIH/IIL -1 Input Capacitance V +1 1 FA pF SERIAL INTERFACE OUTPUTS (MUX_OUT, LD) Output Logic-Level Low 0.3mA sink current Output Logic-Level High 0.3mA source current 0.4 VCC - 0.4 V V Output Current Level High 0.5 mA MAX UNITS SPI TIMING CHARACTERISTICS (VCC_ = +3V to +3.6V, VGND_ = 0V, TA = -40NC to +85NC. Typical values at VCC_ = 3.3V, TA = +25NC.) (Note 2) PARAMETER SYMBOL CLK Clock Period tCP CLK Pulse-Width Low CLK Pulse-Width High CONDITIONS Guaranteed by SCL pulse-width low and high MIN TYP 50 ns tCL 25 ns tCH 25 ns LE Setup Time tLES 20 ns LE Hold Time tLEH 10 ns LE Minimum Pulse-Width High tLEW 20 ns Data Setup Time tDS 25 ns Data Hold Time tDH 25 ns MUX_OUT Setup Time tMS 10 ns MUX_OUT Hold Time tMH 10 ns Note 2: Production tested at TA = +25NC. Cold and hot are guaranteed by design and characterization. Note 3: fREFIN = 40MHz, phase detector frequency = 40MHz, RF output = 3000MHz. Register setting: 00780000,20000141,01005E42,00000013,610F43FC,01400005 Note 4: Measured single ended with 27nH to VCC_RF into 50I load. Power measured with single output enabled. Unused output has 27nH to VCC_RF with 50I termination. Note 5: VCO phase noise is measured open loop. Note 6: Measured at 100kHz with 50MHz Connor-Winfield CWX813 TCXO with 500kHz loop bandwidth. Register setting: 803A0000,8000FFF9,81005F42,F4000013,6384803C,001500005 Note 7: 1/f noise contribution to the in-band phase noise is computed by using 1/fnoise + 10log(10kHz/fOFFSET) + 20log(fRF/1GHz). Register setting: 803A0000,8000FFF9,81005F42,F4000013,6384803C,001500005 Note 8: fREFIN = 50MHz; fPFD = 25MHz; offset frequency = 10kHz; VCO frequency = 4227MHz, output divide-by-2 enabled. RFOUT = 2113.5MHz; N = 169; loop BW = 40kHz, CP[3:0] = 1111; integer mode. Note 9: fREFIN = 50MHz; fPFD = 25MHz; VCO frequency = 4400MHz, fRFOUT_ = 4400MHz; N = 176; loop BW = 40kHz, CP[3:0] = 1111; integer mode. Maxim Integrated 4 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Typical Operating Characteristics (Measured with MAX2870 EV Kit. VCC_ = 3.3V, VGND_ = 0V, fREF_IN = 50MHz, TA = +25°C, see the Testing Conditions Table.) 10 100 1k 10k 1 10 100 1k 10k -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 100k 1 1k 10k 100k 3.0GHz CLOSED-LOOP PHASE NOISE vs. FREQUENCY 4.5GHz CLOSED-LOOP PHASE NOISE vs. FREQUENCY 6.0GHz CLOSED-LOOP PHASE NOISE vs. FREQUENCY -120 -130 -90 -140 -100 -110 -120 -130 -70 -140 -90 -100 -110 -120 -130 -140 -150 -150 -150 -160 -160 -160 -170 -170 10 100 1k 10k 100k -170 1 10 100 FREQUENCY (kHz) 904MHz INTEGER-N MODE PHASE NOISE AND SPUR PERFOMANCE vs. FREQUENCY -80 -100 -40 -60 -80 -140 -160 -160 FREQUENCY (kHz) Maxim Integrated 1k 10k 1k 10k 100k 2113.5MHz FRACTIONAL-N PHASE NOISE (LOW-NOISE MODE) vs. FREQUENCY -140 100 100 2687.5MHz INTEGER-N MODE PHASE NOISE AND SPUR PERFOMANCE vs. FREQUENCY -120 10 10 FREQUENCY (kHz) -100 -120 1 -70 -80 -90 PHASE NOISE (dBc/Hz) -60 100k FREQUENCY (kHz) -20 PHASE NOISE (dBc/Hz) SPURS (dBc) -40 10k MAX2780 toc08 -20 1k 0 MAX2780 toc07 0 DIV1 DIV2 DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 -80 MAX2780 toc09 -110 DIV1 DIV2 DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 PHASE NOISE (dBc/Hz) -90 -70 -80 MAX2780 toc05 DIV1 DIV2 DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 -100 PHASE NOISE (dBc/Hz) SPURS (dBc) 100 FREQUENCY (kHz) -70 1 10 FREQUENCY (kHz) -80 1 MAX2780 toc03 MAX2780 toc02 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 100k -40 FREQUENCY (kHz) PHASE NOISE (dBc/Hz) 1 6.0GHz VCO OPEN-LOOP PHASE NOISE vs. FREQUENCY PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -50 MAX2780 toc04 PHASE NOISE (dBc/Hz) -50 PHASE NOISE (dBc/Hz) -40 MAX2780 toc01 -40 4.5GHz VCO OPEN-LOOP PHASE NOISE vs. FREQUENCY MAX2780 toc06 3.0GHz VCO OPEN-LOOP PHASE NOISE vs. FREQUENCY -100 -110 -120 -130 -140 -150 -160 -170 1 10 100 FREQUENCY (kHz) 1k 10k 1 10 100 1k 10k FREQUENCY (kHz) 5 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Typical Operating Characteristics (continued) (Measured with MAX2870 EV Kit. VCC_ = 3.3V, VGND_ = 0V, fREF_IN = 50MHz, TA = +25°C, see the Testing Conditions Table.) -80 -100 -110 -120 -130 -140 -70 -80 -90 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) -90 -100 -110 -120 -130 -140 -100 -110 -120 -130 -140 -150 -150 -150 -160 -160 -160 -170 -170 1 10 100 1k 10k -170 1 10 100 1k 10k 1 10 100 1k 10k FREQUENCY (kHz) FREQUENCY (kHz) SUPPLY CURRENT vs. OUTPUT POWER SETTING (ONE CHANNEL ACTIVE, 3GHz) SUPPLY CURRENT vs. FREQUENCY (ONE CHANNEL ACTIVE, MAXIMUM OUTPUT POWER) SUPPLY CURRENT vs. OUTPUT POWER SETTING (TWO CHANNELS ACTIVE) 110 TA = -40°C 100 90 80 230 180 210 TA = +85°C 190 170 TA = +25°C 150 TA = -40°C 130 110 150 140 120 110 100 70 90 60 50 10 PWR SETTING Maxim Integrated 11 TA = -40°C 130 70 01 TA = +25°C 160 90 00 TA = +85°C 170 SUPPLY CURRENT (mA) TA = +85°C 120 250 MAX2780 toc14 TA = +25°C 130 SUPPLY CURRENT (mA) 140 MAX2780 toc15 FREQUENCY (kHz) MAX2780 toc13 PHASE NOISE (dBc/Hz) -90 2679.4MHz FRACTIONAL-N PHASE NOISE vs. FREQUENCY (LOW-SPUR MODE) MAX2780 toc11 -80 SUPPLY CURRENT (mA) -70 MAX2780 toc10 -70 2679.4MHz FRACTIONAL-N PHASE NOISE vs. FREQUENCY (LOW-NOISE MODE) MAX2780 toc12 2113.5MHz FRACTIONAL-N PHASE NOISE vs. FREQUENCY (LOW-SPUR MODE) 80 10 100 1k FREQUENCY (MHz) 10k 00 01 10 11 PWR SETTING 6 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Typical Operating Characteristics (continued) (Measured with MAX2870 EV Kit. VCC_ = 3.3V, VGND_ = 0V, fREF_IN = 50MHz, TA = +25°C, see the Testing Conditions Table.) SUPPLY CURRENT vs. FREQUENCY (TWO CHANNELS ACTIVE, MAXIMUM OUTPUT POWER) SUPPLY CURRENT (mA) 260 3.06 FREQUENCY (GHz) 280 TA = +85°C 240 220 TA = +25°C 200 180 MAX2780 toc17 MAX2780 toc16 300 PLL LOCK vs. TIME 3.08 3.04 FASTLOCK OFF 3.02 TA = -40°C 160 3.00 140 FASTLOCK ON 120 2.98 0 100 10 100 1k 50 10k 100 150 200 TIME (µs) FREQUENCY (MHz) Typical Operating Characteristics Testing Conditions Table TOC TITLE 3.0GHz VCO OPEN-LOOP PHASE NOISE vs. FREQUENCY 4.5GHz VCO OPEN-LOOP PHASE NOISE vs. FREQUENCY 6.0GHz VCO OPEN-LOOP PHASE NOISE vs. FREQUENCY Maxim Integrated fREF (MHz) N/A N/A N/A fPFD (MHz) REGISTER SETTINGS (hex) LOOP FILTER BW (Hz) MAX2870 EV KIT COMPONENT VALUES C13 (F) R1 + R2 (I) C14 (F) R0 (I) C12 (F) COMMENTS N/A 80B40000, 80000141, 0000405A, XX00013, 648020FC, 00000005 VCO bits set for 3GHz output, VAS_SHDN = 1 N/A 80B40000, 80000141, 0000405A, XX00013 648020FC, 00000005 VCO bits set for 4.5GHz output, VAS_SHDN = 1 N/A 80B40000, 80000141 0000405A XX00013, 648020FC 00000005 VCO bits set for 6.0GHz output, VAS_SHDN = 1 7 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Typical Operating Characteristics Testing Conditions Table TOC TITLE 3.0GHz CLOSED-LOOP PHASE NOISE vs. FREQUENCY 4.5GHz CLOSED-LOOP PHASE NOISE vs. FREQUENCY 6.0GHz CLOSED-LOOP PHASE NOISE vs. FREQUENCY 904MHz INTEGER-N MODE PHASE NOISE AND SPUR PERFOMANCE vs. FREQUENCY 2687.5MHz INTEGER-N PHASE NOISE AND SPUR PERFORMANCE vs. FREQUENCY 2113.5MHz FRACTIONAL-N PHASE NOISE (LOW-NOISE MODE) vs. FREQUENCY 2113.5MHz FRACTIONAL-N PHASE NOISE vs. FREQUENCY (LOW-SPUR MODE) Maxim Integrated fREF (MHz) 50 50 50 40 40 50 50 fPFD (MHz) REGISTER SETTINGS (hex) TOC TITLE MAX2870 EV KIT COMPONENT VALUES C13 (F) R1 + R2 (I) C14 (F) R0 (I) C12 (F) 25 803C0000 80000141 00009E42, E8000013, 618160FC, 00400005 40k 0.1F 120 0.012F 250 820p 25 805A0000, 80000141, 00009E42, E8000013, 618160FC, 00400005 40k 0.1F 120 0.012F 250 820p 25 80780000, 0080000141, 00009E42, EA000013, 608C80FC, 00400005 40k 0.1F 120 0.012F 250 820p 0.8 82350000, 800007D1 E1065FC2, 2C000013 6020803C 00400005 16k 0.1F 806 3300p 1201 470p 0.5 94FF0000, 803207D1, 010A1E42, B00000A3, 6090803C, 00400005 5k 0.1F 1000 6800p 300 0.01F 25 00548050, 400003E9, 81005FC2, E8000013, 609C80FC, 00400005 40k 0.1F 120 0.012F 250 820p 25 00548050, 400003E9, E1005FC2, E8000013, 609C80FC, 00400005 40k 0.1F 120 0.012F 250 820p COMMENTS 8 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Typical Operating Characteristics Testing Conditions Table TOC TITLE 2679.4MHz FRACTIONAL-N PHASE NOISE vs. FREQUENCY (LOW-NOISE MODE) fREF (MHz) 50 2679.4MHz FRACTIONAL-N PHASE NOISE vs. FREQUENCY (LOW-SPUR MODE) SUPPLY CURRENT vs. OUTPUT POWER SETTING (ONE CHANNEL ACTIVE, 3GHz) SUPPLY CURRENT vs. FREQUENCY (ONE CHANNEL ACTIVE, MAXIMUM OUTPUT POWER) SUPPLY CURRENT vs. OUTPUT POWER SETTING (TWO CHANNELS ACTIVE) SUPPLY CURRENT vs. FREQUENCY (TWO CHANNELS ACTIVE MAXIMUM OUTPUT POWER) PLL LOCK vs. TIME Maxim Integrated 50 50 50 50 40 fPFD (MHz) REGISTER SETTINGS (hex) TOC TITLE MAX2870 EV KIT COMPONENT VALUES C13 (F) R1 + R2 (I) C14 (F) R0 (I) C12 (F) COMMENTS 25 00358160, 203207D1, 01005E42, B20000A3, 6010003C, 00400005 40k 0.1F 120 0.012F 250 820p 25 00358160, 203207D1, 41005E42, B20000A3, 6010003C, 00400005 40k 0.1F 120 0.012F 250 820p 25 003C0000, 20000321, 01005E42, 00000013, 610F423C, 01400005, APWR swept from 00 to 11 25 003C0000, 20000321, 01005E42, 00000013, 610F423C, 01400005 N and F values changed for each frequency 25 003C0000, 20000321, 01005E42, 00000013, 610F43FC, 01400005 APWR and BPWR swept from 00 to 11 25 003C0000, 20000321, 01005E42, 00000013, 610F43FC, 01400005 N and F values swept for each frequency 40 00250120, 20320141, 00004042, 000000A3, 0184023C, 01400005 40k 0.1F 120 0.012F 250 820p CDM changed from 00 to 01 9 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO TUNE NOISE_FILT GND_VCO VCC_VCO 23 RSET 24 GND_TUNE BIAS_FILT TOP VIEW REG Pin Configuration 22 21 20 19 18 17 LD 25 16 RFOUT_EN 26 15 RFOUTB_N GND_DIG 27 14 RFOUTB_P 13 RFOUTA_N 12 RFOUTA_P 11 GND_RF 10 VCC_PLL 9 GND_PLL VCC_DIG 28 MAX2870 REF_IN 29 MUX_OUT 30 GND_SD 31 EP + 6 7 8 GND_CP LE 5 CP_OUT DATA 4 SW 3 VCC_CP 2 CE 1 CLK VDD_SD 32 VCC_RF TQFN Pin Description PIN NAME FUNCTION 1 CLK 2 DATA 3 LE Load Enable Input. When LE goes high the data stored in the shift register is loaded into the appropriate latches. 4 CE Chip Enable. A logic-low powers the part down and the charge pump becomes high impedance. 5 SW Fast-Lock Switch. Connect to the loop filter when using the fast-lock mode. 6 VCC_CP Power Supply for Charge Pump. Place decoupling capacitors as close as possible to the pin. 7 CP_OUT Charge-Pump Output. Connect to external loop filter input. 8 GND_CP Ground for Charge-Pump. Connect to board ground, not to the paddle. 9 GND_PLL Ground for PLL. Connect to main board ground plane, not to the paddle. 10 VCC_PLL Power Supply for PLL. Place decoupling capacitors as close as possible to the pin. 11 GND_RF Ground for RF Outputs. Connect to board ground plane, not to the paddle. Serial Clock Input. The data is latched into the 32-bit shift register on the rising edge of the CLK line. Serial Data Input. The serial data is loaded MSB first. The 3 LSBs identify the register address. 12 RFOUTA_P Open Collector Positive RF Output A. Connect to supply through RF choke or 50I load. 13 RFOUTA_N Open Collector Negative RF Output A. Connect to supply through RF choke or 50I load. Maxim Integrated 10 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Pin Description (continued) PIN NAME 14 RFOUTB_P Open Collector Positive RF Output B. Connect to supply through RF choke or 50I load. 15 RFOUTB_N Open Collector Negative RF Output B. Connect to supply through RF choke or 50I load. 16 VCC_RF 17 VCC_VCO 18 GND_VCO 19 NOISE_FILT FUNCTION Power Supply for RF Output and Dividers. Place decoupling capacitors as close as possible to the pin. VCO Power Supply. Place decoupling capacitors to the analog ground plane. Ground for VCO. Connect to external paddle. VCO Noise Decoupling. Place a 1FF capacitor to ground. 20 TUNE 21 GND_TUNE 22 RSET 23 BIAS_FILT 24 REG 25 LD 26 RFOUT_EN 27 GND_DIG Ground for Digital circuitry. Connect to main board ground plane, not directly to the paddle. 28 VCC_DIG Power Supply for Digital Circuitry. Place decoupling capacitors as close as possible to pin. 29 REF_IN Reference Frequency Input. This is a high-impedance input with a nominal bias voltage of VCC_DIG/2. AC-couple to reference signal. 30 MUX_OUT 31 GND_SD Ground for Sigma-Delta Modulator. Connect to main board ground plane, not directly to the paddle. 32 VCC_SD Power Supply for Sigma-Delta Modulator. Place decoupling capacitors as close as possible to the pin. — EP Maxim Integrated Control Input to the VCO. Connect to external loop filter. Ground for Control Input to the VCO. Connect to external paddle. Charge-Pump Current Range Input. Connect an external resistor to ground to set the minimum CP current. ICP = 1.63/RSET x (1 + CP) VCO Noise Decoupling. Place a 1FF capacitor to ground. Reference Voltage Compensation. Place a 1FF capacitor to ground. Lock Detect Output. Logic-high when locked, and logic-low when unlocked. See register description for more details (Table 9). RF Output Enable. A logic-low disables the RF outputs. Multiplexed Output and Serial Data Out. See Table 6. Exposed Pad. Connect to board ground. 11 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Detailed Description Register 0x06 can be read back through MUX_OUT. The user must set MUX = 1100. To begin the read sequence, set LE to logic-low, send 32 periods of CLK, and set LE to logic-high. While the CLK is running, the DATA pin can be held at logic-high or logic-low for 29 clocks, but the last 3 bits must be 110 to indicate register 6. Then finally, send 1 period of the clock. The MSB of register 0x06 appears on the falling edge of the next clock and continues to shift out for the next 29 clock cycles (Figure 2). After the LSB of register 0x06 has been read, the user can reset MUX = 0000. 4-Wire Serial Interface The MAX2870 serial interface contains five write-only and one read-only 32-bit registers. The 29 most-significant bits (MSBs) are data, and the three least-significant bits (LSBs) are the register address. Register data is loaded MSB first through the 4-wire serial interface (SPI). When LE is logic-low, the logic level at DATA is shifted at the rising edge of CLK. At the rising edge of LE, the 29 data bits are latched into the register selected by the address bits. The user must program all register values after power-up. Power Modes The MAX2870 can be put into low-power mode by setting SHDN = 1 (register 2, bit 5) or by setting the CE pin to logic-low. Register programming order should be address 0x05, 0x04, 0x03, 0x02, 0x01, and 0x00. Several bits are double buffered to update the settings at the same time. See the register descriptions for double buffered settings. tLES tLEH tCP LE tLEW tCL CLK tCH tDEN DATA tDH tDS Figure 1. SPI Timing Diagram DATA DON’T CARE LE tMH CLK 1 29 30 31 32 33 34 35 36 MUX_OUT tMS Figure 2. Initiating Readback Maxim Integrated 12 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO REF_IN X2 MUX R COUNTER DIVIDE-BY-2 MUX PFD Figure 3. Reference Input Reference Input The reference input stage is configured as a CMOS inverter with shunt resistance from input to output. In shutdown mode this input is set to high impedance to prevent loading of the reference source. The reference input signal path also includes optional x2 and ÷2 blocks. When the reference doubler is enabled (DBR = 1), the maximum reference input frequency is limited to 100MHz. When the doubler is disabled, the reference input frequency is limited to 200MHz. The minimum reference frequency is 10MHz. The minimum R counter divide ratio is 1, and the maximum divide ratio is 1023. Int, Frac, Mod, and R Counter Relationship The phase-detector frequency is determined as follows: fPFD = fREF O [(1 + DBR)/(R x (1 + RDIV2))] fREF represents the external reference input frequency. DBR (register 2, bit 25) sets the fREF input frequency doubler mode (0 or 1). RDIV2 (register 2, bit 24) sets the fREF divide-by-2 mode (0 or 1). R (register 2, bits 23:14) is the value of the 10-bit programmable reference counter (1 to 1023). The maximum fPFD is 50MHz for frac-N mode and 105MHz for int-N mode. The R-divider can be held in reset when RST (register 2, bit 3) = 1. The VCO frequency (fVCO), N, F, and M can be determined based on desired RF output frequency (fRFOUTA) as follows: Set DIVA value property based on fRFOUTA and DIVA register table (register 4[22.20]) fVCO = fRFOUTA x DIVA If bit FB = 1, (DIVA is not in PLL feedback loop): (N + (F/M) = fVCO/fPFD If bit FB = 0, (DIVA is in PLL feedback loop) and DIVA ≤ 16: (N + (F/M) = (fVCO/fPFD)/DIVA If bit FB = 0, (DIVA is in PLL feedback loop) and DIVA > 16: (N + (F/M) = (fVCO / fPFD)/16 Maxim Integrated N is the value of the 16-bit N counter (16 to 65535), programmable through bits 30:15 of register 0. M is the fractional modulus value (2 to 4095), programmable through bits 14:3 of register 1. F is the fractional division value (0 to MOD - 1), programmable through bits 14:3 of register 0. In frac-N mode, the minimum N value is 19 and maximum N value is 4091. The N counter is held in reset when RST = 1 (register 2, bit 3). DIVA is the RF output divider setting (0 to 7), programmable through bits 22:20 of register 4. The division ratio is set by 2DIVA. The RF B output frequency is determined as follows: If BDIV = 0 (register 4, bit 9), fRFOUTB = fRFOUTA. If BDIV = 1, fRFOUTB = fVCO. Int-N/Frac-N Modes Integer-N mode is selected by setting bit INT = 1 (register 0, bit 31). When operating in integer-N mode, it is also necessary to set bit LDF (register 2, bit 8) to set the lock detect to integer-N mode. The device’s frac-N mode is selected by setting bit INT = 0 (register 0, bit 31). Additionally, set bit LDF = 0 (register 2, bit 8) for frac-N lock-detect mode. If the device is in frac-N mode, it will remain in frac-N mode when fractional division value F = 0, which can result in unwanted spurs. To avoid this condition, the device can automatically switch to integer-N mode when F = 0 if the bit F01 = 1 (register 5, bit 24). Phase Detector and Charge Pump The device’s charge-pump current is determined by the value of the resistor from pin RSET to ground and the value of bits CP (register 2, bits 12:9) as follows: ICP = 1.63/RSET x (1 + CP) To reduce spurious in frac-N mode, set charge-pump linearity bit CPL = 1 (register 1, bits 30:29). For int-N mode, set CPL = 0. For lower noise operation in int-N mode, set charge-pump output clamp bit CPOC = 1 (register 1, bit 31) to prevent leakage current onto the loop filter. For frac-N mode, set CPOC = 0. 13 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO The charge-pump output can be put into high-impedance mode when TRI = 1 (register 2, bit 4). The output is in normal mode when TRI = 0. the loop filter capacitor. When CDM = 01 (register 3, bits 16:15), fast-lock is active after the VAS has completed. During fast-lock, the charge pump is increased to CP = 1111 and the shunt loop filter resistance is set to 1/4th the total resistance by changing pin SW from high impedance to ground. Fast-lock deactivates after a timeout set by the user. This timeout is loop filter dependent, and is set by: The phase detector polarity can be changed if an active inverting loop filter topology is used. For noninverting loop filters, set PDP = 1 (register 2, bit 6). For inverting loop filters, set PDP = 0. MUX_OUT and Lock Detect tFAST-LOCK = M x CDIV/fREF MUX_OUT is a multipurpose test output for observing various internal functions of the MAX2870. MUX_OUT can also be configured as serial data output. Bits MUX (register 2, bit 28:26) are used to select the desired MUX_OUT signal (see Table 6). where M is the modulus setting and CDIV is the clock divider setting. The user must determine the CDIV setting based on their loop filter time constant. RFOUTA± and RFOUTB± Lock detect can be monitored through the LD output by setting the LD bits (register 5, bits 23:22). For digital lock detect, set LD = 01. The digital lock detect is dependent on the mode of the synthesizer. In frac-N mode set LDF = 0, and in int-N mode set LDF = 1. To set the accuracy of the digital lock detect, see Tables 1 and 2. The device has dual differential open-collector RF outputs that require an external RF choke 50I resistor to supply for each output. Each differential output can be independently enabled or disabled by setting bits RFA_EN (register 4, bit 5) and RFB_EN (register 4, bit 8). Both outputs are also controlled by applying a logic-high (enabled) or logic-low (disabled) to pin RFOUT_EN. Analog lock detect can be set with LD = 10. In this mode, LD is an open-drain output and requires an external pullup resistor. The output power of each output can be individually controlled with APWR (register 4, bits 4:3) for RFOUTA and BPWR (register 4, bits 7:6) for RFOUTB. The available differential output power settings are from -4dBm to +5dBm, in 3dB steps with 50I pullup to supply. The available single-ended output power ranges from -4dBm to +5dBm in 3dB steps with a RF choke to supply. Across the entire frequency range different pullup elements (L or R) are required for optimal output power. If the output is used single ended, the unused output should be terminated in a corresponding load. Fast-Lock The device uses a fast-lock mode to decrease lock time. This mode requires that CP = 0000 (register 2, bits 12:9) and that the shunt resistive portion of the loop filter be segmented into two parts, where one resistor is 1/4th the total resistance, and the other resistor is 3/4th the total resistance. The larger resistor should be connected from ground to SW, and the smaller resistor from SW to Table 1. Frac-N Digital Lock-Detect Settings PFD FREQUENCY LDS LDP LOCKED UP/DOWN TIME SKEW (ns) NUMBER OF LOCKED CYCLES TO SET LD UP/DOWNTIME SKEW TO UNSET LD (ns) P 32MHz 0 0 10 40 15 P 32MHz 0 1 6 40 15 > 32MHz 1 X 4 40 4 Table 2. Int-N Digital Lock-Detect Settings PFD FREQUENCY LDS LDP LOCKED UP/DOWN TIME SKEW (ns) NUMBER OF LOCKED CYCLES TO SET LD UP/DOWNTIME SKEW TO UNSET LD (ns) P 32MHz 0 0 10 5 15 P 32MHz 0 1 6 5 15 > 32MHz 1 X 4 5 4 Maxim Integrated 14 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Voltage-Controlled Oscillator The fundamental VCO frequency of the device guarantees gap-free coverage from 3.0GHz to 6.0GHz using four individual VCO core blocks with 16 sub-bands within each block. Connect the output of the loop filter to the TUNE input. The TUNE input is used to control the VCO. Tune ADC A 3-bit ADC is used to read the VCO tuning voltage. The ADC value can be read back by bits 22:20 in register 6. The ADC uses the ranges shown in Table 3. Note that the digital or analog lock detect might still be valid when the tuning voltage is out of the compliance range. Table 3. ADC VCO Status ADC VCO STATUS 000 Out-of-lock, VTUNE < 0.5V 001 In-lock, 0.5V < VTUNE < 0.7V 010 In-lock, 0.7V < VTUNE < 1.3V 011 Not used 100 Not used 101 In-lock, 1.3V < VTUNE < 2.1V 110 In-lock, 2.1V < VTUNE < 2.5V 111 Out-of-lock, VTUNE > 2.5V VCO Autoselect (VAS) State Machine An internal VCO autoselect state machine is initiated when register 0 is programmed to automatically select the correct VCO if bit VAS_SHDN = 0 (register 3, bit 25). If VAS_SHDN = 1, then the VCO can be manually selected by bits VCO. The state machine clock, fBS, must be set to 50kHz. This is set by the BS bits. The formula for setting BS is: BS = fREF /50kHz where fREF is the reference frequency. The BS (register 4, bits 19:12) value should be rounded to the nearest integer. If the calculated BS is higher than 1023, then set BS = 1023. If fREF is lower than 50kHz, then set BS = 1. The time needed to select the correct VCO is 10/fBS. The RETUNE (register 3, bit 24) bit is used to enable or disable the VAS auto-retune function. Should the 3-bit TUNE ADC detect that the VCO control voltage (VTUNE) has drifted into the 000 or 111 state, the VAS will initiate an auto-retune if RETUNE = 1. If RETUNE = 0, then this function is disabled. Maxim Integrated Phase Shift Mode After achieving lock, the phase of the RF output can be changed in increments of P/M x 360N. The absolute phase cannot be determined, but it can be changed relative to the current phase. To change the phase, do the following: 1) Achieve lock at the desired frequency. 2) Set the increment of phase relative to the current phase by setting P = M x {desired_phase_change}/360N. 3) Enable the phase change by setting CDM = 10. 4) Reset CDM = 00. Low-Spur Mode The device offers three modes for the sigma-delta modulator. Low-noise mode offers lower in-band noise at the expense of spurs. The spurs can be reduced by setting SDN = 10 (register 2, bits 30:29) or SDN = 11 for different modes of dithering. The user can determine which mode works best for their application. 15 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Register and Bit Descriptions The operating mode of the device is controlled by five on-chip registers. Defaults are not guaranteed upon power-up and are provided for reference only. All reserved bits should only be written with default values. In low-power mode the register values are retained. Table 4. Register 0 (Address: 000, Default: 007D0000HEX) BIT LOCATION BIT ID NAME DEFINITION 31 INT Int-N or Frac-N Mode Control 0 = Enables the fractional-N mode 1 = Enables the integer-N mode The LDF bit must also be set to the appropriate mode. 30:15 N[15:0] Integer Division Value Sets integer part (N-divider) of the feedback divider factor. All integer values from 16 to 65,535 are allowed for integer mode. Integer values from 19 to 4,091 are allowed for fractional mode. 14:3 FRAC[11:0] Fractional Division Value Sets fractional value: 000000000000 = 0 (see F0I bit description) 000000000001 = 1 ---111111111110 = 4094 111111111111 = 4095 2:0 ADDR[2:0] Address Bits Register address bits Table 5. Register 1 (Address: 001, Default: 2000FFF9HEX) BIT LOCATION 31 30:29 28:27 26:15 Maxim Integrated BIT ID NAME DEFINITION CPOC CP Output Clamp Sets charge-pump output clamp mode. 0 = Disables clamping of the CP output when the CP is off 1 = Enables the clamping of the CP output when the CP is off (improved integer-N in-band phase noise) CPL[1:0] CP Linearity CPT[1:0] Charge Pump Test P[11:0] Phase Value Sets CP linearity mode. 00 = Disables the CP linearity mode (integer-N mode) 01 = Enables the CP linearity mode (frac-N mode) 10 = Reserved 11 = Reserved Sets charge-pump test modes. 00 = Normal mode 01 = Reserved 10 = Force CP into source mode 11 = Force CP into sink mode Sets phase value. See the Phase Shift Mode section. 000000000000 = 0 000000000001 = 1 (recommended) ----111111111111 = 4095 16 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Table 5. Register 1 (Address: 001, Default: 2000FFF9HEX) (continued) BIT LOCATION BIT ID NAME 14:3 M[11:0] Modulus Value (M) 2:0 ADDR[2:0] Address Bits DEFINITION Fractional modulus value used to program fVCO. See the Int, Frac, Mod, and R Counter Relationship section. Double buffered by register 0. 000000000000 = Unused 000000000001 = Unused 000000000010 = 2 ----111111111111 = 4095 Register address bits Table 6. Register 2 (Address: 010, Default: 00004042HEX) BIT LOCATION 31 30:29 BIT ID LDS SDN[1:0] NAME DEFINITION Lock-Detect Speed Lock-detect speed adjustment. 0 = fPFD P 32MHz 1 = fPFD > 32MHz Frac-N Noise Mode Sets noise mode (See the Low-Spur Mode section.) 00 = Low-noise mode 01 = Reserved 10 = Low-spur mode 1 11 = Low-spur mode 2 28:26 MUX[3:0] MUX_OUT Configuration Sets MUX_OUT pin configuration (MSB bit located register 05). 0000 = Three-state output 0001 = D_VDD 0010 = D_GND 0011 = R-divider output 0100 = N-divider output 0101 = Analog lock detect 0110 = Digital lock detect 0111:1011 = Reserved 1100 = Read register 06 MUX_OUT is configured as serial data out. 1101:1111 = Reserved 25 DBR Reference Doubler Mode Sets reference doubler mode. 0 = Disable reference doubler 1 = Enable reference doubler 24 RDIV2 Reference Div2 Mode Sets reference divider mode. 0 = Disable reference divide-by-2 1 = Enable reference divide-by-2 23:14 Maxim Integrated R[9:0] Reference Divider Mode Sets reference 0000000000 = 0000000001 = ----1111111111 = divide value (R). Double buffered by register 0. 0 (unused) 1 1023 17 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Table 6. Register 2 (Address: 010, Default: 00004042HEX) (continued) BIT LOCATION 13 BIT ID REG4DB NAME DEFINITION Double Buffer Sets double buffer mode. 0 = Disabled 1 = Enabled Sets charge-pump current in mA (RSET = 5.1kI). Double buffered by register 0. 0000 = 0.32 0001 = 0.64 0010 = 0.96 0011 = 1.28 0100 = 1.60 0101 = 1.92 0110 = 2.24 0111 = 2.56 [ICP = 1.63/RSET x (1 + CP<3:0>)] 1000 = 2.88 1001 = 3.20 1010 = 3.52 1011 = 3.84 1100 = 4.16 1101 = 4.48 1110 = 4.80 1111 = 5.12 12:9 CP[3:0] Charge-Pump Current 8 LDF Lock-Detect Function Sets lock-detect function. 0 = Frac-N lock detect 1 = Int-N lock detect 7 LDP Lock-Detect Precision Sets lock-detect precision. 0 = 10nS 1 = 6nS 6 PDP Phase Detector Polarity 5 SHDN Power-Down Mode 4 TRI Charge-Pump Three-State Mode Sets charge-pump three-state mode. 0 = Disabled 1 = Enabled 3 RST Counter Reset Sets counter reset mode. 0 = Normal operation 1 = R and N counters reset 2:0 ADDR Address Bits Maxim Integrated Sets phase detector polarity. 0 = Negative (for use with inverting active loop filters) 1 = Positive (for use with passive loop filers and noninverting active loop filters) Sets power-down mode. 0 = Normal mode 1 = Device shutdown Register address 18 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Table 7. Register 3 (Address: 011, Default: 0000000BHEX) BIT LOCATION BIT ID NAME DEFINITION Manual selection of VCO and VCO sub-band when VAS is disabled. 000000 = VCO0 …. 111111 = VCO63 31:26 VCO[5:0] VCO 25 VAS_SHDN VAS_SHDN 24 RETUNE RETUNE Sets VAS response to temperature drift. 0 = VAS auto-retune over temp disabled 1 = VAS auto-retune over temp enabled 23:18 Reserved Reserved Reserved. Program to 000000. 17 Reserved Reserved Reserved. Program to 0. Clock Divider Mode Sets clock divider mode. 00 = Clock divider off 01 = Fast-lock enabled 10 = Phase mode 11 = Reserved 16:15 CDM[1:0] Sets VAS state machine mode. 0 = VAS enabled 1 = VAS disabled 14:3 CDIV[11:0] Clock Divider Value Sets 12-bit clock divider value. 000000000000 = Unused 000000000001 = 1 000000000010 = 2 ----111111111111 = 4095 2:0 ADDR[2:0] Address Bits Register address Maxim Integrated 19 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Table 8. Register 4 (Address: 100, Default: 6180B23CHEX) BIT LOCATION BIT ID NAME 31:26 Reserved Reserved 25:24 BS_MSBs[1:0] Band-Select MSBs 23 FB VCO Feedback Mode Sets VCO to N counter feedback mode. 0 = Divided 1 = Fundamental RFOUT_ Output Divider Mode Sets RFOUT_ output divider mode. Double buffered by register 0 when REG4DB = 1. 000 = Divide by 1, if 3000MHz ≤ fRFOUTA ≤ 6000MHz 001 = Divide by 2, if 1500MHz ≤ fRFOUTA < 3000MHz 010 = Divide by 4, if 750MHz ≤ fRFOUTA < 1500MHz 011 = Divide by 8, if 375MHz ≤ fRFOUTA < 750MHz 100 = Divide by 16, if 187.5MHz ≤ fRFOUTA < 375MHz 101 = Divide by 32, if 93.75MHz ≤ fRFOUTA < 187.5MHz 110 = Divide by 64, if 46.875MHz ≤ fRFOUTA < 93.75MHz 111 = Divide by 128, if 23.5MHz ≤ fRFOUTA < 46.875MHz 22:20 DIVA[2:0] DEFINITION Reserved. Program to 011000. Band-select MSBs. See bits [19:12]. Sets band select clock divider value. MSB are located in bits [25:24]. 0000000000 = Reserved 0000000001 =1 0000000010 = 2 ---1111111111 = 1023 19:12 BS[7:0] Band Select 11 Reserved Reserved Reserved. Program to 0. 10 Reserved Reserved Reserved. Program to 0. 9 BDIV RFOUTB Output Path Select Sets RFOUTB output path select. 0 = VCO divided output 1 = VCO fundamental frequency 8 RFB_EN RFOUTB Output Mode Sets RFOUTB output mode. 0 = Disabled 1 = Enabled 7:6 BPWR[1:0] RFOUTB Output Power Sets RFOUTB single-ended output power. See the RFOUTAQ and RFOUTBQ section. 00 = -4dBm 01 = -1dBm 10 = +2dBm 11 = +5dBm 5 RFA_EN RFOUTA Output Mode Sets RFOUTA output mode. 0 = Disabled 1 = Enabled 4:3 APWR[1:0] RFOUTA Output Power 2:0 ADDR[2:0] Register Address Maxim Integrated Sets RFOUTA single-ended output power. See the RFOUTAQ and RFOUTBQ section. 00 = -4dBm 01 = -1dBm 10 = +2dBm 11 = +5dBm Register address 20 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Table 9. Register 5 (Address: 101, Default: 00400005HEX) BIT LOCATION BIT ID NAME 31:25 Reserved Reserved 24 F01 F01 Lock-Detect Pin Function DEFINITION Reserved. Program to 0000000. Sets integer mode for F = 0. 0 = If F[11:0] = 0, then fractional-N mode is set 1 = If F[11:0] = 0, then integer-N mode is auto set Sets lock-detect pin function. 00 = Low 01 = Digital lock detect 10 = Analog lock detect 11 = High 23:22 LD[1:0] 21:19 Reserved Reserved Reserved. Program to 000. 18 MUX MUX MSB Sets mode at MUX_OUT pin (see register 2 [28:26]) 17:3 Reserved Reserved Reserved 2:0 ADDR[2:0] Register Address Register address bits Table 10. Register 6 (Read-Only Register) BIT LOCATION BIT ID NAME 31:24 — Reserved 23 POR Power_On_ Reset 22:20 ADC[2:0] VTUNE_ADC 19:9 — Reserved 8:3 V[5:0] Active VCO 2:0 ADDR[2:0] Register Address Maxim Integrated DEFINITION Reserved POR readback status. 0 = POR has been read back 1 = POR has not been read back (registers at default) Reads back the ADC reading of the VTUNE (see the Tune ADC section) Reserved Reads back the current active VCO. 000000 = VCO0 …… 111111 = VCO63 Register address bits 21 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Typical Application Circuit 24 TO GPIO FROM GPIO LD RFOUT_EN 23 22 21 20 19 VCC_VCO GND_VCO NOISE_FILT TUNE GND_TUNE RSET REG BIAS_FILT VCC_RF 18 VCC_RF 17 25 16 26 15 VCC_RF RFOUTB_N RFOUTB GND_DIG VCC_DIG VCC_DIG REF_IN MUX_OUT GND_SD 27 14 28 13 MAX2870 29 12 30 11 31 10 EP RFOUTB_P RFOUTA_N RFOUTA RFOUTA_P GND_RF VCC_PLL VCC_PLL VCC_DIG VDD_SD 9 32 GND_PLL VCC_RF 8 GND_CP 7 CP_OUT 6 VCC_CP 5 SW 4 CE 3 LE DATA 2 CLK 1 VCC_PLL FROM GPIO SPI INTERFACE FOR BEST PERFORMANCE GENERATE THREE SUPPLIES USING SEPARATE LDOs. VCC_RF VCC_DIG VCC_PLL Maxim Integrated 22 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Package Information Ordering Information PART TEMP RANGE PIN-PACKAGE MAX2870ETJ+ -40NC to +85NC 32 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Maxim Integrated For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 32 TQFN T3255+5 21-0140 90-0013 23 MAX2870 23.5MHz to 6000MHz Fractional/ Integer-N Synthesizer /VCO Revision History REVISION NUMBER REVISION DATE 0 4/12 Initial release 1 7/12 Updated Int, Frac, Mod and R Counter Relationship section; updated formula in VCO Autoselect (VAS) State Machine section, updated Table 8 DESCRIPTION PAGES CHANGED — 13, 15, 20 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2012 Maxim Integrated Products, Inc. 24 The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.