Wideband Synthesizer with Integrated VCO ADF4350 FEATURES GENERAL DESCRIPTION Output frequency range: 137.5 MHz to 4400 MHz Fractional-N synthesizer and integer-N synthesizer Low phase noise VCO Programmable divide-by-1/-2/-4/-8/-16 output Typical rms jitter: 0.5 ps rms Power supply: 3.0 V to 3.6 V Logic compatibility: 1.8 V Programmable dual-modulus prescaler of 4/5 or 8/9 Programmable output power level RF output mute function 3-wire serial interface Analog and digital lock detect Switched bandwidth fast-lock mode Cycle slip reduction The ADF4350 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers if used with an external loop filter and external reference frequency. The ADF4350 has an integrated voltage controlled oscillator (VCO) with a fundamental output frequency ranging from 2200 MHz to 4400 MHz. In addition, divide-by-1/2/4/8 or 16 circuits allow the user to generate RF output frequencies as low as 137.5 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin- and software-controllable. An auxiliary RF output is also available, which can be powered down if not in use. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use. APPLICATIONS Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Test equipment Wireless LANs, CATV equipment Clock generation FUNCTIONAL BLOCK DIAGRAM SDVDD 10-BIT R COUNTER ×2 DOUBLER DVDD VP RSET VVCO MULTIPLEXER ÷2 DIVIDER MUXOUT LOCK DETECT SW FLO SWITCH LD CLK DATA LE DATA REGISTER FUNCTION LATCH CHARGE PUMP CPOUT PHASE COMPARATOR INTEGER REG FRACTION REG VTUNE VREF VCOM VCO CORE MODULUS REG THIRD-ORDER FRACTIONAL INTERPOLATOR TEMP MULTIPLEXER N COUNTER MULTIPLEXER CE AGND OUTPUT STAGE ÷1/2/4/8/16 DGND SDGND CPGND RFOUTA– PDBRF OUTPUT STAGE ADF4350 AGNDVCO RFOUTA+ RFOUTB+ RFOUTB– 07325-001 REFIN AVDD Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. ADF4350 TABLE OF CONTENTS Features .............................................................................................. 1 Register 1 ..................................................................................... 18 Applications ....................................................................................... 1 Register 2 ..................................................................................... 18 General Description ......................................................................... 1 Register 3 ..................................................................................... 20 Functional Block Diagram .............................................................. 1 Register 4 ..................................................................................... 20 Revision History ............................................................................... 2 Register 5 ..................................................................................... 20 Specifications..................................................................................... 3 Initialization Sequence .............................................................. 21 Timing Characteristics ................................................................ 5 RF Synthesizer—A Worked Example ...................................... 21 Absolute Maximum Ratings............................................................ 6 Modulus ....................................................................................... 21 Transistor Count ........................................................................... 6 Reference Doubler and Reference Divider ............................. 21 ESD Caution .................................................................................. 6 12-Bit Programmable Modulus ................................................ 21 Pin Configuration and Function Descriptions ............................. 7 Cycle Slip Reduction for Faster Lock Times ........................... 22 Typical Performance Characteristics ............................................. 9 Spurious Optimization and Fast lock ...................................... 22 Circuit Description ......................................................................... 11 Fast-Lock Timer and Register Sequences ............................... 22 Reference Input Section ............................................................. 11 Fast Lock—An Example ............................................................ 22 RF N Divider ............................................................................... 11 Fast Lock—Loop Filter Topology............................................. 23 INT, FRAC, MOD, and R Counter Relationship.................... 11 Spur Mechanisms ....................................................................... 23 INT N MODE ............................................................................. 11 Spur Consistency and Fractional Spur Optimization ........... 24 R Counter .................................................................................... 11 Phase Resync ............................................................................... 24 Phase Frequency Detector (PFD) and Charge Pump ............ 11 Applications Information .............................................................. 25 MUXOUT and LOCK Detect ................................................... 12 Direct Conversion Modulator .................................................. 25 Input Shift Registers ................................................................... 12 Interfacing ................................................................................... 26 Program Modes .......................................................................... 12 PCB Design Guidelines for a Chip Scale Package ................. 26 VCO.............................................................................................. 12 Output Matching ........................................................................ 27 Output Stage ................................................................................ 13 Outline Dimensions ....................................................................... 28 Register Maps .................................................................................. 14 Ordering Guide .......................................................................... 28 Register 0 ..................................................................................... 18 REVISION HISTORY 11/08—Revision 0: Initial Version Rev. 0 | Page 2 of 28 ADF4350 SPECIFICATIONS AVDD = DVDD = VVCO = SDVDD = VP = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is −40°C to +85°C. Table 1. Parameter REFIN CHARACTERISTICS Input Frequency Input Sensitivity Input Capacitance Input Current PHASE DETECTOR Phase Detector Frequency 2 CHARGE PUMP ICP Sink/Source 3 High Value Low Value RSET Range Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output High Current, IOH Output Low Voltage, VOL POWER SUPPLIES AVDD DVDD, VVCO, SDVDD, VP DIDD + AIDD 4 Output Dividers IVCO4 IRFOUT4 Low Power Sleep Mode RF OUTPUT CHARACTERISTICS Maximum VCO Output Frequency Minimum VCO Output Frequency Minimum VCO Output Frequency Using Dividers VCO Sensitivity Frequency Pushing (Open-Loop) Frequency Pulling (Open-Loop) Harmonic Content (Second) Harmonic Content (Third) Harmonic Content (Second) Harmonic Content (Third) Minimum RF Output Power 5 Maximum RF Output Power5 Output Power Variation Minimum VCO Tuning Voltage Maximum VCO Tuning Voltage Min B Version Typ 10 0.7 Max Unit Conditions/Comments 105 AVDD For f < 10 MHz ensure slew rate > 21 V/μs Biased at AVDD/2 1 ±60 MHz V p-p pF μA 32 MHz 10 With RSET = 5.1 kΩ 5 0.312 2.7 10 2 1.5 2 1.5 0.6 ±1 3.0 DVDD − 0.4 3.0 AVDD 21 6 to 24 70 21 7 33 1 90 −19 −13 −20 −10 −4 5 ±1 0.5 2.5 0.5 V ≤ VCP ≤ 2.5 V 0.5 V ≤ VCP ≤ 2.5 V VCP = 2.0 V V V μA pF 500 0.4 V μA V 3.6 V 27 mA mA mA mA μA CMOS output chosen IOL = 500 μA These voltages must equal AVDD 80 26 1000 4400 2200 137.5 mA mA kΩ % % % MHz MHz MHz MHz/V MHz/V kHz dBc dBc dBc dBc dBm dBm dB V V Rev. 0 | Page 3 of 28 Each output divide-by-2 consumes 6 mA RF output stage is programmable Fundamental VCO mode 2200 MHz fundamental output and divide by 16 selected Into 2.00 VSWR load Fundamental VCO output Fundamental VCO output Divided VCO output Divided VCO output Programmable in 3 dB steps ADF4350 Parameter NOISE CHARACTERISTICS VCO Phase-Noise Performance 6 Normalized In-Band Phase Noise Floor 7 In-Band Phase Noise 8 Integrated RMS Jitter 9 Spurious Signals Due to PFD Frequency Level of Signal With RF Mute Enabled Min B Version Typ −89 −114 −134 −148 −86 −111 −134 −145 −83 −110 −132 −145 −213 −97 0.5 −70 −40 Max Unit Conditions/Comments dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ps dBc dBm 10 kHz offset from 2.2 GHz carrier 100 kHz offset from 2.2 GHz carrier 1 MHz offset from 2.2 GHz carrier 5 MHz offset from 2.2 GHz carrier 10 kHz offset from 3.3 GHz carrier 100 kHz offset from 3.3 GHz carrier 1 MHz offset from 3.3 GHz carrier 5 MHz offset from 3.3 GHz carrier 10 kHz offset from 4.4 GHz carrier 100 kHz offset from 4.4 GHz carrier 1 MHz offset from 4.4 GHz carrier 5 MHz offset from 4.4 GHz carrier 1 3 kHz offset from 2113.5 MHz carrier AC coupling ensures AVDD/2 bias. Guaranteed by design. Sample tested to ensure compliance. ICP is internally modified to maintain constant loop gain over the frequency range. 4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V; prescaler = 8/9; fREFIN = 100 MHz; fPFD = 25 MHz; fRF = 4.4 GHz. 5 Using 50 Ω resistors to VVCO, into a 50 Ω load. Power measured with auxiliary RF output disabled. The current consumption of the auxiliary output is the same as for the main output. 6 The noise of the VCO is measured in open-loop conditions. 7 This figure can be used to calculate phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output use the following formula: −213 + 10log(fPFD) + 20logN . The value given is the lowest noise mode. 8 fREFIN = 100 MHz; fPFD = 25 MHz; offset frequency = 10 kHz; VCO frequency = 4227 MHz, output divide by two enabled. RFOUT = 2113.5 MHz; N = 169; loop BW = 40 kHz, ICP = 313 μA; low noise mode. The noise was measured with an EVAL-ADF4350EB1Z and the Agilent E5052A signal source analyzer. 9 fREFIN = 100 MHz; fPFD = 25 MHz; VCO frequency = 4400 MHz, RFOUT = 4400 MHz; N = 176; loop BW = 40 kHz, ICP = 313 μA; low noise mode. The noise was measured with an EVAL-ADF4350EB1Z and the Agilent E5052A signal source analyzer. 2 3 Rev. 0 | Page 4 of 28 ADF4350 TIMING CHARACTERISTICS AVDD = DVDD = VVCO = SDVDD = VP = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 Limit (B Version) 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min t4 Test Conditions/Comments LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width t5 CLK t2 DATA DB31 (MSB) t3 DB30 DB2 (CONTROL BIT C3) DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 07325-002 t6 LE Figure 2. Timing Diagram Rev. 0 | Page 5 of 28 ADF4350 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND1 AVDD to DVDD VVCO to GND VVCO to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN to GND Operating Temperature Range Storage Temperature Range Maximum Junction Temperature LFCSP θJA Thermal Impedance (Paddle-Soldered) Reflow Soldering Peak Temperature Time at Peak Temperature 1 Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +85°C −65°C to +125°C 150°C 27.3°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high-performance RF integrated circuit with an ESD rating of <0.5 kV and is ESD sensitive. Proper precautions should be taken for handling and assembly. TRANSISTOR COUNT 24202 (CMOS) and 918 (bipolar) ESD CAUTION 260°C 40 sec GND = AGND = DGND = 0 V Rev. 0 | Page 6 of 28 ADF4350 32 31 30 29 28 27 26 25 SDVDD SDGND MUXOUT REFIN DVDD DGND PDBRF LD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 3 4 5 6 VREF 23 VCOM 22 RSET 24 PIN 1 INDICATOR ADF4350 TOP VIEW (Not to Scale) 7 21 AGNDVCO 20 VTUNE 19 TEMP 18 AGNDVCO 17 VVCO AGND 9 AVDD 10 AGNDVCO 11 8 07325-003 1 2 RFOUTA+ 12 RFOUTA− 13 RFOUTB+ 14 RFOUTB− 15 VVCO 16 CLK DATA LE CE SW VP CPOUT CPGND NOTES 1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND. Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic CLK 2 DATA 3 LE 4 CE 5 6 SW VP 7 CPOUT 8 9 10 CPGND AGND AVDD 11, 18, 21 12 13 AGNDVCO RFOUTA+ RFOUTA− 14 RFOUTB+ 15 RFOUTB− 16, 17 VVCO 19 TEMP 20 VTUNE Description Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is selected by the three LSBs. Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A logic high on this pin powers up the device depending on the status of the power-down bits. Fast-Lock Switch. A connection should be made from the loop filter to this pin when using the fast-lock mode. Charge Pump Power Supply. This pin is to be equal to AVDD. Decoupling capacitors to the ground plane are to be placed as close as possible to this pin. Charge Pump Output. When enabled, this provides ±ICP to the external loop filter. The output of the loop filter is connected to VTUNE to drive the internal VCO. Charge Pump Ground. This is the ground return pin for CPOUT. Analog Ground. This is a ground return pin for AVDD. Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane are to be placed as close as possible to this pin. AVDD must have the same value as DVDD. VCO Analog Ground. These are the ground return pins for the VCO. VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available. Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available. Auxilliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available. Complementary Auxilliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available. Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to these pins. VVCO must have the same value as AVDD. Temperature Compensation Output. Decoupling capacitors to the ground plane are to be placed as close as possible to this pin. Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT output voltage. Rev. 0 | Page 7 of 28 ADF4350 Pin No. 22 Mnemonic RSET Description Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage bias at the RSET pin is 0.55 V. The relationship between ICP and RSET is I CP = 23 VCOM 24 25 26 27 28 VREF LD PDBRF DGND DVDD 29 REFIN 30 MUXOUT 31 32 SDGND SDVDD 33 EP 25.5 R SET where: RSET = 5.1 kΩ ICP = 5 mA Internal Compensation Node Biased at Half the Tuning Range. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. Reference Voltage. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock. A logic low output indicates loss of PLL lock. RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable. Digital Ground. Ground return path for DVDD. Digital Power Supply. This pin should be the same voltage as AVDD. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. Digital Sigma-Delta (Σ-Δ) Modulator Ground. Ground return path for the Σ-Δ modulator. Power Supply Pin for the Digital Σ-Δ Modulator. Should be the same voltage as AVDD. Decoupling capacitors to the ground plane are to be placed as close as possible to this pin. Exposed Pad. Rev. 0 | Page 8 of 28 ADF4350 TYPICAL PERFORMANCE CHARACTERISTICS –40 –70 –50 –80 –90 –70 PHASE NOISE (dBc/Hz) –80 –90 –100 –110 –120 –130 –130 –140 1M 10M 100M –170 1k 100k 1M 10M Figure 7. Closed-Loop Phase Noise, Fundamental VCO and Dividers, VCO = 2.2 GHz, PFD = 25 MHz, Loop Bandwidth = 40 kHz –40 –70 –50 –80 –60 FUND DIV2 DIV4 DIV8 DIV16 –90 PHASE NOISE (dBc/Hz) –70 –80 –90 –100 –110 –120 –130 –100 –110 –120 –130 –140 –150 –140 100k 1M 10M 100M FREQUENCY (Hz) –170 07325-029 10k 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 5. Open-Loop VCO Phase Noise, 3.3 GHz 07325-032 –160 –150 Figure 8. Closed-Loop Phase Noise, Fundamental VCO and Dividers, VCO = 3.3 GHz, PFD = 25 MHz, Loop Bandwidth = 40 kHz –40 –70 –50 –80 –60 FUND DIV2 DIV4 DIV8 DIV16 –90 PHASE NOISE (dBc/Hz) –70 –80 –90 –100 –110 –120 –130 –100 –110 –120 –130 –140 –150 –140 –160 10k 100k 1M 10M FREQUENCY (Hz) 100M 07325-030 –150 –160 1k 100M FREQUENCY (Hz) Figure 4. Open-Loop VCO Phase Noise, 2.2 GHz –160 1k 10k 07325-031 100k 07325-028 10k FREQUENCY (Hz) PHASE NOISE (dBc/Hz) –120 –160 –150 PHASE NOISE (dBc/Hz) –110 –150 –140 –160 1k –100 Figure 6. Open-Loop VCO Phase Noise, 4.4 GHz –170 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 07325-033 PHASE NOISE (dBc/Hz) –60 FUND DIV2 DIV4 DIV8 DIV16 Figure 9. Closed-Loop Phase Noise, Fundamental VCO and Dividers, VCO = 4.4 GHz, PFD = 25 MHz, Loop Bandwidth = 40 kHz Rev. 0 | Page 9 of 28 0 0 –20 –20 –40 –40 PHASE NOISE (dBc/Hz) –60 –80 –100 –120 10k 100k FREQUENCY (Hz) 1M 10M –120 –160 07325-034 1k Figure 10. Integer-N Phase Noise and Spur Performance. GSM900 Band, RFOUT = 904 MHz, REFIN = 100 MHz, PFD = 800 kHz, Output Divide-by-4 Selected; Loop-Filter Bandwidth = 16 kHz, Channel Spacing = 200 kHz. 1k 0 0 –20 –20 –40 –40 –60 –80 –100 –120 10k 100k FREQUENCY (Hz) 1M 10M Figure 13. Fractional-N Spur Performance. Low Noise Mode, RFOUT = 2.591 GHz, REFIN = 105 MHz, PFD = 17.5 MHz, Output Divide-by-1 Selected; Loop Filter Bandwidth = 20 kHz, Channel Spacing = 100 kHz. PHASE NOISE (dBc/Hz) –60 –80 –100 –120 –140 –140 1k 10k 100k FREQUENCY (Hz) 1M 10M –160 07325-035 –160 Figure 11. Fractional-N Spur Performance; Low Noise Mode. W-CDMA Band, RFOUT = 2113.5 MHz, REFIN = 100 MHz, PFD = 25 MHz, Output Divide-by-2 Selected; Loop Filter Bandwidth = 40 kHz, Channel Spacing = 200 kHz. 1k 3.02 –20 3.01 FREQUENCY (GHz) –40 –80 –100 100k FREQUENCY (Hz) 1M 10M Figure 14. Fractional-N Spur Performance. Low Spur Mode RFOUT = 2.591 GHz, REFIN = 105 MHz, PFD = 17.5 MHz, Output Divide-by-1 Selected. Loop Filter Bandwidth = 20 kHz, Channel Spacing = 100 kHz (Note That Fractional Spurs Are Removed and Only the Integer Boundary Spur Remains in Low Spur Mode). 0 –60 10k 07325-038 PHASE NOISE (dBc/Hz) –100 –140 –160 PHASE NOISE (dBc/Hz) –80 07325-037 –140 –60 –120 CSR OFF CSR ON 3.00 2.99 2.98 2.97 2.96 –140 1k 10k 100k FREQUENCY (Hz) 1M 10M 2.95 07325-036 –160 Figure 12. Fractional-N Spur Performance. Low Spur Mode, W-CDMA Band RFOUT = 2113.5 MHz, REFIN = 100 MHz, PFD = 25 MHz, Output Divide-by-2 Selected; Loop Filter Bandwidth = 40 kHz, Channel Spacing = 200 kHz 0 100 200 300 TIME (µs) 400 500 600 07325-039 PHASE NOISE (dBc/Hz) ADF4350 Figure 15. Lock Time for 100 MHz Jump from 3070 MHz to 2970 MHz with CSR On and Of f, PFD = 25 MHz, ICP = 313 μA, Loop Filter Bandwidth = 20 kHz Rev. 0 | Page 10 of 28 ADF4350 CIRCUIT DESCRIPTION RF N DIVIDER REFERENCE INPUT SECTION The reference input stage is shown in Figure 16. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed, and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin during power-down. FROM VCO OUTPUT/ OUTPUT DIVIDERS THIRD-ORDER FRACTIONAL INTERPOLATOR INT REG FRAC VALUE 07325-006 MOD REG 100kΩ SW2 Figure 17. RF INT Divider TO R COUNTER BUFFER SW3 NO INT N MODE If the FRAC = 0 and DB8 in Register 2 (LDF) is set to 1, the synthesizer operates in integer-N mode. The DB8 in Register 2 (LDF) should be set to 1 to get integer-N digital lock detect. Figure 16. Reference Input Stage RF N DIVIDER The RF N divider allows a division ratio in the PLL feedback path. The division ratio is determined by INT, FRAC and MOD values, which build up this divider. INT, FRAC, MOD, AND R COUNTER RELATIONSHIP The INT, FRAC, and MOD values, in conjunction with the R counter, make it possible to generate output frequencies that are spaced by fractions of the PFD frequency. See the RF Synthesizer—A Worked Example section for more information. The RF VCO frequency (RFOUT) equation is RFOUT = fPFD × (INT + (FRAC/MOD)) (1) where RFOUT is the output frequency of external voltage controlled oscillator (VCO). INT is the preset divide ratio of the binary 16-bit counter (23 to 65535 for 4/5 prescaler, 75 to 65,535 for 8/9 prescaler). MOD is the preset fractional modulus (2 to 4095). FRAC is the numerator of the fractional division (0 to MOD − 1). fPFD = REFIN × [(1 + D)/(R × (1 + T))] (2) R COUNTER The 10–bit R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the PFD. Division ratios from 1 to 1023 are allowed. PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The phase frequency detector (PFD) takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 18 is a simplified schematic of the phase frequency detector. The PFD includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns. This pulse ensures there is no dead zone in the PFD transfer function, and gives a consistent reference spur level. HIGH D1 Q1 UP U1 +IN where: REFIN is the reference input frequency. D is the REFIN doubler bit. T is the REFIN divide-by-2 bit (0 or 1). R is the preset divide ratio of the binary 10-bit programmable reference counter (1 to 1023). CLR1 DELAY HIGH U3 CHARGE PUMP CLR2 DOWN D2 Q2 U2 –IN Figure 18. PFD Simplified Schematic Rev. 0 | Page 11 of 28 CP 07325-007 SW1 07325-005 REFIN NC TO PFD N COUNTER POWER-DOWN CONTROL NC N = INT + FRAC/MOD ADF4350 (R0) must be written to, to ensure the modulus value is loaded correctly. Divider select in Register 4 (R4) is also double buffered, but only if DB13 of Register 2 (R2) is high. MUXOUT AND LOCK DETECT The output multiplexer on the ADF4350 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 (for details, see Figure 26). Figure 19 shows the MUXOUT section in block diagram form. VCO The VCO core in the ADF4350 consists of three separate VCOs each of which uses 16 overlapping bands, as shown in Figure 20, to allow a wide frequency range to be covered without a large VCO sensitivity (KV) and resultant poor phase noise and spurious performance. R COUNTER INPUT DVDD THREE-STATE-OUTPUT The correct VCO and band are chosen automatically by the VCO and band select logic at power-up or whenever Register 0 (R0) is updated. DVDD DGND R COUNTER OUTPUT MUX CONTROL MUXOUT N COUNTER OUTPUT ANALOG LOCK DETECT DIGITAL LOCK DETECT VCO and band selection take 10 PFD cycles × band select clock divider value. The VCO VTUNE is disconnected from the output of the loop filter and is connected to an internal reference voltage. 2.8 2.4 2.0 Table 5. C3, C2, and C1 Truth Table C3 0 0 0 0 1 1 Control Bits C2 0 0 1 1 0 0 C1 0 1 0 1 0 1 Register Register 0 (R0) Register 1 (R1) Register 2 (R2) Register 3 (R3) Register 4 (R4) Register 5 (R5) PROGRAM MODES Table 5 and Figure 23 through Figure 29 show how the program modes are to be set up in the ADF4350. 1.6 1.2 0.8 FREQUENCY (MHz) 4600 4400 4200 4000 3800 3600 3400 3200 3000 2800 2600 2400 0 07325-009 0.4 2200 The ADF4350 digital section includes a 10–bit RF R counter, a 16–bit RF N counter, a 12-bit FRAC counter, and a 12–bit modulus counter. Data is clocked into the 32–bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of six latches on the rising edge of LE. The destination latch is determined by the state of the three control bits (C3, C2, and C1) in the shift register. These are the 3 LSBs, DB2, DB1, and DB0, as shown in Figure 2. The truth table for these bits is shown in Table 5. Figure 23 shows a summary of how the latches are programmed. 1800 INPUT SHIFT REGISTERS VTUNE (V) Figure 19. MUXOUT Schematic 2000 DGND 07325-008 RESERVED Figure 20. VTUNE vs. Frequency The R counter output is used as the clock for the band select logic. A programmable divider is provided at the R counter output to allow division by 1 to 255 and is controlled by Bits [BS8:BS1] in Register 4 (R4). When the required PFD frequency is higher than 125 kHz, the divide ratio should be set to allow enough time for correct band selection. After band select, normal PLL action resumes. The nominal value of KV is 33 MHz/V when the N-divider is driven from the VCO output or this value divided by D. D is the output divider value if the N-divider is driven from the RF divider output (chosen by programming Bits [D12:D10] in Register 4 (R4). The ADF4350 contains linearization circuitry to minimize any variation of the product of ICP and KV to keep the loop bandwidth constant. A number of settings in the ADF4350 are double buffered. These include the modulus value, phase value, R counter value, reference doubler, reference divide-by-2, and current setting. This means that two events have to occur before the part uses a new value of any of the double buffered settings. First, the new value is latched into the device by writing to the appropriate register. Second, a new write must be performed on Register R0. For example, any time the modulus value is updated, Register 0 Rev. 0 | Page 12 of 28 ADF4350 The VCO shows variation of KV as the VTUNE varies within the band and from band-to-band. It has been shown for wideband applications covering a wide frequency range (and changing output dividers) that a value of 33 MHz/V provides the most accurate KV as this is closest to an average value. Figure 21 shows how KV varies with fundamental VCO frequency along with an average value for the frequency band. Users may prefer this figure when using narrowband designs. 80 60 50 40 An auxiliary output stage exists on Pins RFOUTB+ and RFOUTB− providing a second set of differential outputs which can be used to drive another circuit, or which can be powered down if unused. 30 20 07325-133 10 The RFOUTA+ and RFOUTA− pins of the ADF4350 are connected to the collectors of an NPN differential pair driven by buffered outputs of the VCO, as shown in Figure 22. To allow the user to optimize the power dissipation vs. the output power requirements, the tail current of the differential pair is programmable by Bits [D2:D1] in Register 4 (R4). Four current levels may be set. These levels give output power levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm, respectively, using a 50 Ω resistor to AVDD and ac coupling into a 50 Ω load. Alternatively, both outputs can be combined in a 1 + 1:1 transformer or a 180° microstrip coupler (see the Output Matching section). If the outputs are used individually, the optimum output stage consists of a shunt inductor to VVCO. The unused complementary output must be terminated with a similar circuit to the used output. Another feature of the ADF4350 is that the supply current to the RF output stage can be shut down until the part achieves lock as measured by the digital lock detect circuitry. This is enabled by the mute till lock detect (MTLD) bit in Register 4 (R4). 0 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 FREQUENCY (GHz) Figure 21. KV vs. Frequency In fixed frequency applications, the ADF4350 VTUNE may vary with ambient temperature switching from hot to cold. In extreme cases, the drift causes VTUNE to drop to a very low level (<0.25 V) and can cause loss of lock. This becomes an issue only at fundamental VCO frequencies less than 2.95 GHz and at ambient temperatures below 0°C. In cases such as these, if the ambient temperature decreases below 0°C, the frequency needs to be reprogrammed (R0 updated) to avoid VTUNE dropping to a level close to 0 V. Reprogramming the part chooses a more suitable VCO band, and thus avoids the low VTUNE issue. Any further temperature drops of more than 20°C (below 0°C) also require further reprogramming. Any increases in the ambient temperature do not require reprogramming. Rev. 0 | Page 13 of 28 RFOUTA+ VCO RFOUTA– BUFFER/ DIVIDE-BY1/2/4/8/16 07325-010 VCO SENSITIVITY (MHz/V) 70 OUTPUT STAGE Figure 22. Output Stage ADF4350 REGISTER MAPS RESERVED REGISTER 0 16-BIT INTEGER VALUE (INT) CONTROL BITS 12-BIT FRACTIONAL VALUE (FRAC) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 DB2 DB1 DB0 C3(0) C2(0) C1(0) PRESCALER REGISTER 1 RESERVED DBR1 12-BIT PHASE VALUE (PHASE) CONTROL BITS DBR 1 12-BIT MODULUS VALUE (MOD) PR1 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 M12 M11 M10 M9 M8 M7 M6 M5 M4 DB2 DB1 DB0 M3 M2 M1 C3(0) C2(0) C1(1) COUNTER RESET 0 CP THREESTATE 0 PD 0 LDP 0 PD POLARITY DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 CONTROL BITS DBR 1 CHARGE PUMP CURRENT SETTING LDF DBR 1 10-BIT R COUNTER DOUBLE BUFF MUXOUT RDIV2 LOW NOISE AND LOW SPUR MODES REFERENCE DOUBLER DBR 1 RESERVED REGISTER 2 DBR 1 DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 L2 L1 M3 M2 M1 RD2 RD1 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 D1 CP4 CP3 CP2 CP1 U6 U5 U4 U3 U2 U1 DB2 DB1 DB0 C3(0) C2(1) C1(0) RESERVED RESERVED RESERVED CSR REGISTER 3 CLK DIV MODE CONTROL BITS 12-BIT CLOCK DIVIDER VALUE 0 0 0 0 0 0 0 0 0 0 0 F1 0 C2 C1 D12 D11 D10 D9 D8 D7 D6 AUX OUTPUT ENABLE 0 MTLD 0 AUX OUTPUT SELECT DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 D5 D4 D3 D2 D1 DB2 DB1 DB0 C3(0) C2(1) C1(1) DBB 2 DIVIDER SELECT 8-BIT BAND SELECT CLOCK DIVIDER VALUE AUX OUTPUT POWER RF OUTPUT ENABLE RESERVED VCO POWER DOWN FEEDBACK SELECT REGISTER 4 OUTPUT POWER DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 0 0 0 0 0 0 0 D13 D12 D11 D10 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 D9 D8 D7 D6 D5 D4 D3 D2 D1 CONTROL BITS DB2 DB1 DB0 C3(1) C2(0) C1(0) CONTROL BITS RESERVED RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 1 DBR 2 DBB 0 0 0 0 0 0 0 D15 D14 0 1 1 0 0 0 0 0 0 0 0 0 0 = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0. = DOUBLE BUFFERED BITS—BUFFERED BY THE WRITE TO REGISTER 0, IF AND ONLY IF DB13 OF REGISTER 2 IS HIGH. Figure 23. Register Summary Rev. 0 | Page 14 of 28 0 0 0 0 0 0 DB2 DB1 DB0 C3(1) C2(0) C1(1) 07325-011 LD PIN MODE RESERVED RESERVED REGISTER 5 RESERVED ADF4350 16-BIT INTEGER VALUE (INT) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 DB7 DB6 F5 F4 DB5 DB4 F3 F2 DB3 F1 DB2 DB1 DB0 C3(0) C2(0) C1(0) N16 N15 ... N5 N4 N3 N2 N1 INTEGER VALUE (INT) F12 F11 .......... F2 F1 FRACTIONAL VALUE (FRAC) 0 0 ... 0 0 0 0 0 NOT ALLOWED 0 0 .......... 0 0 0 0 0 ... 0 0 0 0 1 NOT ALLOWED 0 0 .......... 0 1 1 0 0 ... 0 0 0 1 0 NOT ALLOWED 0 0 .......... 1 0 2 . . ... . . . . . ... 0 0 .......... 1 1 3 0 0 ... 1 0 1 1 0 NOT ALLOWED . . .......... . . . 0 0 ... 1 0 1 1 1 23 . . .......... . . . 0 0 ... 1 1 0 0 0 24 . . .......... . . . . . ... . . . . . ... 1 1 .......... 0 0 4092 1 1 ... 1 1 1 0 1 65533 1 1 .......... 0 1 4093 1 1 ... 1 1 1 1 0 65534 1 1 .......... 1 0 4094 1 1 ... 1 1 1 1 1 65535 1 1 ......... 1 1 4095 07325-012 0 CONTROL BITS 12-BIT FRACTIONAL VALUE (FRAC) INTmin = 75 with prescaler = 8/9 PRESCALER Figure 24. Register 0 (R0) RESERVED DBR 12-BIT PHASE VALUE (PHASE) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 0 0 0 PR1 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 M12 M11 M10 M9 M8 M7 M6 DB7 DB6 DB5 DB4 M5 M4 P1 PRESCALER P12 P11 .......... P2 P1 PHASE VALUE (PHASE) M12 M11 .......... M2 M1 0 4/5 0 0 .......... 0 0 0 0 0 .......... 1 0 2 1 8/9 0 0 .......... 0 1 1 (RECOMMENDED) 0 0 .......... 1 1 3 0 0 .......... 1 0 2 . . .......... . . . 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 4092 . . .......... . . . 1 1 .......... 0 1 4093 . . .......... . . . 1 1 .......... 1 0 4094 1 1 .......... 0 0 4092 1 1 .......... 1 1 4095 1 1 .......... 0 1 4093 1 1 .......... 1 0 4094 1 1 .......... 1 1 4095 M3 M2 DB3 M1 DB2 DB1 DB0 C3(0) C2(0) C1(1) INTERPOLATOR MODULUS (MOD) 07325-013 0 CONTROL BITS DBR 12-BIT MODULUS VALUE (MOD) Figure 25. Register 1 (R1) Rev. 0 | Page 15 of 28 COUNTER RESET CP THREESTATE POWER-DOWN PD POLARITY DBR LDF 10-BIT R COUNTER CHARGE PUMP CURRENT SETTING LDP DBR DOUBLE BUFF MUXOUT RDIV2 LOW NOISE AND LOW SPUR MODES REFERENCE DOUBLER DBR RESERVED ADF4350 DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 L2 L1 M3 M2 M1 RD2 RD1 R10 L1 L2 NOISE MODE RD2 REFERENCE DOUBLER 0 0 LOW NOISE MODE 0 DISABLED 0 1 RESERVED 1 ENABLED 1 0 RESERVED 1 1 LOW SPUR MODE R8 R7 REFERENCE DIVIDE BY 2 0 DISABLED .......... R2 R1 0 0 .......... 0 1 1 0 0 .......... 1 0 2 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 1020 1 1 .......... 0 1 1021 1 1 .......... 1 0 1022 1 1 .......... 1 1 1023 M1 OUTPUT 0 0 THREE-STATE OUTPUT 0 0 1 DVDD 0 1 0 DGND 0 1 1 R DIVIDER OUTPUT 1 0 0 N DIVIDER OUTPUT 1 0 1 ANALOG LOCK DETECT 1 1 0 DIGITAL LOCK DETECT 1 1 1 RESERVED R4 R3 R2 R DIVIDER (R) R1 D1 CP4 CP3 CP2 DOUBLEBUFFER R4 DB22-20 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.31 0.63 0.94 1.25 1.56 1.88 2.19 2.50 2.81 3.13 3.44 3.75 4.06 4.38 4.69 5.00 U1 C3(0) C2(1) C1(0) COUNTER RESET 0 DISABLED 1 ENABLED 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 U2 INT-N DISABLED ICP (mA) 5.1kΩ U3 U1 ENABLED CP1 U4 FRAC-N 1 CP2 U5 DB0 LDF 0 CP3 U6 DB1 U6 0 CP4 CP1 DB2 U5 LDP U2 CP THREE-STATE 0 10ns 0 DISABLED 1 6ns 1 ENABLED U4 PD POLARITY U3 POWER DOWN 0 NEGATIVE 0 DISABLED 1 POSITIVE 1 ENABLED 07325-014 M2 0 R5 ENABLED R9 M3 R6 D1 RD1 1 R10 R9 CONTROL BITS CLK DIV MODE DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 0 0 0 0 0 0 0 0 0 0 0 0 0 F1 0 C2 C1 CONTROL BITS 12-BIT CLOCK DIVIDER VALUE D12 D11 D10 D9 D8 D7 D6 DB7 DB6 DB5 DB4 D5 D4 D3 D2 DB3 D1 F1 CYCLE SLIP REDUCTION D12 D11 .......... D2 D1 CLOCK DIVIDER VALUE 0 0 .......... 0 0 0 0 DISABLED 0 0 .......... 0 1 1 1 ENABLED 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . C2 C1 CLOCK DIVIDER MODE 0 0 CLOCK DIVIDER OFF 1 1 .......... 0 0 4092 0 1 FAST-LOCK ENABLE 1 1 .......... 0 1 4093 1 0 RESYNC ENABLE 1 1 .......... 1 0 4094 1 1 RESERVED 1 1 .......... 1 1 4095 Figure 27. Register 3 (R3) Rev. 0 | Page 16 of 28 DB2 DB1 DB0 C3(0) C2(1) C1(1) 07325-015 CSR RESERVED RESERVED RESERVED Figure 26. Register 2 (R2) AUX OUTPUT POWER RF OUTPUT ENABLE AUX OUTPUT ENABLE 8-BIT BAND SELECT CLOCK DIVIDER VALUE AUX OUTPUT SELECT DIVIDER SELECT DBB MTLD RESERVED VCO POWERDOWN FEEDBACK SELECT ADF4350 CONTROL BITS OUTPUT POWER DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 0 0 0 0 0 0 0 D13 D12 D11 D10 BS8 BS7 BS6 BS5 BS4 FEEDBACK D13 SELECT 0 D12 D11 D10 0 0 0 BS2 0 1 ÷2 1 0 ÷4 0 1 1 ÷8 1 0 0 ÷16 D8 D6 D5 D4 D3 D2 D1 DB2 DB1 DB0 C3(1) C2(0) C1(0) D2 D1 OUTPUT POWER 0 0 -4 1 VCO POWERED DOWN 0 1 -1 1 0 +2 1 1 +5 D8 MUTE TILL LOCK DETECT 0 MUTE DISABLED D3 1 MUTE ENABLED 0 DISABLED 1 ENABLED AUX OUTPUT SELECT 0 DIVIDED OUTPUT 1 FUNDAMENTAL RF OUT D5 D4 AUX OUTPUT POWER 0 0 -4 0 1 -1 AUX OUT 1 0 +2 0 DISABLED 1 1 +5 1 ENABLED .......... BS2 BS1 0 0 .......... 0 1 1 0 0 .......... 1 0 2 D6 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 252 1 1 .......... 0 1 253 1 1 .......... 1 0 254 1 1 .......... 1 1 255 07325-016 BAND SELECT CLOCK DIVIDER (R) D7 BS7 BS8 D7 VCO POWERED UP ÷1 0 D9 0 RF DIVIDER SELECT 0 BS1 VCO POWER-DOWN D9 DIVIDED FUNDAMENTAL 1 BS3 LD PIN MODE RESERVED RESERVED Figure 28. Register 4 (R4) RESERVED CONTROL BITS RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 0 0 0 0 0 0 0 D15 D14 0 0 D1 5 D1 4 LOCK DETECT PIN OPERATION 0 0 LOW 0 1 DIGITAL LOCK DETECT 1 0 LOW 1 1 HIGH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB2 DB1 DB0 C3(1) C2(0) C1(1) 07325-017 0 DB3 Figure 29. Register 5 (R5) Rev. 0 | Page 17 of 28 ADF4350 If neither the phase resync nor the spurious optimization functions are being used, it is recommended the PHASE word be set to 1. REGISTER 0 Control Bits With Bits [C3:C1] set to 0, 0, 0, Register 0 is programmed. Figure 24 shows the input data format for programming this register. 12-Bit Interpolator MOD Value 16-Bit INT Value These sixteen bits set the INT value, which determines the integer part of the feedback division factor. It is used in Equation 1 (see the INT, FRAC, MOD, and R Counter Relationship section). All integer values from 23 to 65,535 are allowed for 4/5 prescaler. For 8/9 prescaler, the minimum integer value is 75. 12-Bit FRAC Value The 12 FRAC bits set the numerator of the fraction that is input to the Σ-Δ modulator. This, along with INT, specifies the new frequency channel that the synthesizer locks to, as shown in the RF Synthesizer—A Worked Example section. FRAC values from 0 to MOD − 1 cover channels over a frequency range equal to the PFD reference frequency. REGISTER 1 Control Bits With Bits [C3:C1] set to 0, 0, 1, Register 1 is programmed. Figure 25 shows the input data format for programming this register. Prescaler Value The dual modulus prescaler (P/P + 1), along with the INT, FRAC, and MOD counters, determines the overall division ratio from the VCO output to the PFD input. This programmable register sets the fractional modulus. This is the ratio of the PFD frequency to the channel step resolution on the RF output. See the RF Synthesizer—A Worked Example section for more information. REGISTER 2 Control Bits With Bits [C3:C1] set to 0, 1, 0, Register 2 is programmed. Figure 26 shows the input data format for programming this register. Low Noise and Low Spur Modes The noise modes on the ADF4350 are controlled by DB30 and DB29 in Register 2 (see Figure 26). The noise modes allow the user to optimize a design either for improved spurious performance or for improved phase noise performance. When the lowest spur setting is chosen, dither is enabled. This randomizes the fractional quantization noise so it resembles white noise rather than spurious noise. As a result, the part is optimized for improved spurious performance. This operation would normally be used when the PLL closed-loop bandwidth is wide, for fast-locking applications. Wide loop bandwidth is seen as a loop bandwidth greater than 1/10 of the RFOUT channel step resolution (fRES). A wide loop filter does not attenuate the spurs to the same level as a narrow loop bandwidth. Operating at CML levels, the prescaler takes the clock from the VCO output and divides it down for the counters. It is based on a synchronous 4/5 core. When set to 4/5, the maximum RF frequency allowed is 3 GHz. Therefore, when operating the ADF4350 above 3 GHz, this must be set to 8/9. The prescaler limits the INT value, where P is 4/5, NMIN is 23 and P is 8/9, NMIN is 75. For best noise performance, use the lowest noise setting option. As well as disabling the dither, this setting also ensures that the charge pump is operating in an optimum region for noise performance. This setting is extremely useful where a narrow loop filter bandwidth is available. The synthesizer ensures extremely low noise and the filter attenuates the spurs. The typical performance characteristics give the user an idea of the trade-off in a typical W-CDMA setup for the different noise and spur settings. In the ADF4350, PR1 in Register 1 sets the prescaler values. MUXOUT 12-Bit Phase Value The on-chip multiplexer is controlled by Bits [DB28:DB26] (see Figure 26). These bits control what is loaded as the phase word. The word must be less than the MOD value programmed in Register 1. The word is used to program the RF output phase from 0° to 360° with a resolution of 360°/MOD. See the Phase Resync section for more information. In most applications, the phase relationship between the RF signal and the reference is not important. In such applications, the phase value can be used to optimize the fractional and subfractional spur levels. See the Spur Consistency and Fractional Spur Optimization section for more information. Reference Doubler Setting DB25 to 0 feeds the REFIN signal directly to the 10–bit R counter, disabling the doubler. Setting this bit to 1 multiplies the REFIN frequency by a factor of 2 before feeding into the 10-bit R counter. When the doubler is disabled, the REFIN falling edge is the active edge at the PFD input to the fractional synthesizer. When the doubler is enabled, both the rising and falling edges of REFIN become active edges at the PFD input. Rev. 0 | Page 18 of 28 ADF4350 When the doubler is enabled and the lowest spur mode is chosen, the in-band phase noise performance is sensitive to the REFIN duty cycle. The phase noise degradation can be as much as 5 dB for the REFIN duty cycles outside a 45% to 55% range. The phase noise is insensitive to the REFIN duty cycle in the lowest noise mode and when the doubler is disabled. The maximum allowable REFIN frequency when the doubler is enabled is 30 MHz. RDIV2 Lock Detect Precision (LDP) When DB7 is set to 0, 40 consecutive PFD cycles of 10 ns must occur before digital lock detect is set. When this bit is programmed to 1, 40 consecutive reference cycles of 6 ns must occur before digital lock detect is set. This refers to fractional-N digital lock detect (set DB8 to 0). With integer–N digital lock detect activated (set DB8 to 1), and DB7 set to 0, then five consecutive cycles of 6 ns need to occur before digital lock detect is set. When DB7 is set to 1, five consecutive cycles of 10 ns must occur. Setting the DB24 bit to 1 inserts a divide-by-2 toggle flip-flop between the R counter and PFD, which extends the maximum REFIN input rate. This function allows a 50% duty cycle signal to appear at the PFD input, which is necessary for cycle slip reduction. Phase Detector Polarity 10–Bit R Counter Power-Down The 10–bit R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the PFD. Division ratios from 1 to 1023 are allowed. DB5 provides the programmable power-down mode. Setting this bit to 1 performs a power-down. Setting this bit to 0 returns the synthesizer to normal operation. When in software power-down mode, the part retains all information in its registers. Only if the supply voltages are removed are the register contents lost. Double Buffer DB13 enables or disables double buffering of Bits [DB22:DB20] in Register 4. The Divider Select section explains how double buffering works. DB6 sets the phase detector polarity. When a passive loop filter, or noninverting active loop filter is used, this should be set to 1. If an active filter with an inverting characteristic is used, it should be set to 0. When a power-down is activated, the following events occur: • Charge Pump Current Setting Bits [DB12:DB09] set the charge pump current setting. This should be set to the charge pump current that the loop filter is designed with (see Figure 26). LDF Setting DB8 to 1 enables integer–N digital lock detect, when the FRAC part of the divider is 0; setting DB8 to 0 enables fractional–N digital lock detect. • • • • • The synthesizer counters are forced to their load state conditions. The VCO is powered down. The charge pump is forced into three-state mode. The digital lock detect circuitry is reset. The RFOUT buffers are disabled. The input register remains active and capable of loading and latching data. Charge Pump Three-State DB4 puts the charge pump into three-state mode when programmed to 1. It should be set to 0 for normal operation. Counter Reset DB3 is the R counter and N counter reset bit for the ADF4350. When this is 1, the RF synthesizer N counter and R counter are held in reset. For normal operation, this bit should be set to 0. Rev. 0 | Page 19 of 28 ADF4350 REGISTER 3 Band Select Clock Divider Value Control Bits Bits [DB19:DB12] set a divider for the band select logic clock input. The output of the R counter, is by default, the value used to clock the band select logic, but, if this value is too high (>125 kHz), a divider can be switched on to divide the R counter output to a smaller value (see Figure 28). With Bits [C3:C1] set to 0, 1, 1, Register 3 is programmed. Figure 27 shows the input data format for programming this register. CSR Enable Setting DB18 to 1 enables cycle slip reduction. This is a method for improving lock times. Note that the signal at the phase frequency detector (PFD) must have a 50% duty cycle for cycle slip reduction to work. The charge pump current setting must also be set to a minimum. See the Cycle Slip Reduction for Faster Lock Times section for more information. VCO Power-Down DB11 powers the VCO down or up depending on the chosen value. Mute Till Lock Detect If DB10 is set to 1, the supply current to the RF output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. Clock Divider Mode AUX Output Select Bits [DB16:DB15] must be set to 1, 0 to activate PHASE resync or 0, 1 to activate fast lock. Setting Bits [DB16:DB15] to 0, 0 disables the clock divider. See Figure 27. DB9 sets the auxiliary RF output. The selection can be either the output of the RF dividers or fundamental VCO frequency. 12-Bit Clock Divider Value The 12-bit clock divider value sets the timeout counter for activation of PHASE resync. See the Phase Resync section for more information. It also sets the timeout counter for fast lock. See the Fast-Lock Timer and Register Sequences section for more information. AUX Output Enable DB8 enables or disables auxiliary RF output, depending on the chosen value. AUX Output Power Bits [DB7:DB6] set the value of the auxiliary RF output power level (see Figure 28). REGISTER 4 RF Output Enable Control Bits DB5 enables or disables primary RF output, depending on the chosen value. With Bits [C3:C1] set to 1, 0, 0, Register 4 is programmed. Figure 28 shows the input data format for programming this register. Output Power Bits [DB4:DB3] set the value of the primary RF output power level (see Figure 28). Feedback Select DB23 selects the feedback from the VCO output to the N counter. When set to 1, the signal is taken from the VCO directly. When set to 0, it is taken from the output of the output dividers. The dividers enable covering of the wide frequency band (137.5 MHz to 4.4 GHz). When the divider is enabled and the feedback signal is taken from the output, the RF output signals of two separately configured PLLs are in phase. This is useful in some applications where the positive interference of signals is required to increase the power. REGISTER 5 Control Bits With Bits [C3:C1] set to 1, 0, 1, Register 5 is programmed. Figure 29 shows the input data form for programming this register. Lock Detect Pin Operation Bits [DB23:DB22] set the operation of the lock detect pin (see Figure 29). Divider Select Bits [DB22:DB20] select the value of the output divider (see Figure 28). Rev. 0 | Page 20 of 28 ADF4350 INITIALIZATION SEQUENCE The following sequence of registers is the correct sequence for initial power-up of the ADF4350 after the correct application of voltages to the supply pins: • • • • • • Register 5 Register 4 Register 3 Register 2 Register 1 Register 0 Channel resolution (fRESOUT) or 200 kHz is required at the output of the RF divider. Therefore, channel resolution at the output of the VCO (fRES) is to be twice the fRESOUT, that is 400 kHz. MOD = REFIN/fRES MOD = 10 MHz/400 kHz = 25 From Equation 4, The following is an example how to program the ADF4350 synthesizer: (3) where: RFOUT is the RF frequency output. INT is the integer division factor. FRAC is the fractionality. MOD is the modulus. RF divider is the output divider that divides down the VCO frequency. (4) where: REFIN is the reference frequency input. D is the RF REFIN doubler bit. T is the reference divide-by-2 bit (0 or 1). R is the RF reference division factor. For example, in a UMTS system, where 2112.6 MHz RF frequency output (RFOUT) is required, a 10 MHz reference frequency input (REFIN) is available, and a 200 kHz channel resolution (fRESOUT) is required on the RF output. Note that the ADF4350 operates in the frequency range of 2.2 GHz to 4.4 GHz. Therefore, the RF divider of 2 should be used (VCO frequency = 4225.2 MHz, RFOUT = VCO frequency/RF divider = 4225.2 MHz/2 = 2112.6 MHz). It is also important where the loop is closed. In this example, the loop is closed (see Figure 30). RFOUT N DIVIDER Figure 30. Loop Closed Before Output Divider 07325-027 ÷2 (6) The choice of modulus (MOD) depends on the reference signal (REFIN) available and the channel resolution (fRES) required at the RF output. For example, a GSM system with 13 MHz REFIN sets the modulus to 65. This means the RF output resolution (fRES) is the 200 kHz (13 MHz/65) necessary for GSM. With dither off, the fractional spur interval depends on the modulus values chosen (see Table 6). REFERENCE DOUBLER AND REFERENCE DIVIDER fPFD = REFIN × [(1 + D)/(R × (1+T))] VCO 2112.6 MHz = 10 MHz × (INT + FRAC/25)/2 MODULUS RFOUT = [INT + (FRAC/MOD)] × [fPFD]/RF divider PFD (5) where: INT = 422 FRAC = 13 RF SYNTHESIZER—A WORKED EXAMPLE fPFD fPFD = [10 MHz × (1 + 0)/1] = 10 MHz The reference doubler on-chip allows the input reference signal to be doubled. This is useful for increasing the PFD comparison frequency. Making the PFD frequency higher improves the noise performance of the system. Doubling the PFD frequency usually improves noise performance by 3 dB. It is important to note that the PFD cannot operate above 32 MHz due to a limitation in the speed of the Σ-Δ circuit of the N-divider. The reference divide-by-2 divides the reference signal by 2, resulting in a 50% duty cycle PFD frequency. This is necessary for the correct operation of the cycle slip reduction (CSR) function. See the Cycle Slip Reduction for Faster Lock Times section for more information. 12-BIT PROGRAMMABLE MODULUS Unlike most other fractional-N PLLs, the ADF4350 allows the user to program the modulus over a 12–bit range. This means the user can set up the part in many different configurations for the application, when combined with the reference doubler and the 10-bit R counter. For example, consider an application that requires 1.75 GHz RF and 200 kHz channel step resolution. The system has a 13 MHz reference signal. One possible setup is feeding the 13 MHz directly to the PFD and programming the modulus to divide by 65. This results in the required 200 kHz resolution. Another possible setup is using the reference doubler to create 26 MHz from the 13 MHz input signal. This 26 MHz is then fed into the PFD programming the modulus to divide by 130. This also results in 200 kHz resolution and offers superior phase noise performance over the previous setup. Rev. 0 | Page 21 of 28 ADF4350 The programmable modulus is also very useful for multistandard applications. If a dual-mode phone requires PDC and GSM 1800 standards, the programmable modulus is a great benefit. PDC requires 25 kHz channel step resolution, whereas GSM 1800 requires 200 kHz channel step resolution. A 13 MHz reference signal can be fed directly to the PFD, and the modulus can be programmed to 520 when in PDC mode (13 MHz/520 = 25 kHz). The modulus needs to be reprogrammed to 65 for GSM 1800 operation (13 MHz/65 = 200 kHz). Up to seven extra charge pump cells can be turned on. In most applications, it is enough to eliminate cycle slips altogether, giving much faster lock times. Setting Bit DB18 in the Register 3 to 1 enables cycle slip reduction. Note that the PFD requires a 45% to 55% duty cycle for CSR to operate correctly. If the REFIN frequency does not have a suitable duty cycle, the RDIV2 mode ensures that the input to the PFD has a 50% duty cycle. SPURIOUS OPTIMIZATION AND FAST LOCK It is important that the PFD frequency remain constant (13 MHz). This allows the user to design one loop filter for both setups without running into stability issues. It is important to remember that the ratio of the RF frequency to the PFD frequency principally affects the loop filter design, not the actual channel spacing. Narrow loop bandwidths can filter unwanted spurious signals, but these usually have a long lock time. A wider loop bandwidth will achieve faster lock times, but a wider loop bandwidth may lead to increased spurious signals inside the loop bandwidth. The fast lock feature can achieve the same fast lock time as the wider bandwidth, but with the advantage of a narrow final loop bandwidth to keep spurs low. CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES FAST-LOCK TIMER AND REGISTER SEQUENCES As outlined in the Low Noise and Low Spur Mode section, the ADF4350 contains a number of features that allow optimization for noise performance. However, in fast locking applications, the loop bandwidth generally needs to be wide, and therefore, the filter does not provide much attenuation of the spurs. If the cycle slip reduction feature is enabled, the narrow loop bandwidth is maintained for spur attenuation but faster lock times are still possible. If the fast-lock mode is used, a timer value is to be loaded into the PLL to determine the duration of the wide bandwidth mode. Cycle Slips Cycle slips occur in integer-N/fractional-N synthesizers when the loop bandwidth is narrow compared to the PFD frequency. The phase error at the PFD inputs accumulates too fast for the PLL to correct, and the charge pump temporarily pumps in the wrong direction. This slows down the lock time dramatically. The ADF4350 contains a cycle slip reduction feature that extends the linear range of the PFD, allowing faster lock times without modifications to the loop filter circuitry. When the circuitry detects that a cycle slip is about to occur, it turns on an extra charge pump current cell. This outputs a constant current to the loop filter, or removes a constant current from the loop filter (depending on whether the VCO tuning voltage needs to increase or decrease to acquire the new frequency). The effect is that the linear range of the PFD is increased. Loop stability is maintained because the current is constant and is not a pulsed current. When Bits [DB16:DB15] in Register 3 are set to 0, 1 (fast-lock enable), the timer value is loaded by the 12–bit clock divider value. The following sequence must be programmed to use fast lock: 1. 2. Initialization sequence (see the Initialization Sequence section) occurs only once after powering up the part. Load Register 3 by setting Bits [DB16:DB15] to 0, 1 and the chosen fast-lock timer value [DB14:DB3]. Note that the duration the PLL remains in wide bandwidth is equal to the fast-lock timer/fPFD. FAST LOCK—AN EXAMPLE If a PLL has reference frequencies of 13 MHz and fPFD = 13 MHz and a required lock time of 50 μs, the PLL is set to wide bandwidth for 40 μs. This example assumes a modulus of 65 for channel spacing of 200 kHz. If the time period set for the wide bandwidth is 40 μs, then Fast-Lock Timer Value = Time in Wide Bandwidth × fPFD/MOD Fast-Lock Timer Value = 40 μs × 13 MHz/65 = 8 Therefore, a value of 8 must be loaded into the clock divider value in Register 3 in Step 1 of the sequence described in the Fast-Lock Timer and Register Sequences section. If the phase error increases again to a point where another cycle slip is likely, the ADF4350 turns on another charge pump cell. This continues until the ADF4350 detects the VCO frequency has gone past the desired frequency. The extra charge pump cells are turned off one by one until all the extra charge pump cells have been disabled and the frequency is settled with the original loop filter bandwidth. Rev. 0 | Page 22 of 28 ADF4350 FAST LOCK—LOOP FILTER TOPOLOGY To use fast-lock mode, the damping resistor in the loop filter is reduced to ¼ of its value while in wide bandwidth mode. To achieve the wider loop filter bandwidth, the charge pump current increases by a factor of 16 and to maintain loop stability the damping resistor must be reduced a factor of ¼. To enable fast lock, the SW pin is shorted to the GND pin by settings Bits [DB16:DB15] in Register 3 to 0, 1. The following two topologies are available: • The damping resistor (R1) is divided into two values (R1 and R1A) that have a ratio of 1:3 (see Figure 31). • An extra resistor (R1A) is connected directly from SW, as shown in Figure 32. The extra resistor is calculated such that the parallel combination of an extra resistor and the damping resistor (R1) is reduced to ¼ of the original value of R1 (see Figure 32). ADF4350 R2 CP C1 C2 VCO C3 R1 In low noise mode (dither disabled) the quantization noise from the Σ-Δ modulator appears as fractional spurs. The interval between spurs is fPFD/L, where L is the repeat length of the code sequence in the digital Σ-Δ modulator. For the third-order modulator used in the ADF4350, the repeat length depends on the value of MOD, as listed in Table 6. Table 6. Fractional Spurs with Dither Disabled Condition (Dither Disabled) If MOD is divisible by 2, but not 3 If MOD is divisible by 3, but not 2 If MOD is divisible by 6 Otherwise Repeat Length 2 × MOD 3 × MOD 6 × MOD MOD Spur Interval Channel step/2 Channel step/3 Channel step/6 Channel step In low spur mode (dither enabled), the repeat length is extended to 221 cycles, regardless of the value of MOD, which makes the quantization error spectrum look like broadband noise. This may degrade the in-band phase noise at the PLL output by as much as 10 dB. For lowest noise, dither disabled is a better choice, particularly when the final loop bandwidth is low enough to attenuate even the lowest frequency fractional spur. Integer Boundary Spurs SW Another mechanism for fractional spur creation is the interactions between the RF VCO frequency and the reference frequency. When these frequencies are not integer related (the point of a fractional-N synthesizer) spur sidebands appear on the VCO output spectrum at an offset frequency that corresponds to the beat note or difference frequency between an integer multiple of the reference and the VCO frequency. These spurs are attenuated by the loop filter and are more noticeable on channels close to integer multiples of the reference where the difference frequency can be inside the loop bandwidth, therefore, the name integer boundary spurs. 07325-018 R1A Figure 31. Fast-Lock Loop Filter Topology—Topology 1 ADF4350 R2 CP C1 C2 R1A R1 VCO C3 SW 07325-019 Reference Spurs Figure 32. Fast-Lock Loop Filter Topology—Topology 2 SPUR MECHANISMS This section describes the three different spur mechanisms that arise with a fractional-N synthesizer and how to minimize them in the ADF4350. Fractional Spurs The fractional interpolator in the ADF4350 is a third-order Σ-Δ modulator (SDM) with a modulus (MOD) that is programmable to any integer value from 2 to 4095. In low spur mode (dither enabled) the minimum allowable value of MOD is 50. The SDM is clocked at the PFD reference rate (fPFD) that allows PLL output frequencies to be synthesized at a channel step resolution of fPFD/MOD. Reference spurs are generally not a problem in fractional-N synthesizers because the reference offset is far outside the loop bandwidth. However, any reference feed-through mechanism that bypasses the loop may cause a problem. Feed through of low levels of on-chip reference switching noise, through the RFIN pin back to the VCO, can result in reference spur levels as high as –90 dBc. PCB layout needs to ensure adequate isolation between VCO traces and the input reference to avoid a possible feed through path on the board. Rev. 0 | Page 23 of 28 ADF4350 SPUR CONSISTENCY AND FRACTIONAL SPUR OPTIMIZATION With dither off, the fractional spur pattern due to the quantization noise of the SDM also depends on the particular phase word with which the modulator is seeded. The phase word can be varied to optimize the fractional and subfractional spur levels on any particular frequency. Thus, a look-up table of phase values corresponding to each frequency can be constructed for use when programming the ADF4350. When a new frequency is programmed, the second sync pulse after the LE rising edge is used to resynchronize the output phase to the reference. The tSYNC time is to be programmed to a value that is as least as long as the worst-case lock time. This guarantees the phase resync occurs after the last cycle slip in the PLL settling transient. In the example shown in Figure 33, the PFD reference is 25 MHz and MOD = 125 for a 200 kHz channel spacing. tSYNC is set to 400 μs by programming CLK_DIV_VALUE = 80. If a look-up table is not used, keep the phase word at a constant value to ensure consistent spur levels on any particular frequency. LE SYNC (INTERNAL) The output of a fractional-N PLL can settle to any one of the MOD phase offsets with respect to the input reference, where MOD is the fractional modulus. The phase resync feature in the ADF4350 produces a consistent output phase offset with respect to the input reference. This is necessary in applications where the output phase and frequency are important, such as digital beam forming. See the Phase Programmability section to program a specific RF output phase when using phase resync. FREQUENCY PLL SETTLES TO INCORRECT PHASE PLL SETTLES TO CORRECT PHASE AFTER RESYNC PHASE –100 Phase resync is enabled by setting Bits [DB16:DB15] in Register 3 to 1, 0. When phase resync is enabled, an internal timer generates sync signals at intervals of tSYNC given by the following formula: LAST CYCLE SLIP 07325-020 PHASE RESYNC tSYNC 0 100 200 300 400 500 600 TIME (µs) 700 800 900 1000 Figure 33. Phase Resync Example Phase Programmability tSYNC = CLK_DIV_VALUE × MOD × tPFD where: tPFD is the PFD reference period. CLK_DIV_VALUE is the decimal value programmed in Bits [DB14:DB3] of Register 3 and can be any integer in the range of 1 to 4095. MOD is the modulus value programmed in Bits [DB14:DB3] of Register 1 (R1). The phase word in Register 1 controls the RF output phase. As this word is swept from 0 to MOD, the RF output phase sweeps over a 360° range in steps of 360°/MOD. Rev. 0 | Page 24 of 28 ADF4350 APPLICATIONS INFORMATION The LO ports of the ADL5375 can be driven differentially from the complementary RFOUTA and RFOUTB outputs of the ADF4350. This gives better performance than a single-ended LO driver and eliminates the use of a balun to convert from a single-ended LO input to the more desirable differential LO input for the ADL5375. The typical rms phase noise (100 Hz to 5 MHz) of the LO in this configuration is 0.61°rms. DIRECT CONVERSION MODULATOR Direct conversion architectures are increasingly being used to implement base station transmitters. Figure 34 shows how Analog Devices, Inc., parts can be used to implement such a system. The circuit block diagram shows the AD9761 TxDAC® being used with the ADL5375. The use of dual integrated DACs, such as the AD9788 with its specified ±0.02 dB and ±0.001 dB gain and offset matching characteristics, ensures minimum error contribution (over temperature) from this portion of the signal chain. The AD8349 accepts LO drive levels from −10 dBm to 0 dBm. The optimum LO power can be software programmed on the ADF4350, which allows levels from −4 dBm to +5 dBm from each output. The local oscillator (LO) is implemented using the ADF4350. The low-pass filter was designed using ADIsimPLL™ for a channel spacing of 200 kHz and a closed-loop bandwidth of 35 kHz. 51Ω REFIO 51Ω IOUTA MODULATED DIGITAL DATA LOW-PASS FILTER IOUTB AD9761 The RF output is designed to drive a 50 Ω load, but must be ac-coupled, as shown in Figure 34. If the I and Q inputs are driven in quadrature by 2 V p-p signals, the resulting output power from the modulator is approximately 2 dBm. TxDAC QOUTA LOW-PASS FILTER QOUTB FSADJ 51Ω 51Ω 2kΩ VVCO 17 VVCO 28 10 DVDD AVDD 30 26 25 4 6 32 CE PDB RF VP SDVDD MUXOUT LD 1nF 1nF FREF IN RFOUTB+ 14 VVCO IBBN RFOUTB– 15 1 CLK 2 DATA 3.9nH 3.9nH 3 LE SPI-COMPATIBLE SERIAL BUS ADL5375 IBBP 29 REF IN 51Ω 1nF ADF4350 RFOUTA+ 12 22 RSET QBBN RFOUTA– 13 4.7kΩ QBBP DSOP 680Ω LOIP CPOUT 7 39nF CPGND SDGND AGND AGNDVCO 8 31 9 11 18 21 DGND 27 10pF RFO 1nF VTUNE 20 SW 5 QUADRATURE PHASE SPLITTER 2700pF 1200pF LOIN 360Ω TEMP VCOM VREF 19 23 0.1µF 10pF 24 0.1µF 10pF 0.1µF Figure 34. Direct Conversion Modulator Rev. 0 | Page 25 of 28 07325-021 16 LOCK DETECT VDD ADF4350 INTERFACING ADSP-21xx Interface The ADF4350 has a simple SPI-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE goes high, the 32 bits that have been clocked into the appropriate register on each rising edge of CLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the register address table. Figure 36 shows the interface between the ADF4350 and the ADSP-21xx digital signal processor. The ADF4350 needs a 32-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Figure 35 shows the interface between the ADF4350 and the ADuC812 MicroConverter®. Because the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4350 needs a 32-bit word, which is accomplished by writing four 8-bit bytes from the MicroConverter to the device. When the fourth byte has been written, the LE input should be brought high to complete the transfer. MOSI ADuC812 I/O PORTS CLK SDATA LE ADF4350 MUXOUT (LOCK DETECT) CLK MOSI SDATA TFS ADSP-21xx I/O PORTS LE ADF4350 CE MUXOUT (LOCK DETECT) Figure 36. ADSP-21xx to ADF4350 Interface Set up the word length for 8 bits and use four memory locations for each 32-bit word. To program each 32-bit latch, store the 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. PCB DESIGN GUIDELINES FOR A CHIP SCALE PACKAGE CE 07325-022 SCLOCK SCLK 07325-023 ADuC812 Interface Figure 35. ADuC812 to ADF4350 Interface I/O port lines on the ADuC812 are also used to control powerdown input (CE) and lock detect (MUXOUT configured as lock detect and polled by the port input). When operating in the described mode, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 125 kHz. The lands on the chip scale package (CP-32-2) are rectangular. The PCB pad for these is to be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land is to be centered on the pad. This ensures the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the PCB is to be at least as large as the exposed pad. On the PCB, there is to be a minimum clearance of 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias can be used on the PCB thermal pad to improve the thermal performance of the package. If vias are used, they are to be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter is to be between 0.3 mm and 0.33 mm, and the via barrel is to be plated with 1 oz. of copper to plug the via. Rev. 0 | Page 26 of 28 ADF4350 VVCO OUTPUT MATCHING There are a number of ways to match the output of the ADF4350 for optimum operation; the most basic is to use a 50 Ω resistor to VVCO. A dc bypass capacitor of 100 pF is connected in series as shown in Figure 37. Because the resistor is not frequency dependent, this provides a good broadband match. Placing the output power in this circuit into a 50 Ω load typically gives values chosen by Bit D2 and Bit D1 in Register 4 (R4). 3.9nH 50Ω 07325-025 1nF RFOUT Figure 38.Optimum ADF4350 Output Stage VVCO If differential outputs are not needed, the unused output can be terminated or combined with both outputs using a balun. 50Ω VVCO L2 RFOUTA+ Figure 37. Simple ADF4350 Output Stage A better solution is to use a shunt inductor (acting as an RF choke) to VVCO. This gives a better match and, therefore, more output power. Experiments have shown the circuit shown in Figure 38 provides an excellent match to 50 Ω for the W-CDMA UMTS Band 1 (2110 MHz to 2170 MHz). The maximum output power in that case is about 5 dBm. Both single-ended architectures can be examined using the EVAL-ADF4350EB1Z evaluation board. L1 C1 C2 50Ω L1 RFOUTA– 07325-132 50Ω 07325-021 100pF RFOUT C1 Figure 39. ADF4350 LC Balun A balun using discrete inductors and capacitors may be implemented with the architecture in Figure 39. Component L1 and Component C1 comprise the LC balun, L2 provides a dc path for RFOUTA−, and Capacitor C2 is used for dc blocking. Table 7. LC Balun Components Frequency Range (MHz) 137 to 300 300 to 460 400 to 600 600 to 900 860 to 1240 1200 to 1600 1600 to 3600 2800 to 3800 Inductor L1 (nH) 100 51 30 18 12 5.6 3.3 2.2 Capacitor C1 (pF) 10 5.6 5.6 4 2.2 1.2 0.7 0.5 RF Choke Inductor (nH) 390 180 120 68 39 15 10 10 Rev. 0 | Page 27 of 28 DC Blocking Capacitor (pF) 1000 120 120 120 10 10 10 10 Measured Output Power (dBm) 9 10 10 10 9 9 8 8 ADF4350 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 3.25 3.10 SQ 2.95 EXPOSED PAD (BOTTOM VIEW) 17 16 0.80 MAX 0.65 TYP 9 8 0.25 MIN 3.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 1 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 011708-A 12° MAX 1.00 0.85 0.80 PIN 1 INDICATOR 32 25 24 Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model ADF4350BCPZ 1 ADF4350BCPZ-RL1 ADF4350BCPZ-RL71 EVAL-ADF4350EB1Z1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07325-0-11/08(0) Rev. 0 | Page 28 of 28 Package Option CP-32-2 CP-32-2 CP-32-2