19-1963; Rev 0; 2/01 ILABLE N KIT AVA EVALUATIO 16:1 Serializer, 3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs Features ♦ Single +3.3V Supply ♦ 495mW Power Consumption ♦ Exceeds ANSI, ITU, and Bellcore Specifications ♦ 155Mbps (16-bit wide) Parallel to 2.5Gbps Serial Conversion ♦ Clock Synthesis for 2.5Gbps ♦ Multiple Clock Reference Frequencies (155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz) ♦ Additional High-Speed Output for System Loopback Testing ♦ Single-Ended PECL Data Inputs ♦ Differential PECL Clock Inputs and Serial Data Outputs ________________________Applications 2.5Gbps SDH/SONET Transmission Systems Ordering Information 2.5Gbps Access Nodes PART Add/Drop Multiplexers MAX3891ECB Digital Cross-Connects TEMP. RANGE PIN-PACKAGE -40°C to +85°C 64 TQFP EP* *EP = Exposed Pad ATM Backplanes Pin Configuration GND VCC PDI1 VCC PDIO PCLKO+ PCLKO- VCC RCLK+ RCLK- VCC 63 62 61 60 59 58 FIL- GND 64 FIL+ VCC CLKSET TOP VIEW 57 56 55 54 53 52 51 50 49 GND 1 48 GND VCC 2 47 VCC SLBO- 3 46 PDI2 SLBO+ 4 45 VCC VCC 5 44 PDI3 SOS 6 43 VCC VCC 7 SCLKO- 8 SCLKO+ 42 PDI4 41 VCC MAX3891 9 40 PDI5 VCC 10 39 VCC SDO- 11 38 PDI6 SDO+ 12 37 VCC VCC 13 36 PDI7 VCC 14 35 VCC PCLKI+ 15 34 PDI8 PCLKI- 16 33 GND VCC VCC PDI9 VCC PDI10 VCC PDI11 VCC PDI12 VCC PDI13 VCC PDI14 VCC GND PDI15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TQFP Typical Application Circuit appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX3891 General Description The MAX3891 serializer converts 16-bit wide, 155Mbps parallel data to 2.5Gbps serial data in ATM and SDH/SONET applications. The MAX3891 is ideal for interfacing with high-speed digital circuitry. This device accepts single-ended LVPECL data inputs and delivers differential LVPECL data and clock outputs. An internal 2.5Gbps serial clock, synthesized by a fully integrated PLL that accepts multiple input reference clock rates, retimes the output data stream. The MAX3891 operates from a single +3.3V supply and accepts differential LVPECL reference clock rates of 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz. A CML loopback data output is provided to facilitate system diagnostic testing. The MAX3891 is available in the extended temperature range (-40°C to +85°C) in a 64-pin TQFP exposed pad (EP) package. MAX3891 16:1 Serializer, 3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect to GND) VCC ..................................................................-0.5V to +5.0V All Inputs, FIL+, FIL- .............................-0.5V to (VCC + 0.5V) Output Currents PECL Outputs (SDO±, SCLKO±, PCLKO±) ..................50mA CML Outputs (SLBO±)...................................................15mA Continuous Power Dissipation (TA = +85°C) 64-Pin TQFP-EP (derate 45.5mW/°C above +85°C) ........2.9W Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, PECL loads = 50Ω ±1% to (VCC - 2V), CML loads = 50Ω ±1% to VCC, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN Supply Current ICC PECL outputs unterminated, SOS = iow PECL OUTPUTS (SDO±, SCLKO±, PCLKO±) Output Voltage High Output Voltage Low TYP MAX UNITS 150 230 mA TA = 0°C to +85°C VCC - 1.025 VCC - 0.88 TA = -40°C VCC - 1.085 VCC - 0.88 TA = 0°C to +85°C VCC - 1.81 VCC - 1.62 TA = -40°C VCC - 1.83 VCC - 1.555 VCC - 1.16 VCC - 0.88 VCC - 1.48 +10 µA VOH VOL V V PECL INPUTS (PDI_, PCLKI±, RCLK±) Input High Voltage VIH Input Low Voltage VIL Input Current High PDI_, RCLKI± IIH VCC - 1.81 -10 Input Current Low PDI_, RCLKI± IIL -10 +10 µA Input Current High PCLKI± IIH -60 +60 µA IIL -60 +60 µA ±500 µA Input Current Low PCLKI± V V PROGRAMMING INPUT (CLKSET) CLKSET Input Current ICLKSET CLKSET = GND or VCC TTL INPUT (SOS) TTL Input High Voltage VIH TTL Input Low Voltage VIL TTL Input High Current 2.0 IIH TTL Input Low Current IIL CURRENT MODE LOGIC (CML) OUTPUTS (SLBO±) CML Differential Output Voltage Swing CML Single-Ended Output Impedance 2 VOD RO RL = 50 Ω to VCC V 0.8 V -10 +10 µA -10 +10 µA 100 400 mV 50 _______________________________________________________________________________________ Ω 16:1 Serializer, 3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs (VCC = +3.0V to +3.6V, PECL loads = 50Ω ±1% to (VCC - 2V), CML loads = 50Ω ±1% to VCC, TA = -40°C to +85°C. Typical values are at TA = +25°C and VCC = +3.3V, unless otherwise noted.) (Note 1) PARAMETER SYMBOL Serial Clock Rate CONDITIONS MIN Parallel Data Setup Time tSU (Notes 2, 3) 300 Parallel Data-Hold Time tH (Notes 2, 3) 700 PCLKO to PCLKI Skew tSKEW Output Jitter Generation (SCLKO±) TYP MAX UNITS 2.488 fSCLK Figure 1 GHz ps ps 0 +4.0 Jitter bandwidth = 12kHz to 20MHz 3 ns psRMS PECL Differential Output (SDO±, SCLKO±) Rise/Fall Time tR, tF Parallel Input Clock Rate fPCLKI Reference Clock Input (RCLK±) Rise/Fall Time tR, tF 20% to 80%, f = 155.52MHz 1.0 ns Parallel Clock Output (PCLKO±) Rise/Fall Time tR, tF 20% to 80% 1.0 ns 290 ps Serial-Clock Output (SCLKO±) to Serial-Data Output (SDO±) Delay tSCLK-SD 20% to 80% 120 ps 155.52 SCLKO rising edge to SDO edge 110 MHz Note 1: AC characteristics are guaranteed by design and characterization. Note 2: Setup and hold times are relative to the rising edge of PCLKI+, measured by applying a 155.52MHz differential parallel clock with rise/fall time = 1ns (20% to 80%). See Figure 1. Note 3: Setup and hold time measurements assume that the PCLKI and PDI signals are from the same source and have identical common-mode voltages, swings, and slew rates. Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. TEMPERATURE MAX3891 toc01 180 SUPPLY CURRENT (mA) SERIAL-DATA OUTPUT EYE DIAGRAM SERIAL-DATA OUTPUT JITTER MAX3891 toc03 MAX3891 toc02 200 fRCLK = 155.52MHz 160 140 120 PECL OUTPUTS UNTERMINATED 100 -50 -25 0 25 50 TEMPERATURE (°C) 75 100 100ps/div 5000ps/div TOTAL WIDEBAND RMS JITTER = 2.059ps, PEAK-TO-PEAK JITTER = 16.70ps _______________________________________________________________________________________ 3 MAX3891 AC ELECTRICAL CHARACTERISTICS 16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs MAX3891 Pin Description PIN NAME 1, 17, 33, 48, 49, 63 GND Ground 2, 5, 7, 10, 13, 14, 19, 21, 23, 25, 27, 29, 31, 32, 35, 37, 39, 41, 43, 45, 47, 51, 53, 56, 60, 64 VCC +3.3V Supply Voltage 3 SLBO- 4 SLBO+ 6 SOS System Loopback Negative Output. Enabled when SOS is high. System Loopback Positive Output. Enabled when SOS is high. System Loopback Output Select, TTL Input. System loopback disabled when low. 8 SCLKO- 9 SCLKO+ Positive PECL Serial Clock Output 11 SDO- Negative PECL Serial Data Output 12 SDO+ Negative PECL Serial Clock Output Positive PECL Serial Data Output 15 PCLKI+ Positive PECL Parallel Clock Input. Connect the incoming parallel-clock signal to the PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal. 16 PCLKI- Negative PECL Parallel Clock Input. Connect the incoming parallel-clock signal to the PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal. 18, 20, 22, 24, 26, 28, 30, 34, 36, 38, 40, 42, 44, 46, 50, 52 PDI15 to PDI0 Single-Ended PECL Parallel Data Inputs. Data is clocked on the PCLKI positive transition. PDI15 is transmitted first. 54 PCLKO+ Positive PECL Parallel Clock Output. Use positive transition of PCLKO to clock the overhead management circuit. 55 PCLKO- Negative PECL Parallel Clock Output. Use positive transition of PCLKO to clock the overhead management circuit. 57 RCLK+ Positive Reference Clock Input. Connect a PECL-compatible crystal reference clock to the RCLK inputs. 58 RCLK- Negative Reference Clock Input. Connect a PECL-compatible crystal reference clock to the RCLK inputs. 59 4 FUNCTION CLKSET Reference Clock Rate Programming Pin: CLKSET = VCC: Reference Clock Rate = 155.52MHz CLKSET = Open: Reference Clock Rate = 77.76MHz CLKSET = 20kΩ to GND: Reference Clock Rate = 51.84MHz CLKSET = GND: Reference Clock Rate = 38.88MHz 61 FIL- Filter Capacitor Input. Connect a 0.33µF capacitor between FIL+ and FIL- 62 FIL+ Filter Capacitor Input. Connect a 0.33µF capacitor between FIL+ and FIL- EP Exposed Pad Ground. This must be soldered to a circuit board for proper electrical and thermal performance (see exposed pad package information). _______________________________________________________________________________________ 16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs MAX3891 PCLKO tSKEW PCLKI tSU tH PARALLEL INPUT DATA (PDI_) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15* NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCKLO = (PCLK0+) - (PCLKO-). *PDI I5 = D15; PDI14 = D14, . . . PDI0 = D0. THIS FIGURE IS NOT INTENDED TO SHOW A SPECIFIC TIMING RELATIONSHIP BETWEEN PARALLEL INPUT DATA AND SERIAL OUTPUT DATA. Figure 1. Timing Diagram Detailed Description The MAX3891 converts 16-bit wide, 155Mbps data to 2.5Gbps serial data (Figure 2). The MAX3891 is composed of a 16-bit parallel input register, a 16-bit shift register, control and timing logic, PECL output buffers and a frequency-synthesizing PLL, consisting of a phase/frequency detector, loop filter/amplifier, voltagecontrolled oscillator, and prescaler. The PLL synthesizes an internal 2.5Gbps reference used to clock the output shift register. This clock is generated from the external 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz reference-clock signal (RCLK). The incoming parallel data is clocked into the MAX3891 on the rising transition of the parallel clock-input signal (PCLKI). Proper operation is ensured if the parallel-input register is latched within a window of time (t SKEW), defined with respect to the parallel clock-output signal (PCLKO). PCLKO is the synthesized 2.488Gbps internal serial-clock signal divided by 16. The allowable PCLKO to PCLKI skew is 0ns to 4ns. This defines a timing window after the PCLKO rising edge, during which a PCLKI rising edge may occur (Figure 1). System Loopback The MAX3891 is designed to provide system loopback testing. The loopback outputs (SLBO) of the MAX3891 may be directly connected to the loopback inputs of a deserializer (MAX3881) for system diagnostics. To enable the SLBO outputs, apply a TTL logic-high signal to the SOS input. The same signal that controls the SOS enable input may also be used to control the SIS enable input on the MAX3881. _______________________________________________________________________________________ 5 MAX3891 16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs MAX3891 PDI15 PECL 16-BIT PARALLEL INPUT REGISTER PDI1 PECL PDI0 PECL BUF SOS SLBO+ CML PCLKI+ SLBO- PECL PCLKI- PRESCALER RCLK+ PECL RCLK- PHASE/FREQ DETECT FILTER VCO DIVIDE BY 16 SHIFT 16-BIT PARALLEL SHIFT REGISTER LATCH SDO+ PECL SDO- SCLKO+ PECL FIL+ FIL- CLKSET PECL SCLKO- PCLKO+ PCLKO- Figure 2. Functional Block Diagram Applications Information Setup and Hold Time Requirements The setup and hold-time specifications assume that the parallel clock-input signal (PCLKI) and parallel-data input signal (PDI_) are from the same source. They should have identical common-mode voltages, signal amplitudes, and slew rates. If PCLKI and PDI_ differ significantly, the setup and hold-time requirements must be modified to account for these differences. Define tDEG as the adjustment to the setup and holdtime requirement when there are significant differences between PCLKI and PDI_. 6 tDEG = VCMDIFF × tT 0.6 V -V OH OL where tT is the transition time (20%–80%) of the parallel-data and clock-input signals, VOH and VOL are the input high and low voltage, respectively, of the paralleldata and clock-input signals, and VCMDIFF is the difference in common-mode voltages of the parallel-data and clock-input signals. _______________________________________________________________________________________ 16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs PECL Input and Output Terminations It is important to bias the MAX3891’s PECL data and clock IOs appropriately. Figures 3 and 4 show alternative PECL output termination methods. A circuit that provides 50Ω to (VCC - 2V) should be used in conjunction with controlled impedance transmission lines for proper termination. Use Thevenin equivalent termination when a (VCC - 2V) supply is not available. If ACcoupling is necessary, make sure that the coupling capacitor follows the 50Ω or Thevenin equivalent DC termination. To ensure best performance, the differential outputs (SDO± and PCLKO±) must have balanced loads. Current-Mode Logic Outputs Layout Techniques For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Use controlled impedance transmission lines to interface with the MAX3891 clock and data inputs and outputs. Exposed Pad Package The 64-pin exposed pad (EP) TQFP incorporates features that provide a very low thermal-resistance path for heat removal. The MAX3891 EP must be soldered directly to a ground plane with good thermal conductance. Chip Information TRANSISTOR COUNT: 1712 PROCESS: Bipolar The system loopback outputs (SLBO) of the MAX3891 are CML compatible. The configuration of the MAX3891 current-mode logic (CML) output circuit includes internal 50Ω back termination to V CC (Figure 5). These outputs are intended to drive a terminated 50Ω transmission line. _______________________________________________________________________________________ 7 MAX3891 The adjusted setup (t SUADJ ) and hold-time (t HADJ ) requirements become tSUADJ (or tHADJ) = tSU (or tH) + tDEG MAX3891 16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs MAX3891 OVERHEAD GENERATION Z0 = 50Ω Z0 = 50Ω PECL INPUTS 50Ω PECL TERMINATIONS 50Ω (VCC - 2V) a. PECL TERMINATIONS V = +3.3V 130Ω 130Ω MAX3891 OVERHEAD GENERATION Z0 = 50Ω Z0 = 50Ω PECL INPUTS 82Ω 82Ω DC-COUPLING TO PECL OUTPUTS b. DC-COUPLING TO NON-PECL OUTPUTS +3.3V 82Ω OVERHEAD GENERATION Z0 = 50Ω Z0 = 50Ω 82Ω MAX3891 0.1µF 0.1µF PECL INPUTS 130Ω 130Ω AC-COUPLING TO NON-PECL OUTPUTS c. AC-COUPLING TO NON-PECL OUTPUTS Figure 3. Alternative PECL-Input Termination 8_______________________________________________________________________________________________________ _______________________________________________________________________________________ 8 16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs MAX3891 MAX3891 SCLKO+ OR SDO+ Z0 = 50Ω SCLKOOR SDO- Z0 = 50Ω 0.1µF HIGH IMPEDANCE INPUTS 0.1µF 50Ω 50Ω a. PECL OUTPUT TERMINATION +3.3V 130Ω 130Ω MAX3891 SCLKO+ OR SDO+ Z0 = 50Ω SCLKOOR SDO- Z0 = 50Ω PECL INPUTS 82Ω 82Ω b. THEVENIN-EQUIVALENT DC TERMINATION Figure 4. Alternative PECL-Output Termination VCC VCC MAX3891 50Ω 50Ω 50Ω 50Ω SLB0+ SLB1+ SLB0ESD SRUCTURE SLB1- MAX3881 GND OUTPUT CIRCUIT INPUT CIRCUIT Figure 5. Current-Mode Logic _______________________________________________________________________________________ 9 16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs MAX3891 Typical Application Circuit TERM 155MHz REFERENCE CLOCK INPUT +3.3V TTL RCLK+ RCLK- CLKSET VCC SOS TERM TERM +3.3V PDI0 MAX3891 SDO+ TERM SDO- TERM TERM PDI15 TERM PCLKI+ TERM PCLKI- SCLKO+ TERM TERM PCLKI SCLKO- TERM TERM PCLKI OVERHEAD GENERATION FIL+ MAX3869 FIL- SLBO+ SLBOTERM 0.33µF TERM OPTIONAL CONNECTION TO MAX3881 FOR SYSTEM LOOPBACK TESTING THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω TERM 10 THIS SYMBOL REPRESENTS A PECL TERMINATION WITH A THEVENIN EQUIVALENT OF 50Ω TO (VCC - 2V) NOTE: REFER TO APPLICATIONS INFORMATION SECTION FOR MORE ON PECL INPUT AND OUTPUT TERMINATIONS ______________________________________________________________________________________ 16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs 64L, TQFP.EPS ______________________________________________________________________________________ 11 MAX3891 Package Information 16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs MAX3891 Package Information (continued) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.