19-1534; Rev 1; 10/99 +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator Features ♦ +3.3V Single Supply ♦ 1.45W Power Dissipation (MAX3831) ♦ 4-Channel Mux/Demux with Fully Integrated 2.488GHz Clock Generator ♦ Frame Detection Maintains Channel Assignment ♦ ±7.5ns Elastic Store Range ♦ 2.5ps RMS Serial-Data Output Random Jitter ♦ 8ps Serial-Data Output Deterministic Jitter ♦ 622Mbps LVDS Parallel Input/Output ♦ 2.488Gbps Serial CML Input/Output ♦ On-Chip Pattern Generator Provides High-Speed BIST ♦ System Test Flexibility: System Loopback, Line Loopback ♦ Loss-of-Frame Indicator The MAX3831/MAX3832 are 4:1 multiplexers (muxes) and 1:4 demultiplexers (demuxes) with automatic channel assignment. Operating from a single +3.3V supply, the mux receives four parallel, 622Mbps SDH/SONET channels. These channels are bit interleaved to generate a serial data stream of 2.488Gbps for interfacing to an optical or an electrical driver. A 10-bit-wide elastic buffer tolerates up to ±7.5ns skew between any parallel data input and the reference clock. An external 155MHz reference clock is required for the on-chip PLL to synthesize a high-frequency 2.488GHz clock for timing the outgoing data streams. The MAX3831/MAX3832’s demux receives 2.488Gbps serial data and the 2.488GHz clock from an external clock/data recovery device (MAX3876), converting it to four 622Mbps LVDS outputs. The MAX3831 provides a 622MHz LVDS clock output, and the MAX3832 provides a 155MHz LVDS clock output. An internal frame detector looks for a 622Mbps SDH/SONET framing pattern and rolls the demux to maintain proper channel assignment at the outputs. These devices also include an embedded pattern generator that enables a full-speed, built-in self-test (BIST). Two different loopback modes provide system test flexibility. A TTL loss-of-frame monitor is included. The MAX3831/MAX3832 are available in 64-pin TQFP-EP (exposed paddle) packages and are specified over the upper commercial (0°C to +85°C) temperature range. Applications SDH/SONET Backplanes High-Speed Parallel Links ATM Switching Networks Line Extenders Intrarack/Subrack Interconnects Dense Digital CrossConnects Ordering Information Pin Configuration appears at end of data sheet. PART TEMP. RANGE MAX3831UCB MAX3832UCB 0°C to +85°C 0°C to +85°C PIN-PACKAGE 64 TQFP-EP 64 TQFP-EP Typical Application Circuit TTL 0.33µF +3.3V TTL TTL TTL TEST LOF PLBEN 0.1µF RSETES 155MHz REF CLOCK INPUT LVDS 4 4 LVDS CMOS OVERHEAD FIL- LVDS 4 VCC RCLKI+ SCLKI- RCLKIPDI1+ TO PDI4+ SCLKI+ CML SDI- PDI1- TO PDI44 LVDS FIL+ MAX3831 MAX3832 PDO1+ TO PDO4+ SDI+ CML SDO- PCLKO+ LBEN TTL RSETFR TTL TRIEN GND 2.5Gbps OPTICAL TRANSCEIVER SDO+ PDO1- TO PDO4- PCLKO- MAX3876 2.5Gbps CDR TTL ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX3831/MAX3832 General Description MAX3831/MAX3832 +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator ABSOLUTE MAXIMUM RATINGS Positive Supply Voltage (VCC)...............................-0.5V to +5.0V Input Voltage (LVDS, TTL)..........................-0.5V to (VCC + 0.5V) CML Input Voltage ..........................(VCC - 0.8V) to (VCC + 0.5V) FIL+, FIL- Voltage.......................................-0.5V to (VCC + 0.5V) TTL Output Voltage ....................................-0.5V to (VCC + 0.5V) LVDS Output Voltage ..................................-0.5V to (VCC +0.5V) CML Output Currents..........................................................22mA Continuous Power Dissipation (TA = +85°C) (Note 1) 64-Pin TQFP-EP (derate 40.0mW/°C above +85°C) .........2.6W Operating Temperature Range...............................0°C to +85°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Note 1: Based on empirical data from the MAX3831/MAX3832 evaluation kit. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, LVDS differential load = 100Ω ±1%, CML load = 50Ω ±1% to VCC, all TTL inputs are open, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C and VCC = +3.3V.) PARAMETER Supply Current SYMBOL ICC CONDITIONS CML inputs and outputs open, LVDS input VOS = 1.2V (Note 2) TYP MAX MAX3831 MIN 440 580 MAX3832 480 614 UNITS mA LVDS INPUTS AND OUTPUTS Input Voltage Range VIN 0 Differential Input Threshold VIDTH -100 Threshold Hysteresis VHYST Input Impedance RIN Input Common-Mode Current IOS Output Voltage High VOH Output Voltage Low VOL Differential Output Voltage Change in Magnitude of Differential Output Voltage for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States VOD 85 LVDS input, VOS = 1.2V +100 mV 100 mV 115 270 Figure 1 1.475 V 400 mV ±25 mV 1.275 V ±25 mV V 250 1.125 ∆VOS TRIEN = GND TRIEN = VCC Ω µA 0.925 VOS Output Current mV 90 ∆VOD Differential Output Impedance 2400 >1 80 Short outputs together (Note 3) MΩ 120 Ω 12 mA CML INPUTS AND OUTPUTS Differential Output Voltage VODp-p Differential Output Impedance 640 800 1000 mVp-p 85 100 115 Ω Output Common-Mode Voltage Single-Ended Input Voltage Range Differential Input Voltage Swing Differential Input Impedance 2 VCC - 0.2 VCC 0.6 VIS Figure 2 400 85 100 _______________________________________________________________________________________ V VCC + 0.4 V 1200 mVp-p 115 Ω +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator (VCC = +3.0V to +3.6V, LVDS differential load = 100Ω ±1%, CML load = 50Ω ±1% to VCC, all TTL inputs are open, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C and VCC = +3.3V.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TTL INPUTS AND OUTPUTS Input Voltage High VIH Input Voltage Low VIL 2.0 Input Current High IIH VIH = 2.0V Input Current Low IIL VIL = 0 Output Voltage High VOH IOH = 20µA Output Voltage Low VOL IOL = 2mA V -250 -50 µA -550 -100 µA 2.4 V 0.4 TRIEN = GND Output Impedance V 0.8 6 V kΩ Note 2: When TEST = GND, the pattern generator will consume an additional 30mA. Note 3: Guaranteed by design and characterization. AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, LVDS differential load = 100Ω ±1%, CML load = 50Ω ±1% to VCC, all TTL inputs are open, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C and VCC = +3.3V.) (Note 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4:1 MULTIPLEXER WITH CLOCK GENERATOR Parallel Input Data Rate Maximum Parallel Input Skew 622.08 tes (Note 5) Serial-Data Output Rate Serial-Data Output Rise/Fall Time tr, tf Mbps ±7.5 ns 2.48832 Gbps 20% to 80% 120 ps 3.5 psRMS 40 psp-p 18 psp-p Serial-Data Output Random Jitter SRJ (Note 6) Serial-Data Output Deterministic Jitter SDJ (Note 7) Serial-Data Setup Time tSU Figure 3 100 ps Serial-Data Hold Time tH Figure 3 100 ps 8 1:4 DEMULTIPLEXER Serial-Data Input Rate Parallel-Data Output Rate Parallel-Clock Output Frequency PCLKO to PDO_ Delay 2.48832 PDO± PCLKO± tCLK-Q LVDS Output Rise/Fall Time 622.08 MAX3831 622.08 MAX3832 155.52 MAX3831, Figure 3 ps 350 ps 65 ps Any differential pair LVDS Channel-to-Channel Skew tSKEW2 PDO1± to PDO4± Note 4: Note 5: Note 6: Note 7: 90 MHz 300 tSKEW1 -100 Mbps 20% to 80% LVDS Differential Skew LVDS Three-State Enable Time Gbps <100 ps 30 ns AC characteristics are guaranteed by design and characterization. Relative to the positive edge of the 155MHz reference clock. PDI1 to PDI4 aligned to RCLKI at reset. Measured with a reference clock jitter of <1psRMS. Deterministic jitter is the arithmetic sum of pattern-dependent jitter and pulse-width distortion. _______________________________________________________________________________________ 3 MAX3831/MAX3832 DC ELECTRICAL CHARACTERISTICS (continued) MAX3831/MAX3832 +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator PDO+ V RL = 100Ω D VOD PDOVPDO- VOH |VOD| SINGLE-ENDED OUTPUT VPDO+ VOS VOL +VOD DIFFERENTIAL OUTPUT 0V 0V (DIFF) VODp-p = VPDO+ - VPDO-VOD Figure 1. Definition of the LVDS Output SDI+ 200mV MIN 600mV MAX SDI- (SDI+) - (SDI-) VID 400mVp-p MIN 1200mVp-p MAX Figure 2. Definition of the CML Input tSCLK = 1 / fSCLK SCLKI tSU tH SDI PCLKO tCLK-Q PDO1–PDO4 NOTE: SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLKI = (SCLKI+) - (SCLKI-). Figure 3. Timing Parameters 4 _______________________________________________________________________________________ +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator SERIAL-DATA OUTPUT JITTER SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT (mA) MAX3831/2 toc01 MAX3832 500 223-1 PRBS PATTERN WIDEBAND RMS JITTER = 2.48ps MAX3831/2 toc03 600 MAX3831/2 toc02 SERIAL-DATA OUTPUT EYE DIAGRAM MAX3831 400 300 200 100 0 5ps/div 50ps/div -50 -25 0 25 50 75 100 TEMPERATURE (°C) SERIAL-DATA HOLD TIME 8 6 2 ERROR-FREE OPERATION 0 80 HOLD TIME (ps) 4 -2 60 40 20 -4 CHANNEL ALIGNED TO RCLKI -6 0 -8 -20 -10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 -50 1.6 -25 0 25 50 75 100 DATA TO RCLKI DELAY AT RESET (ns) TEMPERATURE (°C) SERIAL-DATA SETUP TIME MAX3831 PARALLEL CLOCK-TO-DATA OUTPUT PROPAGATION DELAY vs. TEMPERATURE 80 60 40 20 300 MAX3831/2 toc07 MAX3831/2 toc06 100 PCLKO TO PDO_ PROPAGATION DELAY (ps) 0 SETUP TIME (ps) MAX3831/2 toc05 100 MAX3831/2 toc04 VARIATION OF DATA DELAY AFTER RESET (ns) ELASTIC STORE RANGE 10 250 200 150 100 50 0 0 -50 -25 0 25 50 TEMPERATURE (°C) 75 100 -50 -25 0 25 50 75 100 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX3831/MAX3832 Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) MAX3831/MAX3832 +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator Pin Description PIN NAME 1, 16, 25, 28, 29, 32, 43, 48, 49, 60, 63 GND Supply Ground 2, 5, 10, 13, 17, 24, 38, 55, 59, 64 VCC +3.3V Supply Voltage 3 SDO- Negative CML Serial-Data Output, 2.488Gbps 4 SDO+ Positive CML Serial-Data Output, 2.488Gbps 6 LBEN Line Loopback Enable. When this TTL input is forced low, the CML serial-data inputs (SDI±) route directly to the CML serial-data outputs (SDO±). No other inputs or outputs are affected. An internal 15kΩ pull-up resistor pulls LBEN high for normal operation. See Test Loopbacks. 7 TEST Self-Test Enable. When this TTL input is forced low, the built-in pattern generator generates a standard OC-12 SONET-like frame of 12 A1s, 12 A2s, and 9696 bytes of 27 - 1 pseudorandom bits. This also enables an internal serial-system-loopback path. The CML inputs (SDI± and the SCLK±) and the LVDS inputs are ignored in this mode. An internal 15kΩ pullup resistor pulls TEST high for normal operation. 8 SDI+ Positive CML Serial-Data Input, 2.488Gbps 9 SDI- Negative CML Serial-Data Input, 2.488Gbps 11 SCLKI+ Positive CML Serial-Clock Input, 2.488GHz 12 SCLKI- Negative CML Serial-Clock Input, 2.488GHz 14 PCLKO- Negative LVDS Parallel-Clock Output, 622.08MHz (MAX3831); 155.52MHz (MAX3832) Positive LVDS Parallel-Clock Output, 622.08MHz (MAX3831); 155.52MHz (MAX3832) 6 15 PCLKO+ 18–23, 26, 27 N.C. 30 RSETFR 31 LOF 33 TRIEN FUNCTION No Connection Frame Reset. When this TTL input is forced low, the frame detector and pattern generator are reset. The LOF output is also asserted low. An internal 15kΩ pull-up resistor pulls RSETFR high for normal operation. TTL Loss-of-Frame Output. Asserts low in a loss-of-frame condition. 3-State Enable. When this TTL input is forced low, all TTL and LVDS outputs go into a highimpedance state. An internal 15kΩ pull-up resistor pulls TRIEN high for normal operation. 34, 36, 39, 41 PDO4- to PDO1- Negative LVDS Parallel-Data Output, 622Mbps 35, 37, 40, 42 PDO4+ to PDO1+ Positive LVDS Parallel-Data Output, 622Mbps 44, 46, 50, 52 PDI4- to PDI1- Negative LVDS Parallel-Data Input, 622Mbps 45, 47, 51, 53 PDI4+ to PDI1+ Positive LVDS Parallel-Data Input, 622Mbps 54 PLBEN Parallel System Loopback Enable. When this TTL input is forced low, the LVDS parallel inputs route through the elastic store to the LVDS parallel outputs. This bypasses the highspeed mux and demux. An internal 15kΩ pull-up resistor pulls PLBEN high for normal operation. 56 RCLKI- Negative LVDS Reference Clock Input, 155.52MHz 57 RCLKI+ Positive LVDS Reference Clock Input, 155.52MHz _______________________________________________________________________________________ +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator PIN NAME FUNCTION 58 RSETES Elastic Store Reset. The elastic buffer is centered on a rising edge of RSETES, maximizing the elastic store range. Data must be present for 10µs before applying a pulse of at least 10ns. An internal 15kΩ pull-up resistor pulls RSETES high for normal operation. 61 FIL- Negative PLL Filter Capacitor Input. Connect a 0.33µF capacitor between FIL+ and FIL-. 62 FIL+ Positive PLL Filter Capacitor Input. Connect a 0.33µF capacitor between FIL+ and FIL-. EP Exposed Paddle Ground. This must be soldered to a circuit board for proper thermal performance (see Package Information). _______________Detailed Description The MAX3831/MAX3832 use a 4:1 mux and 1:4 demux with an elastic store buffer to simplify SDH/SONET interconnect I/O routing. The 622Mbps low-voltage differential signal (LVDS) parallel inputs pass through the 10-bit elastic store buffer, which accommodates ±7.5ns skew on any single input relative to the 155MHz reference clock input RCLKI. This reference clock is required to synthesize the internal 2.488GHz clock used to drive the elastic store and 4:1 multiplexer. All TTL and LVDS outputs can be placed in a high-impedance state. See Figure 4 for a functional diagram. The 4:1 mux bit-interleaves the parallel data, providing a 2.488Gbps CML serial output to the optical or electrical driver. The CML serial input receives the 2.488Gbps data, the demux deinterleaves it to 622Mbps and sends the data to the frame detector. The frame detector monitors one 622Mbps channel and rolls the demux into the proper channel assignment. The MAX3831/MAX3832 include high-speed, built-in self-test (BIST), which also allows testing of the 622Mbps parallel-system loopback and the 2.488Gbps line loopback. Elastic Store Buffer Each parallel-data input, PDI1 to PDI4, passes through its respective 10-bit elastic store buffer. Following an elastic store reset, this buffer accommodates ±7.5ns of skew on any input relative to the 155MHz reference clock. Figure 5 illustrates the elastic store buffer relationship with RCLKI. The Elastic Store Range graph in the Typical Operating Characteristics shows the amount of data skew tolerated. Following a 10µs power-up period, the locations of the individual data-channel bit transitions are acquired, guaranteeing data preservation. The output of this block passes directly into the 4:1 mux. After power-up, the elastic store buffer must be reset by applying a low pulse on RSETES for at least 10ns. Due to the inherent uncertainty of the data transitions between the parallel-data inputs there is no bit or frame alignment between these inputs. However, the demux ensures proper channel assignment is maintained. Bit-Interleaved Multiplexer/ Demultiplexer The MAX3831/MAX3832 use a bit interleave/deinterleave mux/demux. To guarantee channel assignment, one of the four channels is inverted before multiplexing to provide a reference for the frame detector during demultiplexing. After demultiplexing, the same channel is inverted back to the original data format. Frame Detector After a 2.5Gbps serial data is bit deinterleaved into four 622Mbps channels, an SDH/SONET frame detector monitors the fourth channel, looking for the 32-bit pattern (A1A1A2A2) in the OC-12 header. To maintain correct channel assignment, the demux outputs rotate until this 32-bit overhead pattern is reliably detected. A lossof-frame output, LOF, indicates when the received data is in or out of frame. When LOF goes high, the frame pattern is detected and the demux outputs are correctly assigned. When LOF is low, the frame detection circuitry is searching for the correct frame. A RSETFR (TTL, active low) is included to reset the frame detector when necessary. The frame detector uses an algorithm to detect an inframe condition and a loss-of-frame condition; this algorithm is implemented to meet the SONET in-frame and false-frame specs. The frame_search state will occur upon start-up or reset. In this state, the frame detector scans through the incoming serial data searching for the framing pattern in the channel 4 output of the demux. While in this state, if the framing pattern is not found within 250µs, the demux channels are shifted (rolled) and the frame search continues (Figure 6). In-frame will be declared if two consecutive framing patterns are found at the correct byte locations within the SONET frame (9720 bytes). If this pattern is not pre- _______________________________________________________________________________________________________ 7 MAX3831/MAX3832 Pin Description (continued) MAX3831/MAX3832 +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator TEST RSETES (155MHz) RCLKI+ RCLKI- FIL+ TRIEN FIL- 155MHz LVDS 622MHz PATTERN GENERATOR MAX3831 MAX3832 FREQUENCY GENERATOR 2.488GHz LBEN CK PDI1+ PDI1PDI2+ ES LVDS SDO+ 4:1 MUX ES SDO- LVDS PDI2- LINE LOOPBACK PDI3+ PDI3- ES LVDS 2.488Gbps SYSTEM LOOPBACK TEST PDI4+ PDI4- ES LVDS 622Mbps PARALLEL LOOPBACK PDO1+ PDO1- LVDS D PDO2+ PDO2- 2.488Gbps 1:4 DEMUX LVDS SDI+ SDI- PDO3+ PDO3- LVDS CK PDO4+ PDO4- LVDS SCLKI+ SCLKI- ROTATE FRAME DETECTOR PLBEN PCLKO+ PCLKO- 2.488GHz LVDS 622MHz CLOCK GENERATOR * RSETFR *MAX3831: fPCLKO = 622MHz, MAX3832: fPCLKO = 155MHz LOF Figure 4. Functional Diagram DATA INPUT PDI1 PDI2 A1 A0 B0 B1 B2 PDI4 B1 C1 C0 PDI3 DATA OUTPUT OF ELASTIC STORE AT t = to A0 D0 C0 D1 D1 RSETES ≥10ns Built-In Self-Test with On-Chip Serial Loopback RCLKI +tes A0 PDI1 PDI2 PDI3 PDI4 -tes B1 C0 A1 DATA OUTPUT OF ELASTIC STORE AT t > to A0 B2 C1 D0 sent at the correct location (false frame), the state machine will return to the frame_search state described above. While in the in_frame state, each frame will be checked for a framing pattern at the correct location. Four consecutive false frames will cause the state machine to return to the frame_search state described above. The false-frame counter is reset with three or fewer consecutive false frames. B1 C0 D1 D1 An on-chip pattern generator can be enabled to produce a 622Mbps SDH/SONET-like transport overhead followed by a pseudorandom bit sequence. This consists of 12 A1s, 12 A2s, and a pseudorandom bit stream (PRBS = 27 - 1). When TEST is low, this pattern is distributed to all parallel inputs, bypassing the LVDS input buffers. Note, this pattern is skewed by one 622MHz Figure 5. Example of Elastic Store Function 8 _______________________________________________________________________________________ +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator MAX3831/MAX3832 FRAME DETECT START-UP OR RESET START 250µs TIMER FRAME_SEARCH NO TIMER TIMED OUT? LOF = 0 FRAME PATTERN DETECTED? YES ROLL DATA NO YES 1 FRAME DETECTED RESET BYTE AND FRAME FRAME PATTERN DETECTED? NO NO YES FRAME PATTERN DETECTED? YES IN_FRAME NO FRAME PATTERN DETECTED? LOF = 1 YES NO FRAME PATTERN DETECTED? NO FRAME PATTERN DETECTED? YES YES Figure 6. Frame Detection Flow Diagram _______________________________________________________________________________________ 9 MAX3831/MAX3832 +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator clock cycle between each channel. In this test mode, serial data is internally looped back to the demux. All frame detect logic is exercised using this mode. The CML inputs (SDI± and SCLKI±) and LVDS inputs (PDI_±) are ignored in this mode. After the BIST mode is enabled, the loss-of-frame flag LOF goes high, indicating that the selftest has passed. In normal operation, TEST is left open (internally pulled high), disabling the pattern generator and accepting data from the parallel input channels. VCC VCC 50Ω 50Ω 50Ω 50Ω SDO+ SDI+ Test Loopbacks Two additional test loopbacks are provided: parallel system loopback and serial line loopback. Parallel System Loopback In parallel system loopback, four 622Mbps parallel input channels are phase aligned by an associated 10bit elastic store and routed to the output LVDS buffers. This loopback is controlled by setting PLBEN low. Normal data transmission is resumed when PLBEN goes high (internally pulled high). Serial Line Loopback Serial line loopback is used for testing the performance of the optical transceiver and the transmission link. The received 2.488Gbps data stream is routed to the transmit CML output buffer. Line loopback is enabled when LBEN is asserted low. When LBEN is left open (internally pulled high), normal serial-data transmission resumes. LVDS Parallel Interface The MAX3831 parallel interface includes four OC-12 data inputs, a 155MHz reference clock input, four 622Mbps parallel-data outputs, and a 622MHz parallelclock output (MAX3832, fPCLKO = 155MHz). All parallel inputs and outputs are LVDS compatible to minimize power dissipation, speed transition time, and improve noise immunity. The 155MHz input signal at RCLKI requires a duty cycle between 40% and 60%. The LVDS outputs go into a high-impedance state when TRIEN is forced low. This simplifies system checks by allowing vectors to be forced on the LVDS outputs. CML Serial Interface The MAX3831/MAX3832 provide a 2.488Gbps serialdata stream to a driver and accept 2.488Gbps serial data and a 2.488GHz clock signal from an external clock and data recovery device (MAX3876). The highspeed interface is CML compatible, resulting in lower system power dissipation and excellent performance (Figure 7). 10 SDO- SDI- MAX3831 MAX3832 MAX3876 Figure 7. CML-to-CML Interface __________Applications Information Low-Voltage Differential Signal Inputs/Outputs The MAX3831/MAX3832 have LVDS inputs and outputs for interfacing with high-speed digital circuitry. All LVDS inputs and outputs are compatible with the IEEE-1596.3 LVDS specification. This technology uses 250mV to 400mV differential low-voltage amplitudes to achieve fast transition times, minimize power dissipation, and improve noise immunity. For proper operation, the parallel clock and data LVDS outputs (PCLKO+, PCLKO-, PDO_+, PDO_-) require 100Ω differential DC termination between the inverting and noninverting outputs. Do not terminate these outputs to ground. The parallel-data LVDS inputs (PDI_+, PDI_-) are internally terminated with 100Ω differential input resistance and therefore do not require external termination. Interfacing with PECL/ECL Input Levels When interfacing with differential PECL input levels, it is important to attenuate the signal while still maintaining 50Ω termination (Figures 8 and 9). Observe the common-mode input voltage specifications. AC-coupling is required if a VCC other than 3.3V is used to maintain the input common-mode level (Figure 8). ______________________________________________________________________________________ +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator MAX3831/MAX3832 VCC VCC = 3.3V 50Ω 0.1µF 25Ω PECL LEVELS VCC = 3.3V 50Ω 50Ω SDI+ 82Ω 50Ω SDI+ RT* 82Ω 100Ω 0.1µF RT* PECL OUTPUT 25Ω 82Ω SDI- SDI82Ω MAX3831 MAX3832 MAX3831 MAX3832 *SELECT RT SUCH THAT THE CORRECT PECL COMMON-MODE LEVEL IS ACHIEVED (TYPICAL PECL OUTPUT CURRENT = 14mA). Figure 8. PECL-to-CML Interface Figure 9. Direct Coupling of a PECL Output into the MAX3831/ MAX3832 Layout Techniques For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3831/MAX3832 high-speed inputs and outputs. Place power-supply decoupling as close to VCC as possible. To reduce feedthrough, take care to isolate the input signals from the output signals. ______________________________________________________________________________________ 11 +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator GND PDI2- PDI2+ PDI1- PLBEN PDI1+ VCC RCLKI- RCLKI+ RSETES VCC GND 63 62 61 60 59 58 FIL- GND 64 FIL+ TOP VIEW VCC MAX3831/MAX3832 Pin Configuration 57 56 55 54 53 52 51 50 49 GND 1 48 GND VCC 2 47 PDI3+ SDO- 3 46 PDI3- SDO+ 4 45 PDI4+ VCC 5 44 PDI4- LBEN 6 43 GND TEST 7 42 PDO1+ SDI+ 8 41 PDO1- SDI- 9 MAX3831 MAX3832 VCC 10 40 PDO2+ 39 PDO2- SCLKI+ 11 38 VCC SCLKI- 12 37 PDO3+ VCC 13 36 PDO3- PCLKO- 14 35 PDO4+ PCLKO+ 15 34 PDO4- GND 16 33 TRIEN GND LOF GND RSETFR GND N.C. N.C. GND VCC N.C. N.C. N.C. N.C. N.C. VCC N.C. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TQFP-EP ___________________Chip Information TRANSISTOR COUNT: 14,134 12 ______________________________________________________________________________________ +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator 64L, TQFP.EPS ______________________________________________________________________________________ 13 MAX3831/MAX3832 Package Information +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator MAX3831/MAX3832 Package Information (continued) 14 ______________________________________________________________________________________ +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator MAX3831/MAX3832 NOTES ______________________________________________________________________________________ 15 MAX3831/MAX3832 +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.