19-1498; Rev 0; 6/99 KIT ATION EVALU E L B AVAILA +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs Features ♦ Single +3.3V Supply ♦ 495mW Power Consumption ♦ Exceeds ANSI, ITU, and Bellcore Specifications ♦ 155Mbps (16-bit wide) Parallel to 2.5Gbps Serial Conversion ♦ Clock Synthesis for 2.5Gbps ♦ Multiple Clock Reference Frequencies (155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz) ♦ LVDS Parallel Clock and Data Inputs ♦ Additional High-Speed Output for System Loopback Testing Applications Ordering Information 2.5Gbps SDH/SONET Transmission Systems PART 2.5Gbps ATM/SONET Access Nodes TEMP. RANGE MAX3890ECB -40°C to +85°C *EP = Exposed Paddle Add/Drop Multiplexers Digital Cross-Connects PIN-PACKAGE 64 TQFP-EP* Pin Configuration appears at end of data sheet. ATM Backplanes Typical Operating Circuit +3.3V 155MHz REF. CLOCK INPUT +3.3V TTL +3.3V PDI0+ RCLK+ RCLK- CLKSET PDI0- VCC SOS SDO+ 130Ω 130Ω VCC SDOPDI15+ OVERHEAD GENERATION 82Ω PDI15- 82Ω MAX3867 PCLKI+ PCLKIPCLKO+ PCLKOGND +3.3V MAX3890 130Ω 130Ω 82Ω 82Ω SCLKO+ SCLKOFIL+ FIL- SLBO+ SLBO- 330nF OPTIONAL CONNECTION TO MAX3880 FOR SYSTEM LOOPBACK TESTING. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE (Z0 = 50Ω). ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX3890 General Description The MAX3890 serializer is ideal for converting 16-bitwide, 155Mbps parallel data to 2.5Gbps serial data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts low-voltage differential-signal (LVDS) clock and data inputs for interfacing with high-speed digital circuitry, and delivers PECL serial data and clock outputs. A fully integrated PLL synthesizes an internal 2.5GHz serial clock from a 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz reference clock. A loopback data output is provided to facilitate system diagnostic testing. The MAX3890 is available in the extended temperature range (-40°C to +85°C) in a 64-pin TQFP exposedpaddle (EP) package. MAX3890 +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect to GND) VCC .......................................................................-0.5V to +5V All Inputs, FIL+, FIL- ...............................-0.5V to (VCC + 0.5V) Output Current LVDS Outputs (PCLKO±)................................................10mA PECL Outputs (SDO±, SCLKO±)....................................50mA CML Outputs (SLBO±)....................................................15mA Continuous Power Dissipation (TA = +85°C) TQFP-EP (derate 44.8mW/°C above +85°C) ......................1W Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, differential LVDS loads = 100Ω ±1%, PECL loads = 50Ω ±1% to (VCC - 2V), CML loads = 50Ω ±1% to VCC, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) PARAMETER Supply Current SYMBOL ICC CONDITIONS MIN PECL outputs unterminated, SOS = low TYP MAX UNITS 150 230 mA PECL OUTPUTS (SDO±, SCLKO±) TA = 0°C to +85°C TA = -40°C TA = 0°C to +85°C Output Voltage Low VOL TA = -40°C LVDS INPUTS AND OUTPUTS (PCLKO±, PDI_±, PCLKI±, RCLKI±) Input Voltage Range VI Differential input voltage = 100mV Differential Input Threshold VIDTH Threshold Hysteresis VHYST Differential Input Resistance RIN Output Voltage High VOH Output Voltage Low VOL |VOD| Differential Output Voltage Figure 5 Output Voltage High Change in Magnitude of Differential Output Voltage for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States Single-Ended Output Resistance Change in Magnitude of Single-Ended Output Resistance for Complementary Outputs 2 VOH VCC - 1.025 VCC - 1.085 VCC - 1.81 VCC -1.83 VCC - 0.88 VCC - 0.88 VCC - 1.62 VCC - 1.555 0 -100 85 2.4 100 400 ±25 mV 1.275 V ±25 mV 95 140 Ω ±2.5 ±10 % 60 100 0.925 250 1.125 ∆VOS RO ∆RO 40 V V mV mV Ω V V mV ∆|VOD| VOS V _______________________________________________________________________________________ 115 1.475 +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs (VCC = +3.0V to +3.6V, differential LVDS loads = 100Ω ±1%, PECL loads = 50Ω ±1% to (VCC - 2V), CML loads = 50Ω ±1% to VCC, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±500 µA PROGRAMMING INPUT (CLKSET) CLKSET Input Current ICLKSET CLKSET = 0 or VCC TTL INPUT (SOS) Input Voltage High VIH Input Voltage Low VIL Input Current High IIH Input Current Low IIL 2.0 V 0.8 V -10 10 µA -10 10 µA 100 400 mV CURRENT MODE LOGIC (CML) OUTPUTS (SLBO±) Differential Output Voltage Single-Ended Output Resistance |VOD| RO Ω 50 AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, differential LVDS load = 100Ω ±1%, PECL loads = 50Ω ±1% to (VCC - 2V), CML loads = 50Ω ±1% to VCC, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) (Note 1) PARAMETER Serial Clock Rate Parallel Data Setup Time Parallel Data-Hold Time PCLKO to PCLKI Skew SYMBOL fSCLK tSU tH tSKEW Output Jitter Generation (SCLKO±) Φ0 PECL Differential Output Rise/Fall Time tR, tF CONDITIONS (Note 2) (Note 2) Figure 2 Jitter bandwidth = 12kHz to 20MHz, RCLK amplitude > |VIDTH| (Note 3) MIN TYP 2.488 300 700 0 20% to 80% MAX +4.0 UNITS GHz ps ps ns 3 psRMS 120 ps Parallel Input Clock Rate fPCLKI 155.52 Reference Clock Input (RCLKI) Rise/Fall Time tR, tF 20% to 80%, f = 155.52MHz 1.0 ns Parallel Clock Output (PCLKO) Rise/Fall Time tR, tF 20% to 80% 1.0 ns Serial Clock Output (SCLKO) to Serial-Data Output (SDO) Delay tSCLK-SD 290 ps SCLKO rising edge to SDO edge 110 MHz Note 1: AC characteristics guaranteed by design and characterization. Note 2: Setup and hold times are relative to the rising edge of PCLKI+, measured by applying a 155.52MHz differential parallel clock with rise/fall time = 1ns (20% to 80%). See Figure 2. Note 3: For fRCLK = 38.88MHz, the minimum reference clock amplitude is ≥ 200mV. _______________________________________________________________________________________ 3 MAX3890 DC ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VCC = +3.3V, PECL loads = 50Ω ±1%, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. TEMPERATURE SERIAL-DATA OUTPUT EYE DIAGRAM MAX3890-02 MAX3890-01 200 180 SUPPLY CURRENT (mA) 160 140 120 PECL OUTPUTS UNTERMINATED 100 -50 -25 0 25 50 75 100 50ps/div TEMPERATURE (°C) OUTPUT JITTER GENERATION vs. RCLK AMPLITUDE SERIAL-DATA OUTPUT JITTER fRCK = 155.52MHz MAX3890 toc04 fRCK = 155.52MHz 3.0 OUTPUT JITTER GENERATION (ps) MAX3890-03 MAX3890 +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs 2.5 fRCLK = 38.88MHz 2.0 fRCLK = 51.84MHz 1.5 1.0 0.5 fRCLK = 155.52MHz fRCLK = 77.76MHz 0 5ps/div TOTAL WIDEBAND RMS JITTER = 2.155ps, PEAK-TO-PEAK JITTER = 15.7ps 4 100 150 200 250 300 RCLK AMPLITUDE (mV) _______________________________________________________________________________________ 350 400 +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs PIN NAME 1, 17, 33, 48, 49, 63 GND Ground FUNCTION 2, 5, 7, 10, 13, 14, 32, 56, 60, 64 VCC +3.3V Supply Voltage 3 SLBO- System Loopback Inverting Output. Enabled when SOS is high. 4 SLBO+ System Loopback Noninverting Output. Enabled when SOS is high. 6 SOS System Loopback Output Select. System loopback disabled when low. 8 SCLKO- Inverting PECL Serial Clock Output 9 SCLKO+ Noninverting PECL Serial Clock Output 11 SDO- Inverting PECL Serial-Data Output 12 SDO+ Noninverting PECL Serial-Data Output 15 PCLKI+ Noninverting LVDS Parallel Clock Input. Connect the incoming parallel-clock signal to the PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal. 16 PCLKI- Inverting LVDS Parallel Clock Input. Connect the incoming parallel-clock signal to the PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal. 18, 20, 22, 24, 26, 28, 30, 34, 36, 38, 40, 42, 44, 46, 50, 52 PDI15+ to PDI0+ Noninverting LVDS Parallel Data Inputs. Data is clocked on the PCLKI positive transition. 19, 21, 23, 25, 27, 29, 31, 35, 37, 39, 41, 43, 45, 47, 51, 53 PDI15- to PDI0- Inverting LVDS Parallel Data Inputs. Data is clocked on the PCLKI positive transition. 54 PCLKO+ Noninverting LVDS Parallel Clock Output. Use positive transition of PCLKO to clock the overhead management circuit. 55 PCLKO- Inverting LVDS Parallel Clock Output. Use positive transition of PCLKO to clock the overhead management circuit. 57 RCLK+ Noninverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal reference clock to the RCLK inputs. 58 RCLK- Inverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal reference clock to the RCLK inputs. 59 CLKSET Reference Clock Rate Programming Pin: CLKSET = VCC: Reference Clock Rate = 155.52MHz CLKSET = Open: Reference Clock Rate = 77.76MHz CLKSET = 20kΩ to GND: Reference Clock Rate = 51.84MHz CLKSET = GND: Reference Clock Rate = 38.88MHz 61 FIL- Filter Capacitor Input. Connect a 330nF capacitor between FIL+ and FIL-. 62 FIL+ Filter Capacitor Input. Connect a 330nF capacitor between FIL+ and FIL-. _______________________________________________________________________________________ 5 MAX3890 Pin Description MAX3890 +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs _______________Detailed Description The MAX3890 converts 16-bit-wide, 155Mbps data to 2.5Gbps serial data (Figure 1). It is composed of a 16bit parallel input register, a 16-bit shift register, control and timing logic, PECL output buffers, LVDS input/output buffers, and a frequency-synthesizing PLL (consisting of a phase/frequency detector, loop filter/amplifier, voltage-controlled oscillator (VCO), and prescaler). The PLL synthesizes an internal 2.5Gbps reference used to clock the output shift register. This clock is generated by locking onto the external 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz reference-clock signal (RCLK). The incoming parallel data is clocked into the MAX3890 on the rising transition of the parallel-clockinput signal (PCLKI). Proper operation is ensured if the parallel input register is latched within a window of time (t SKEW) that is defined with respect to the parallelclock-output signal (PCLKO). PCLKO is the synthesized 2.5Gbps internal serial-clock signal divided by 16. The allowable PCLKO-to-PCLKI skew is 0 to +4ns. This defines a timing window after the PCLKO rising edge, during which a PCLKI rising edge may occur (Figure 2). System Loopback The MAX3890 is designed to allow system loopback testing. The loopback outputs (SLBO+, SLBO-) of the MAX3890 may be directly connected to the loopback inputs of a deserializer (such as the MAX3880) for system diagnostics. To enable the SLBO outputs, apply a TTL logic-high signal to the SOS input. Note: The same signal that controls the SOS enable input may also be used to control the SIS enable input on the MAX3880. PDI15+ PDI15- LVDS MAX3890 16-BIT PARALLEL INPUT REGISTER PDI1+ PDI1- LVDS PDI0+ PDI0- LVDS SOS CML PCLKI+ LVDS PCLKI- PRESCALER RCLKI+ PHASE/FREQ DETECT LVDS RCLKI- FILTER PLL VCO DIVIDE BY 16 LATCH 16-BIT SHIFT REGISTER PCLKO+ PCLKO- Figure 1. Functional Diagram 6 SLBO- SHIFT LVDS FIL+ FIL-CLKSET SLBO+ _______________________________________________________________________________________ PECL PECL SDO+ SDO- SCLKO+ SCLKO- +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs MAX3890 PCLKO tSKEW PCLKI tSU PARALLEL INPUT DATA (PDI_) tH VALID PARALLEL DATA* *D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SERIAL OUTPUT DATA (SDO) NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLKO = (PCLKO+) - (PCLKO-). *PDI 15 = D15; PDI14 = D14; ...PDI0 = D0. THIS FIGURE IS NOT INTENDED TO SHOW A SPECIFIC TIMING RELATIONSHIP BETWEEN PARALLEL INPUT DATA AND SERIAL OUTPUT DATA. Figure 2. Timing Diagram Low-Voltage Differential-Signal Inputs and Outputs The MAX3890 has LVDS inputs and outputs for interfacing with high-speed digital circuitry. The LVDS standard is based on the IEEE 1596.3 LVDS specification. This technology uses 250mV to 400mV differential low-voltage swings to achieve fast transition times, minimized power dissipation, and noise immunity. For proper operation, the parallel clock LVDS outputs (PCLKO+, PCLKO-) require 100Ω differential DC termination between the inverting and noninverting outputs. Do not terminate these outputs to ground. The parallel data and parallel clock LVDS inputs (PDI_+, PDI_-, PCLKI+, PCLKI-, RCLK+, RCLK-) are internally terminated with 100Ω differential input resistance, and therefore do not require external termination. PECL Outputs The serial-data PECL outputs (SDO+, SDO-, SCLKO+, SCLKO-) require 50Ω DC termination to (VCC - 2V) (see the Alternative PECL-Output Termination section). Current-Mode Logic Outputs The system loopback outputs (SLBO+, SLBO-) of the MAX3890 are designed using CML. The configuration of the MAX3890 current-mode logic (CML) output circuit includes internal 50Ω back termination to V CC (Figure 3). These outputs are intended to drive a 50Ω transmission line terminated with a matched load impedance. _______________________________________________________________________________________ 7 MAX3890 +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs VCC VCC 50Ω 50Ω SLBO+ 50Ω 50Ω SLBOSLBI+ ESD STRUCTURE SLBI- GND OUTPUT CIRCUIT INPUT CIRCUIT Figure 3. Current-Mode Logic Applications Information +3.3V Alternative PECL-Output Termination Figure 4 shows alternative PECL-output termination methods. Use Thevenin-equivalent termination when a (VCC - 2V) termination voltage is not available. If ACcoupling is necessary, be sure that the coupling capacitor is placed following the 50Ω or Thevenin-equivalent DC termination. Layout Techniques For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Also, use controlled-impedance transmission lines to interface with the MAX3890 clock and data inputs and outputs. 130Ω 130Ω MAX3890 SCLKO+ OR SDO+ Z0 = 50Ω SCLKOOR SDO- Z0 = 50Ω PECL INPUTS 82Ω 82Ω MAX3890 SCLKO+ OR SDO+ Z0 = 50Ω SCLKOOR SDO- Z0 = 50Ω 50Ω HIGHIMPEDANCE INPUTS 50Ω VCC - 2V Figure 4. Alternative PECL-Output Termination 8 _______________________________________________________________________________________ +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs MAX3890 PD+ RL = 100Ω D V VOD PDVPD- VOH |VOD| SINGLE-ENDED OUTPUT VPD+ VOS VOL +VOD VPD+ - VPDDIFFERENTIAL OUTPUT 0V (DIFF) 0V VODp-p = VPD+ - VPD-VOD Figure 5. Driver Output Levels _______________________________________________________________________________________ 9 +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs MAX3890 Pin Configuration GND PDI1+ PDI1- PDI0+ PDI0- PCLKO+ PCLKO- RCLK+ VCC RCLK- FIL- 63 62 61 60 59 58 VCC GND 64 FIL+ VCC CLKSET TOP VIEW 57 56 55 54 53 52 51 50 49 GND 1 48 GND VCC 2 47 PDI2- SLBO- 3 46 PDI2+ SLBO+ 4 45 PDI3- VCC 5 44 PDI3+ SOS 6 43 PDI4- VCC 7 42 PDI4+ SCLKO- 8 41 PDI5- SCLKO+ 9 40 PDI5+ MAX3890 39 PDI6- VCC 10 SDO- 11 38 PDI6+ SDO+ 12 37 PDI7- VCC 13 36 PDI7+ VCC 14 35 PDI8- PCLKI+ 15 34 PDI8+ PCLKI- 16 33 GND VCC PDI9- PDI9+ PDI10- PDI10+ PDI11- PDI11+ PDI12- PDI12+ PDI13- PDI13+ PDI14- PDI14+ PDI15- GND PDI15+ 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TQFP-EP ___________________Chip Information TRANSISTOR COUNT: 4126 10 ______________________________________________________________________________________ +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs 48L,TQFP.EPS 48L,TQFP.EPS ______________________________________________________________________________________ 11 MAX3890 Package Information +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs MAX3890 Package Information (continued) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.