19-4774; Rev 2; 7/04 +3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs ____________________________Features The MAX3690 serializer is ideal for converting 8-bitwide, 77Mbps parallel data to 622Mbps serial data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts TTL clock and data inputs, and delivers a 3.3V differential PECL serialdata output. A fully integrated PLL synthesizes an internal 622MHz serial clock from a low-speed crystal reference clock (77.76MHz, 51.84MHz, or 38.88MHz). The MAX3690 is available in the extended-industrial temperature range (-40°C to +85°C) in a 32-pin TQFP package. ♦ Selectable Reference Clock Frequency: 77.76MHz, 51.84MHz, or 38.88MHz ♦ Single +3.3V Supply ♦ 77Mbps (8-bit) Parallel to 622Mbps Serial Conversion ♦ Clock Synthesis for 622Mbps Serial Data ♦ 200mW Power ♦ TTL Parallel Clock and Data Inputs ♦ Differential 3.3V PECL Serial-Data Output Ordering Information ________________________Applications 622Mbps SDH/SONET Transmission Systems PART 622Mbps ATM/SONET Access Nodes Add/Drop Multiplexers TEMP RANGE PIN-PACKAGE MAX3690ECJ -40°C to +85°C 32 TQFP MAX3690ECJ+ -40°C to +85°C 32 TQFP +Denotes lead-free package. Digital Cross Connects Pin Configuration appears at end of data sheet. Typical Operating Circuit 38.88MHz TTL CRYSTAL REFERENCE PCLKI OVERHEAD GENERATION PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PCLKO VCC = +3.3V RCLK VCC 1µF 1µF CKSET MAX3690 FIL+ FIL- GND SD- SD+ VCC = +3.3V VCC = +3.3V 130Ω 130Ω MAX3668 82Ω 82Ω THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE (Z0 = 50Ω). ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX3690 General Description MAX3690 +3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect to GND) VCC .......................................................................-0.5V to +5V All Inputs, FIL-, FIL+, PCLKO .................-0.5V to (VCC + 0.5V) Output Current PECL Outputs (SD±).......................................................50mA Continuous Power Dissipation (TA = +85°C) TQFP (derate 10.2mW/°C above +85°C) .....................663mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-60°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, PECL loads = 50Ω ±1% to (VCC - 2V), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) PARAMETER Supply Current CKSET Input Current SYMBOL ICC ICKSET CONDITIONS MIN TYP PECL outputs unterminated 60 CKSET = 0 or VCC MAX UNITS 100 mA 500 µA PECL OUTPUTS (SD±) Output High Voltage VOH Output Low Voltage VOL TA = 0°C to +85°C VCC - 1.025 VCC - 0.88 TA = -40°C VCC - 1.085 VCC - 0.88 TA = 0°C to +85°C VCC - 1.81 VCC - 1.62 TA = -40°C VCC - 1.83 VCC - 1.555 V V TTL INPUTS AND OUTPUTS (PCLKI, RCLK, PCLKO, PD_) Input High Voltage VIH Input Low Voltage VIL 0.8 V Input High Current IIH VIN = VCC -10 10 µA IIL 10 µA Input Low Current 2.0 VIN = 0 -10 Output High Voltage VOH IOH = 400µA 2.4 Output Low Voltage VOL IOL = -400µA V V 0.44 V AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, PECL loads = 50Ω ±1% to (VCC - 2V), all TTL thresholds set to VCC/2, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) (Note 1) PARAMETER Serial Clock Rate SYMBOL CONDITIONS MIN fSCLK TYP MAX 622.08 UNITS MHz Parallel Data Setup Time tSU 1200 ps Parallel Data Hold Time tH 1000 ps tSKEW 0 Allowable Parallel Clock Output to Parallel Clock Input Delay Output Random Jitter PECL Differential Output Rise/Fall Time Φ0 tR, tF 5.0 ns 11 psRMS 20% to 80% 200 ps TTL Output Rise Time tR CLOAD = 15pF, VOUT = 0.8V to 2.0V 650 ns TTL Output Fall Time tF CLOAD = 15pF, VOUT = 0.8V to 2.0V 550 ns Note 1: AC characteristics guaranteed by design and characterization. Note 2: All TTL thresholds set to VCC / 2. 2 _______________________________________________________________________________________ +3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs PARALLEL DATA SETUP TIME vs. TEMPERATURE 65 60 55 50 -65 -70 -75 -80 -85 -25 0 25 50 75 100 -40 -25 0 255 250 245 240 25 50 75 -40 85 SERIAL DATA RANDOM JITTER (RCLKI = 77.76MHz) 0 25 50 75 85 SERIAL-DATA OUTPUT EYE DIAGRAM (622Mbps, PRBS) ALLOWED PCLKO to PCLKI SKEW vs. TEMPERATURE MAX3690-07 15 MAX3690-05 -25 TEMPERATURE (°C) TEMPERATURE (¡C) TEMPERATURE (°C) VCC = 3.3V 260 230 -95 -50 265 235 -90 45 270 MAX3690-03 MAX3690-02 -60 MAX3690-08 SUPPLY CURRENT (mA) 70 -55 PARALLEL DATA SETUP TIME (ps) MAX3690-01 75 PARALLEL DATA HOLD TIME vs. TEMPERATURE PARALLEL DATA HOLD TIME (ps) SUPPLY CURRENT vs. TEMPERATURE 10 TIME (ns) 2mV/ div 100mV/ div 5 0 RJ = 4.66psRMS 5ps/div TEMPERATURE (°C) -5 0 -50 0 50 100 200ps/div TEMPERATURE (°C) _______________________________________________________________________________________ 3 MAX3690 __________________________________________Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) MAX3690 +3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs ______________________________________________________________Pin Description PIN NAME FUNCTION 1–8 PD0–PD7 9, 10, 17, 18, 19, 24, 25, 26, 31, 32 TTL Parallel-Data Inputs. Data is clocked in on the PCLKI signal’s positive transition. GND 11 PCLKO 12, 13, 16, 21, 28, 29 VCC +3.3V Supply Voltage 14 SD- Inverting PECL Serial-Data Output 15 SD+ Noninverting PECL Serial-Data Output Ground TTL Parallel-Clock Output. Use positive transition of PCLKO to clock the overhead management circuit. Reference Clock Rate Programming Pin. CKSET = open: Reference clock rate = 77.76MHz CKSET = 20kΩ to GND: Reference clock rate = 51.84MHz CKSET = GND: Reference clock rate = 38.88MHz 20 CKSET 22 FIL- Filter Capacitor Input. Connect a 1µF capacitor between FIL- and VCC. 23 FIL+ Filter Capacitor Input. Connect a 1µF capacitor between FIL- and VCC. 27 RCLK TTL Reference-Clock Input. Connect a crystal reference clock (77.76MHz, 51.84MHz or 38.88MHz) to the RCLK input. The active edge is the positive transitioning edge. 30 PCLKI TTL Parallel-Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI input. The active edge is the positive transitioning edge. _______________Detailed Description The MAX3690 serializer comprises an 8-bit parallel input register, an 8-bit shift register, control and timing logic, a PECL output buffer, TTL input/output buffers, and a frequency-synthesizing PLL (consisting of a phase/frequency detector, loop filter/amplifier, voltagecontrolled oscillator, and programmable prescaler). This device converts 8-bit-wide, 77Mbps parallel data to 622Mbps serial data (Figure 1). The PLL synthesizes an internal 622MHz reference used to clock the output shift register. This clock is generated by locking onto the external crystal reference clock signal (RCLK) operating at either 77.76MHz, 51.84MHz, or 38.88MHz. The incoming par- 4 allel data is clocked into the MAX3690 on the rising transition of the parallel-clock-input signal (PCLKI). The control and timing logic ensure proper operation if the parallel-input register is latched within a window of time that is defined with respect to the parallel-clock-output signal (PCLKO). PCLKO is the synthesized 622MHz internal serial-clock signal divided by eight. Parallelclock output to parallel-clock-input delay (skew) must be observed. Figure 2 shows the timing diagram. PECL Outputs The serial-data PECL outputs (SD+, SD-) require 50Ω DC termination to (VCC - 2V). See the Alternative PECLOutput Termination section. _______________________________________________________________________________________ +3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs PD6 TTL TTL PD5 PD4 TTL TTL TTL PD1 PD0 8-BIT PARALLEL INPUT REGISTER TTL PD3 PD2 TTL TTL PCLKI TTL PRESCALER CKSET RCLK MAX3690 PD7 SHIFT PHASE/FREQ DETECT TTL VCO CONTROL LATCH 8-BIT SHIFT REGISTER PECL SDOH SDOL TTL MAX3690 FIL+ FIL- PCLKO Figure 1. Functional Diagram PCLKO tSKEW PCLKI tSU PD_ tH VALID PARALLEL DATA SD D7 D6 D5 D4 D3 D2 D1 D0 NOTE: PD7 = D7, PD6 = D6, PD5 = D5, PD4 = D4, PD3 = D3, PD2 = D2, PD1 = D1, PD0 = D0 Figure 2. Timing Diagram _______________________________________________________________________________________ 5 MAX3690 +3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs __________Applications Information +3.3V Alternative PECL-Output Termination Figure 3 shows alternative PECL-output-termination methods. Use Thevenin-equivalent termination when a (VCC - 2V) termination voltage is not available. If AC coupling is necessary, be sure that the coupling capacitor is placed following the 50Ω or Theveninequivalent DC termination. 130Ω 130Ω MAX3690 Layout Techniques SD+ Z0 = 50Ω SD- Z0 = 50Ω For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Also, use controlled-impedance transmission lines to interface with the MAX3690 data outputs. PECL INPUTS 82Ω 82Ω MAX3690 SD+ Z0 = 50Ω SD- Z0 = 50Ω 50Ω HIGHIMPEDENCE INPUTS 50Ω VCC - 2V Figure 3. Alternative PECL-Output Termination 6 _______________________________________________________________________________________ +3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs 24 23 22 21 20 19 18 17 GND FIL+ FILVCC CKSET GND GND GND TOP VIEW MAX3690 Pin Configuration MAX3690 16 15 14 13 12 11 10 9 VCC SD+ SDVCC VCC PCLKO GND GND 1 2 3 4 5 6 7 8 25 26 27 28 29 30 31 32 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 GND GND RCLK VCC VCC PCLKI GND GND TQFP _______________________________________________________________________________________ 7 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) TQFPPO.EPS MAX3690 +3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.