Ordering number : ENA1744 LC72725KVS CMOS IC RDS(RBDS) Demodulation IC Overview The LC72725KVS is ICs that implement the signal processing required by the European Broadcasting Union RDS (Radio Data System) standard and by the US NRSC (National Radio System Committee) RBDS (Radio Broadcast Data System) standard. These ICs include band-pass filter, demodulator,and data buffer on chip. RDS data can be read out from this on-chip memory by external clock input in slave operation mode. Functions • Bandpass filter • RDS Demodulation • Buffer • Data output • RDS-ID • Standby control • Fully adjustment free • Low Voltage : Switched capacitor filter (SCF) : 57KHz carrier and RDS data clock regeneration, biphase decode, differential decode. : 128 bit (about 100ms) can be restored in the on-chip data buffer. : Master or slave output mode can be selected. : Detect RDS signal which can be reset by RST signal input. : Crystal oscillator can be stopped. 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 60910HKIM 20100427-S00009 No.A1744-1/9 LC72725KVS Specifications Absolute Maximum Ratings at Ta = 25°C, VSSd = VSSa = 0V Parameter Symbol Pin Name Conditions Ratings VDD max VDDd, VDDa Maximum input voltage VIN1 max TEST, MODE, RST -0.3 to +6.5 V VIN2 max XIN, RDCL -0.3 to VDDd+0.3 V VIN3 max MPXIN, CIN -0.3 to VDDa+0.3 V VO1 max RDS-ID(READY) -0.3 to +6.5 V VO2 max XOUT, RDDA, RDCL -0.3 to VDDd+0.3 V VO3 max FLOUT -0.3 to VDDa+0.3 V IO1 max XOUT, FLOUT, RDDA, RDCL IO2 max RDS-ID(READY) Maximum output voltage Maximum output current VDDa≤VDDd+0.3V Unit Maximum supply voltage Allowable power dissipation Pd max (Ta≤85°C) Operating temperature Topr VDD = 3.0V to 5.5V Storage temperature Tstg -0.3 to +6.5 V +3.0 mA +20.0 mA 100 mW -40 to +85 °C -40 to +125 °C Allowable Operating Ranges at Ta = -40 to +85°C, VSSd = VSSa = 0V, VDDd = VDDa = 3.0V to 5.5V Parameter Symbol Pin Name Ratings Conditions min Supply voltage VDD VDDd, VDDa Input high-level voltage VIH1 TEST, MODE, RST VIH2 RDCL VIL TEST, MODE, RST, Input low-level voltage Ta = -40 to +85°C RDCL Output voltage typ 3.0 unit max 5.5 V 0.7VDDd 6.5 V 0.7VDDd VDDd V 0 0.3VDDd V VDDd V 6.5 V 1.6 50 mVrms 400 1500 mVrms VO1 RDDA, RDCL VO2 RDS-ID(READY) VIN MPXIN VXIN XIN Xtal XIN, XOUT CI≤120Ω TXtal XIN, XOUT Fo = 4.332MHz RDCL setup time tCS RDCL, RDDA RDCL high-level time tCH RDCL low-level time tCL Data output time tDC RDCL, RDDA 0.75 READY output time tRC RDCL, READY 0.75 μs READY low-level time tRL READY 107 ms Input amplitude Guaranteed crystal f = 57±2kHz 4.332 oscillator frequencies Crystal oscillator operating MHz ±100 range ppm 0 μs RDCL 0.75 μs RDCL 0.75 μs μs No.A1744-2/9 LC72725KVS Electrical Characteristics at Ta = -40 to +85°C, VSSd = VSSa = 0V, VDDd = VDDa = 3.0V to 5.5V Parameter Symbol Pin Name Ratings Conditions min Internal feedback Rf XIN VHIS TEST, MODE, RST, MΩ 0.1VDDd RDCL Output low-level voltage max 1.0 resistance Hysteresis unit typ V VOL1 RDDA, RDCL I = 2mA 0.4 VOL2 RDS-ID(READY) I = 8mA 0.4 Output high-level voltage VOH RDDA, RDCL I = -2mA Input high-level current IIH1 TEST, MODE, RST, VI = 6.5V VDDd-0.54 IIH2 XIN VI = VDDd IIL1 TEST, MODE, RST, VI = 0V 2.0 RDCL Output off leakage IIL2 XIN VI = 0V IOFF RDS-ID(READY) VO = 6.5V IDD VDDd+VDDa VDDd+VDDa 2.0 current Current drain 1.5 (VDDd = VDDa = 3.3V) V V RDCL Input low-level current V 2.5 5.0 μA 11 μA 5.0 μA 11 μA 5.0 μA 3.5 mA Bandpass Filter Characteristics at Ta = 25°C, VSSd = VSSa = 0V, VDDd = VDDa = 3.0V to 5.5V Parameter Symbol Pin Name Ratings Conditions min Input resistance Rmpxin Rcin typ unit max MPXIN-VSSa f = 57kHz 100 kΩ CIN-VSSa f = 57kHz 100 kΩ Center frequency fc FLOUT 56.5 57.0 57.5 kHz -3dB band width BW-3dB FLOUT 2.5 3.0 3.5 kHz 31 34 dB Gain Gain MPXIN-FLOUT f = 57kHz 28 Stop band attenuation Att1 FLOUT Δf = ±7kHz 30 Att2 FLOUT f<45kHz, f>70kHz 40 dB Att3 FLOUT f<20kHz 50 dB Vref Vref VDDa = 3V Reference voltage output dB 1.5 V No.A1744-3/9 LC72725KVS Package Dimensions Pin Assignment 9 LC72725KV 5 6 7 8 VSSa FLOUT CIN 1.5max (1.3) 4 Top view 0.1 3 VDDa 0.15 0.22 2 MPXIN 0.65 (0.33) 1 VREF 8 RDDA 1 RDS-ID/READY 0.5 6.4 4.4 16 15 14 13 12 11 10 TEST MODE VSSd VDDd 9 XIN 16 XOUT 5.2 RST RDCL unit : mm (typ) 3178B SANYO : SSOP16(225mil) Block Diagram VREF +3V FLOUT CIN +3V VDDa VSSa MPXIN PLL (57kHz) REFERENCE VOLTAGE CLOCK RECOVERY (1187.5Hz) VSSd VREF ANTIALIASING FILTER 57kHz BPF (SCF) VDDd DATA DECODER SMOOTHING FILTER RDDA RDCL RAM (128bit) RST CLK(4.332MHz) TEST TEST RDS-ID DETECT OSC XIN MODE RDS-ID/ READY XOUT No.A1744-4/9 LC72725KVS Pin Descriptions Pin No. Pin Name I/O 3 VREF Output Function Reference voltage output (VDDa/2) Pin Circuit VDDa VSSa 4 MPXIN Input Baseband (multiplexed) signal input VDDa VSSa 7 FLOUT Output 8 CIN Input Subcarrier output (filter output) Subcarrier input (comparator input) VDDa VSSa VREF 5 VDDa - Analog system power supply (+3V) - 6 VSSa - Analog system ground - 14 XOUT Output 13 XIN Input Crystal oscillator output (4.332MHz) VDDd Crystal oscillator input (external reference signal input) XIN VSSd XOUT 9 TEST Test input 10 MODE Read out mode (0:master, 1:slave) 15 RST 2 RDDA S RDS-ID/RAM reset (active high) Output VSSd RDS data output VDDd VSSd 16 RDCL I/O RDS clock output (master mode) / VDDd RDS read out clock input (slave mode) S 1 RDS-ID/ Output READY VSSd RDS reliability data output (High:data with high RDS reliability Low: data with low RDS reliability) READY output (active high) VSSd 12 VDDd - Digital system power supply (+3V) - 11 VSSd - Digital system ground - No.A1744-5/9 LC72725KVS Input/Output Data Format TEST MODE RDCL Pin RDS-ID/READY Pin 0 0 Master read out mode Circuit Operation Mode Clock output RDS-ID output 0 1 Slave read out mode Clock input READY output 1 0 Standby mode (crystal oscillator stopped) - - 1 1 IC test mode which is not available to user applications. - - RST Pin RST = 0 Normal operation RST = 1 RDS-ID • demodulation circuit clear + READY • memory clear (when slave mode) RDS-ID/READY Pin Master mode RDS-ID output (Active-high) Slave mode READY output (Active-high) Note: RDS-ID(READY) pin is an n-channel open-drain output, and requires an external pull-up resistor to output data. RDCL/RDDA Output Timing in Master Mode 421μs 421μs Tp1 RDCL output RDDA output 17μs Tp21 17μs RDS-ID Output Timing RDS-ID High/Low High/Low High/Low High/Low High/Low High/Low High/Low RDCL RDDA Note: RDS-ID is High: data with high RDS reliability, Low: data with low RDS reliability No.A1744-6/9 LC72725KVS RST Operation in Master Mode Tp3≥250ns RST ≈ ≈≈ RDSdetection circuit output (IC internal) RDCL RDDA Note: RDCL and RDDA outputs keep high level after input of RST until RDS detection circuit output is detected. RDCL Operation in Slave Mode tRH tCS tCH tDC ≈ RDCL tCS ≈≈ ≈ READY tRC tCL RDDA Parameter Symbol Pin Name Ratings Conditions min typ unit max RDCL setup time tCS RDCL,RDDA 0 μs RDCL high-level time tCH RDCL 0.75 μs RDCL low-level time tCL RDCL 0.75 Data output time tDC RDCL,RDDA 0.75 μs READY output time tRC RDCL,READY 0.75 μs READY high-level time tRH READY 107 ms μs No.A1744-7/9 LC72725KVS Notes: 1. RDCL input must be started after READY signal goes high. When READY signal is low, RDCL must be low level. 2. READY status must be checked after tRC time from RDCL is set low. If the READY status is high, then next read cycle can be continued. If the READY status is low, next RDCL clock input must be stopped. 3. If the above condition is satisfied, RDS data (RDDA) can be read out at both rising and falling edge of RDCL. 4. READY signal goes low after the last data is read out from on-chip memory. If one RDS data is stored in the memory, READY signal goes high again. 5. When the reception channel is changed, a memory and READY reset must be applied using RST input. If a reset is not applied, reception data from the previous channel may remain in memory. If RST input is applied, reception data is not stored in memory until the first RDS-ID is detected, and READY output goes high after the first RDS-ID is detected. After the first RDS-ID is detected, reception data is stored even if RDS-ID is not detected. 6. The readout mode may be switched between master and slave modes during readout. Applications must observe the following points to assure data continuity during this operation. 1) Data acquisition timing in master made Data must be read on the falling edge of RDCL 2) Timing of the switch from master mode to slave mode After the RDCL output goes low and the RDDA data has been acquired, the application must set MODE high immediately. Then, the microcontroller starts output by setting the RDCL signal low. The microcontroller RDCL output must start within 840μs (tms) after RDCL went low. In this case, if the last data read in master mode was data item n, then data starting with item n+1 will be written to memory. 3) Timing of the switch from slave mode to master mode After all data has been read from memory and READY has gone high, the application must then wait until READY goes low once again the next time (timing A in the figure), immediately read out one bit of data and input the RDCL clock. Then, at the point READY goes high, the microcontroller must terminate RDCL output and then set MODE low. The application must switch MODE to low within 840μs (tms) after READY goes low (timing A in the figure). RDCL (microcontroller status) RDCL (IC status) INPUT OUTPUT OUTPUT INPUT ≈ ≈≈ ≈ tms INPUT OUTPUT undefined ≈≈ RDCL MODE ts m READY RDDA n-2 n-1 n n+1 ≈≈ ≈ Timing A m m+1 m+2 No.A1744-8/9 LC72725KVS Sample Application Connection Circuit (for master mode operation) VDDd 10kΩ RDSID/READY 1 RDSID/READY 2 RDDA 10μF VSSa + MPXIN 3 RDDA RST VREF XOUT 16 5 15 RST 14 MPXIN XIN VDDa VDDd VSSa VSSd 13 12 0.1μF 6 VSSa 7 560pF RDCL 4.332MHz 4 330pF VDDa RDCL 8 FLOUT CIN MODE TEST VDDd 0.1μF 22pF 22pF VSSd VSSd 11 VSSd 10 9 VSSd Note: If the RST pin is unused, it must be connected to ground. SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of June, 2010. Specifications and information herein are subject to change without notice. PS No.A1744-9/9