LC72725KVS RDS(RBDS) Demodulator IC Application Note

LC72725KVS
Application Note
http://onsemi.com
Overview
The LC72725KVS is ICs that implement the signal processing required by the European Broadcasting Union RDS
(Radio Data System) standard and by the US NRSC (National Radio System Committee) RBDS (Radio Broadcast Data
System) standard. These ICs include band-pass filter, demodulator,and data buffer on chip. RDS data can be read out
from this on-chip memory by external clock input in slave operation mode.
Functions
 Bandpass filter
 RDS Demodulation
 Buffer
 Data output
 RDS-ID
 Standby control
 Fully adjustment free
 Low Voltage
: Switched capacitor filter (SCF)
: 57KHz carrier and RDS data clock regeneration, biphase decode, differential decode.
: 128 bit (about 100ms) can be restored in the on-chip data buffer.
: Master or slave output mode can be selected.
: Detect RDS signal which can be reset by RST signal input.
: Crystal oscillator can be stopped.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing products, if you wish to use any such
products, please be sure to refer the datasheet, which can be obtained upon request.
1
LC72725KVS Application Note
Specifications
Absolute Maximum Ratings at Ta = 25C, VSSd = VSSa = 0V
Parameter
Symbol
Pin Name
Conditions
Ratings
VDD max
VDDd, VDDa
Maximum input voltage
VIN1 max
TEST, MODE, RST
VIN2 max
XIN, RDCL
VIN3 max
MPXIN, CIN
-0.3 to VDDa+0.3
V
VO1 max
RDS-ID(READY)
-0.3 to +6.5
V
VO2 max
XOUT, RDDA, RDCL
-0.3 to VDDd+0.3
V
VO3 max
FLOUT
-0.3 to VDDa+0.3
V
IO1 max
XOUT, FLOUT, RDDA, RDCL
IO2 max
RDS-ID(READY)
Maximum output voltage
Maximum output current
VDDaVDDd+0.3V
Unit
Maximum supply voltage
-0.3 to +6.5
V
-0.3 to +6.5
V
-0.3 to VDDd+0.3
V
+3.0
Allowable power dissipation
Pd max
(Ta85C)
Operating temperature
Topr
VDD = 3.0V to 5.5V
Storage temperature
Tstg
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only.
mA
+20.0
mA
100
mW
-40 to +85
C
-40 to +125
C
Functional operation
above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating
Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +85C, VSSd = VSSa = 0V, VDDd = VDDa = 3.0V to 5.5V
Ratings
Parameter
Symbol
Pin Name
Conditions
unit
min
Supply voltage
VDD
VDDd, VDDa
Input high-level voltage
VIH1
TEST, MODE, RST
VIH2
RDCL
VIL
TEST, MODE, RST,
Input low-level voltage
Ta = -40 to +85C
RDCL
Output voltage
typ
3.0
max
5.5
V
0.7VDDd
6.5
V
0.7VDDd
VDDd
V
0
0.3VDDd
V
VDDd
V
6.5
V
1.6
50
mVrms
400
1500
mVrms
VO1
RDDA, RDCL
VO2
RDS-ID(READY)
VIN
MPXIN
VXIN
XIN
Xtal
XIN, XOUT
CI120
TXtal
XIN, XOUT
Fo = 4.332MHz
RDCL setup time
tCS
RDCL, RDDA
RDCL high-level time
tCH
RDCL low-level time
tCL
Data output time
tDC
RDCL, RDDA
0.75
READY output time
tRC
RDCL, READY
0.75
s
READY low-level time
tRL
READY
107
ms
Input amplitude
Guaranteed crystal
f = 572kHz
4.332
oscillator frequencies
Crystal oscillator operating
MHz
100
range
ppm
0
s
RDCL
0.75
s
RDCL
0.75
2
s
s
LC72725KVS Application Note
Electrical Characteristics at Ta = -40 to +85C, VSSd = VSSa = 0V, VDDd = VDDa = 3.0V to 5.5V
Ratings
Parameter
Symbol
Pin Name
Conditions
unit
min
Internal feedback
Rf
typ
XIN
1.0
resistance
Hysteresis
VHIS
TEST, MODE, RST,
M
0.1VDDd
RDCL
Output low-level voltage
max
V
VOL1
RDDA, RDCL
I = 2mA
0.4
V
VOL2
RDS-ID(READY)
I = 8mA
0.4
V
Output high-level voltage
VOH
RDDA, RDCL
I = -2mA
Input high-level current
IIH1
TEST, MODE, RST,
VI = 6.5V
VDDd-0.54
V
RDCL
Input low-level current
IIH2
XIN
VI = VDDd
IIL1
TEST, MODE, RST,
VI = 0V
2.0
RDCL
IIL2
Output off leakage
XIN
VI = 0V
IOFF
RDS-ID(READY)
VO = 6.5V
IDD
VDDd+VDDa
VDDd+VDDa
2.0
current
Current drain
1.5
(VDDd = VDDa = 3.3V)
2.5
5.0
A
11
A
5.0
A
11
A
5.0
A
3.5
mA
Bandpass Filter Characteristics at Ta = 25C, VSSd = VSSa = 0V, VDDd = VDDa = 3.0V to 5.5V
Ratings
Parameter
Symbol
Pin Name
Conditions
unit
min
Input resistance
Rmpxin
Rcin
typ
max
MPXIN-VSSa
f = 57kHz
100
k
CIN-VSSa
f = 57kHz
100
k
Center frequency
fc
FLOUT
56.5
57.0
57.5
kHz
-3dB band width
BW-3dB
FLOUT
2.5
3.0
3.5
kHz
31
34
dB
Gain
Gain
MPXIN-FLOUT
f = 57kHz
28
Stop band attenuation
Att1
FLOUT
f = 7kHz
30
dB
Att2
FLOUT
f<45kHz, f>70kHz
40
dB
Att3
FLOUT
f<20kHz
50
dB
Vref
Vref
VDDa = 3V
Reference voltage output
3
1.5
V
LC72725KVS Application Note
Package Dimensions
Pin Assignment
6.4
9
LC72725KV
4
5
6
7
8
VSSa
FLOUT
CIN
1.5max
0.1 (1.3)
3
VDDa
0.15
0.22
2
MPXIN
0.65
(0.33)
1
VREF
8
RDDA
1
RDS-ID/READY
0.5
4.4
16 15 14 13 12 11 10
TEST
MODE
VSSd
VDDd
9
XIN
16
XOUT
5.2
RST
RDCL
unit : mm (typ)
3178B
Top view
SANYO : SSOP16(225mil)
Block Diagram
VREF
+3V
FLOUT
CIN
+3V
VDDa
VDDd
PLL
(57kHz)
VSSa
VSSd
VREF
57kHz
BPF
(SCF)
MPXIN
DATA
DECODER
RDDA
RDCL
RAM
(128bit)
RST
CLK(4.332MHz)
TEST
TEST
RDS-ID
DETECT
OSC
XIN
XOUT
4
MODE
RDS-ID/
READY
LC72725KVS Application Note
Pin Descriptions
Pin No.
Pin Name
I/O
3
VREF
Output
Function
Reference voltage output (VDDa/2)
Pin Circuit
VDDa
VSSa
4
MPXIN
Input
Baseband (multiplexed) signal input
VDDa
VSSa
7
FLOUT
Output
8
CIN
Input
Subcarrier output (filter output)
Subcarrier input (comparator input)
VDDa
VSSa
VREF
5
VDDa
-
Analog system power supply (+3V)
-
6
VSSa
-
Analog system ground
-
14
XOUT
Output
13
XIN
Input
Crystal oscillator output (4.332MHz)
VDDd
Crystal oscillator input
(external reference signal input)
XIN
VSSd
XOUT
9
TEST
Test input
10
MODE
Read out mode (0:master, 1:slave)
15
RST
2
RDDA
S
RDS-ID/RAM reset (active high)
Output
VSSd
RDS data output
VDDd
VSSd
16
RDCL
I/O
RDS clock output (master mode) /
VDDd
RDS read out clock input (slave mode)
S
1
RDS-ID/
Output
READY
VSSd
RDS reliability data output
(High:data with high RDS reliability
Low: data with low RDS reliability)
READY output (active high)
VSSd
12
VDDd
-
Digital system power supply (+3V)
-
11
VSSd
-
Digital system ground
-
5
LC72725KVS Application Note
Input/Output Data Format
TEST
MODE
RDCL Pin
RDS-ID/READY Pin
0
0
Master read out mode
Circuit Operation Mode
Clock output
RDS-ID output
0
1
Slave read out mode
Clock input
READY output
1
0
Standby mode (crystal oscillator stopped)
-
-
1
1
IC test mode which is not available to user applications.
-
-
RST Pin
RST = 0
Normal operation
RST = 1
RDS-ID  demodulation circuit clear + READY  memory clear (when slave mode)
RDS-ID/READY Pin
Master mode
RDS-ID output (Active-high)
Slave mode
READY output (Active-high)
Note: RDS-ID(READY) pin is an n-channel open-drain output, and requires an external pull-up resistor to output data.
RDCL/RDDA Output Timing in Master Mode
421s
421s
Tp1
RDCL output
RDDA output
17s Tp21
17s
RDS-ID Output Timing
RDS-ID
High/Low
High/Low
High/Low
High/Low
High/Low
High/Low High/Low
RDCL
RDDA
Note: RDS-ID is High: data with high RDS reliability, Low: data with low RDS reliability
6
LC72725KVS Application Note
RST Operation in Master Mode
Tp3250ns
RST
 
RDSdetection circuit output
(IC internal)
RDCL
RDDA
Note: RDCL and RDDA outputs keep high level after input of RST until RDS detection circuit
output is detected.
RDCL Operation in Slave Mode
tRH
tCS
tCH
tDC

RDCL
tCS
 
READY
tRC
tCL
RDDA
Ratings
Parameter
Symbol
Pin Name
Conditions
unit
min
typ
max
RDCL setup time
tCS
RDCL,RDDA
0
s
RDCL high-level time
tCH
RDCL
0.75
s
RDCL low-level time
tCL
RDCL
0.75
Data output time
tDC
RDCL,RDDA
0.75
s
READY output time
tRC
RDCL,READY
0.75
s
READY high-level time
tRH
READY
107
ms
7
s
LC72725KVS Application Note
Notes: 1. RDCL input must be started after READY signal goes high. When READY signal is low, RDCL must be
low level.
2. READY status must be checked after tRC time from RDCL is set low. If the READY status is high, then next
read cycle can be continued. If the READY status is low, next RDCL clock input must be stopped.
3. If the above condition is satisfied, RDS data (RDDA) can be read out at both rising and falling edge of RDCL.
4. READY signal goes low after the last data is read out from on-chip memory. If one RDS data is stored in the
memory, READY signal goes high again.
5. When the reception channel is changed, a memory and READY reset must be applied using RST input. If a
reset is not applied, reception data from the previous channel may remain in memory. If RST input is applied,
reception data is not stored in memory until the first RDS-ID is detected, and READY output goes high after
the first RDS-ID is detected. After the first RDS-ID is detected, reception data is stored even if RDS-ID is not
detected.
6. The readout mode may be switched between master and slave modes during readout.
Applications must observe the following points to assure data continuity during this operation.
1) Data acquisition timing in master made
Data must be read on the falling edge of RDCL
2) Timing of the switch from master mode to slave mode
After the RDCL output goes low and the RDDA data has been acquired, the application must set MODE
high immediately.
Then, the microcontroller starts output by setting the RDCL signal low.
The microcontroller RDCL output must start within 840s (tms) after RDCL went low.
In this case, if the last data read in master mode was data item n, then data starting with item n+1
will be written to memory.
3) Timing of the switch from slave mode to master mode
After all data has been read from memory and READY has gone high, the application must then wait
until READY goes low once again the next time (timing A in the figure), immediately read out one bit of
data and input the RDCL clock.
Then, at the point READY goes high, the microcontroller must terminate RDCL output and then set
MODE low.
The application must switch MODE to low within 840s (tms) after READY goes low (timing A in the
figure).
RDCL (microcontroller status)
RDCL (IC status)
INPUT
OUTPUT
OUTPUT
INPUT
  
tm s
INPUT
OUTPUT
undefined

RDCL
MODE
tsm
READY
RDDA
n-2
n-1
n
n+1
8


Timing A
m
m+1
m+2
LC72725KVS Application Note
Sample Application Connection Circuit (for master mode operation)
VDDd
10k
RDSID/READY
1
RDSID/READY
2
RDDA
10F
VSSa
+
MPXIN
3
RDDA
RST
VREF
XOUT
16
5
15
RST
14
XIN
MPXIN
VDDa
VDDd
VSSa
VSSd
13
12
0.1F
6
VSSa
7
560pF
RDCL
4.332MHz
4
330pF
VDDa
RDCL
8
MODE
FLOUT
TEST
CIN
VDDd
0.1F
22pF
22pF
VSSd
VSSd
11
VSSd
10
9
VSSd
Note: If the RST pin is unused, it must be connected to the ground.
9
LC72725KVS Application Note
Evaluation board
100mm x 100mm
RDDA: RDS data output
RDCL: RDS clock
Composite signal
Power supply
VDD:3.3V（TYP）
GND:0V
Fig.1 The schematic for LC72725KVS evaluation board
VDDD
RDSID/
READY
RDCL
R2
TP5
TP3
RST
LED
R3
TP6
VDDD
IC1
VSSD
RDDA
TP4
+
1
RDSID/
READY
2
R4
RST
SW1
RDCL
16
RDDA
RST
15
3
VREF
XOUT
14
4
MPXIN
XIN
13
5
VDDA
VDDD
12
6
VSSA
VSSD
11
7
FLOUT
MODE
10
8
CIN
TEST
9
VSSD
C2
MPXIN
C1
VSSA
MPXIN
Xtal
TP10
VDDA
CN1
C3
VDDD
C7
C5
C6
VSSD
VSSD
FLOUT
VSSA
C4
TP9
VSSD
R5
VDDD
MODE
SW2
VSSD
JP1
VDDA
VDDD
VDD
GND
C9
TP7
R1
VDDD
TP2
MODE
TEST
+
SW3
C8
VSSD
VSSD
TEST
TP1
JP2
TP8
VSSA
10
LC72725KVS Application Note
Bill of Materials for LC72725KVS Evaluation Board
signator
Quantity
Description
IC1
1
RDS Demodulator
Value
4.332MHz
(CL=12pF)
Tolerance
±100ppm
Package
(inch)
Manufacturer
Manufacturer Part
Number
Substitution
Allowed
Lead
Free
SSOP16
(225mil)
ON SEMI
LC72725KVS
No
YES
DAISHINKU
AT-49
YES
YES
BNC-LR-PC-3(40)
YES
YES
YES
YES
Xtal
1
Crystal Resonator
CN1
1
BNC connector
HIROSE
ELECTRIC
C1
1
DC coupling
330pF,50V
±5％
MURATA
Supertech
Electronic
C2
1
Decoupling
10μF,16V
±20%
SUN Electoronic
Industries Corp.
16ME10HC
YES
YES
C3
1
Bypass Capacitor
0.1μF,50V
+80/-20%
MURATA
RPEF11H104Z2K1
YES
YES
C4
1
DC coupling
560pF ,50V
±5％
MURATA
RPE2C1H561J2
YES
YES
RPE2C1H220J2
±5％
MURATA
Supertech
Electronic
YES
YES
RD15N220J1HH5L
YES
YES
C5
1
External capacitor
for oscillator
22pF,50V
RPE2C1H331J2
RD15N331J1HL2L
RD15N220J1HH5L
C6
1
External capacitor
for oscillator
22pF,50V
±5％
MURATA
Supertech
Electronic
C7
1
Bypass Capacitor
0.1μF,50V
+80/-20%
MURATA
RPEF11H104Z2K1
YES
YES
C8
1
Bypass Capacitor
0.1μF,50V
+80/20%
MURATA
RPEF11H104Z2K1
YES
YES
16ME100HC
YES
YES
RD16**562J
YES
YES
RD16**122J
YES
YES
RD16**241J
YES
YES
C9
1
Decoupling
100μF,16V
±20%
R1
1
Pull-up /Pull down
Resistor
5.6KΩ,
0.166W
±5%
R2
1
Pull-up Resistor
1.2KΩ,
0.166W
±5%
SUN Electoronic
Industries Corp.
AKAHANE
Electronics
Ind.Corp
AKAHANE
Electronics
Ind.Corp
RPE2C1H220J2
R3
1
for current limiting
240Ω,0.166W
±5%
R4
1
Pull-up /Pull down
Resistor
5.6KΩ,
0.166W
±5%
AKAHANE
Electronics
Ind.Corp
AKAHANE
Electronics
Ind.Corp
RD16**562J
YES
YES
±5%
AKAHANE
Electronics
Ind.Corp
R5
LED
SW1SW4
TP1TP8
5.6KΩ,
0.166W
1
Pull-up /Pull down
Resistor
RD16**562J
YES
YES
1
Indicator for RDSID
Opto Supply
Limited
OSRR3133A
YES
YES
4
Switch
NIHON KAIHEIKI
G-12AP
YES
YES
8
Test Pin
Mac Eight
ST-1-3
YES
YES
11
LC72725KVS Application Note
Fig.2 Illustration of LC72725KVS evaluation board
Made in Japan
SANYO Semiconductor
RDS　Demodulator
LC72725KVS Evaluation Board
VDD
RDS-ID/READY
LED
VSS
TEST
SW3
MODE
VDD
VSS
SW2
VDD
VSS
RST
SW1
RDS-ID/READY
TP3
Composite Signal
CN1
RDDA
TP4
RDDA
RDCL
TP5
RDCL
RST
TP6
MODE
TP7
TEST
TP8
GND
TP1
VDD
TP2
Power Supply
(3.0V～5.5V）
How to use:
1. Connect the power supply to VDD (TP2) and GND (TP1).
(+3.3V to +5.5V)
2. Input composite signals to the BNC connector (CN1).
3. Toggle SW1 (RST) and SW2 (MODE) and SW3 (TEST) to “VSS” side.
4. If the LC72725KVS detects RDS signal in composite signal, RDS-ID output level turns "H". And the LED lights up.
5. Connect RDCL and RDDA with RDS encoder (as shown in Fig.3) to measure error rate.
Appendix
Description of SW1 and SW2 and SW3:
(1)SW3 (TEST)
SW3=VDD: Standby mode is on when MODE (SW2) is switched to “VSS” side (Crystal circuit is stopped.).
SW3=VDD: LSI test mode is on when MODE (SW2) is switched to “VDD” side.
(Basically, customer cannot switch SW2 to VDD side.)
SW3=VSS: Once RDS signal is received, the signal is output from RDCL and RDDA, respectively.
(2)SW2 (MODE)
SW2=VDD: Slave mode is on when TEST is switched to “VSS” side. RDS clock must be input to RDCL
externally. RDS-ID/READY is set to READY output port.
SW2=VSS: Once the RDS signal is received, the signal is output from RDCL and RDDA, respectively.
(3)SW1 (RST)
SW1=VDD: RDS-ID and internal buffer are reset. Once the RDS signal is received, the signal is output from
RDCL and RDDA.
The internal circuit is reset.
SW1=VSS: Once the RDS signal is received, the signal is output from RDCL and RDDA.
12
LC72725KVS Application Note
Fig.3 Bit error rate measurement
Data input
RDS　Encoder
VP-7662A(*)
Output
Pilot input
SCA input
19KHz
CLOCK input
RDDA
RDCL
Stereo Modulator
VP-7636A
LC72725KVS
Evaluation Board
Composite
output
Composite
Signal
EXT INPUT
FM/AM　Signal Generator
VP-8120A
RF output
FM　Tuner LSI
(*)RDS encoder(VP-7662A) is no longer in production. An equivalent model is MEGURO MSG-2174.
Reference data
FM Tuner LSI used LC01707PLF.
The bit error rate of LC72725KVS is as shown below.
LC01707PLF + LC72725KVS Input Level v.s. Bit Error Rate [Vdd=3.3V]
Fin=98.0MHz, L=R,Pilot=10%,Tone=OFF
100
Bit Error Rate [%]
10
1
0.1
0.01
0.001
0
10
20
30
40
50
Input Level [dBuV(EMF)]
13
60
70
LC72725KVS Application Note
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no
warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including“Typicals” must be validated for each customer applicationby customer’s technical experts.
SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other applicationin which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any
such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associatedwith such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the
part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
14