Ordering number : EN6037 CMOS IC LC72723, LC72723M RDS Demodulation IC Overview Package Dimensions The LC72723 is an RDS (Radio Data System) signal demodulation IC. This IC integrates a bandpass filter, the demodulation circuit, and buffer RAM on a single chip and can read out RDS data in slave mode operation with the provision of an external clock input. It also supports master mode, in which the data is read out in synchronization with an RDS clock output provided by the IC itself. unit: mm 3006B-DIP16 [LC72723] 16 0.25 6.4 7.62 9 1 8 Functions 3.0 3.4 0.71 2.54 1.2 0.48 SANYO: DIP16 unit: mm 3035A-MFP16 [LC72723M] 0.625 • Bandpass filter: Switched capacitor filter (SCF) • RDS demodulation: Functions include 57kHz carrier regeneration, clock regeneration, biphase decoding, and differential decoding • Buffer RAM: Stores 128 bits (about 100 ms) of data. • Data output: Output can be switched between master mode and slave mode readout. • RDS ID detection: Supports ID reset • Standby control: Stops the crystal oscillator. • Fully adjustment free. 3.65max 19.2 9 16 1 1.8max 4.4 • Operating supply voltage: 4.5 to 5.5 V • Operating temperature: –40 to 85°C • Packages: DIP16 and MFP16 5.15 6.4 Ratings 8 0.15 0.1 1.5 10.1 0.35 1.27 0.605 SANYO: MFP16 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 40299RM (OT) No. 6037-1/8 LC72723, LC72723M Pin Assignment (DIP16/MFP16) Block Diagram No. 6037-2/8 LC72723, LC72723M Pin Descriptions Pin No. Pin Function I/O Pin circuit type 1 VREF Reference voltage output (Vdda/2) Output 2 MPXIN Base band (multiplex) signal input Input 5 FLOUT Subcarrier output (filter output) 6 CIN Subcarrier input (comparator input) Input 3 Vdda Analog system power supply (+5 V) — — 4 Vssa Analog system ground — — 8 XOUT Crystal element output (4.332 MHz) 9 XIN 7 TEST Test input 12 MODE Readout mode setting (0: master, 1: slave) 13 RST RDS ID and RAM reset (Active high logic) 14 RDDA 15 RDCL 16 RDS-ID/READY 11 Vddd Digital system power supply (+5 V) — — 10 Vssd Digital system ground — — Output Output Crystal element input (or external reference signal input) RDS data output RDS clock output (master mode) RDS clock input (slave mode) RDS ID/ready output (Active low) Input Output I/O Output No. 6037-3/8 LC72723, LC72723M Specifications Absolute Maximum Ratings at Ta = 25°C, Vssd = Vssa = 0 V Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Maximum output current Allowable power dissipation Symbol Conditions VDD max Vddd, Vdda * VIN1 max TEST, MODE, RST VIN2 max Ratings Unit –0.3 to 7.0 V –0.3 to +7.0 V XIN, RDCL –0.3 to Vddd + 0.3 V VIN3 max MPXIN, CIN –0.3 to Vdda + 0.3 V Vo1 max RDS-ID (READY) –0.3 to +7.0 V Vo2 max XOUT, RDDA, RDCL –0.3 to Vddd + 0.3 V Vo3 max FLOUT –0.3 to Vdda + 0.3 V Io1 max XOUT, FLOUT, RDDA, RDCL Io2 max RDS–ID (READY) Pd max +3.0 (Ta ≤ 85°C) mA +20.0 mA DIP16 : 300 mW MFP16 : 140 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C *: Note that Vdda must be less than or equal to Vddd + 0.3 V Allowable Operating Ranges at Ta = –40 to +85°C, Vssd = Vssa = 0 V, Vddd = Vdda Parameter Supply voltage High-level input voltage Low-level input voltage Output voltage Symbol Ratings min typ Unit max VDD Vddd, Vdda: Vddd = Vdda VIH1 TEST, MODE, RST 07 Vddd VIH2 RDCL 0.7 Vddd Vddd V 0 0.3 Vddd V Vddd V VIL TEST, MODE, RST, RDCL Vo1 RDDA, RDCL Vo2 RDS–ID (READY) VIN1 Input amplitude Conditions VIN2 4.5 5.0 f = 57 ±2 KHz MPXIN 100% modulation, composite VXIN XIN Guaranteed oscillator operating range Xtal XIN, XOUT: C1 ≤ 120 Ω Crystal oscillator frequency deviation TXtal tCS RDCL, RDDA RDCL high-level time tCH RDCL low-level time V V 6.5 V 50 mVrms 100 mVrms 400 1500 4.332 XIN, XOUT: Fo = 4.332 MHz RDCL setup time 5.5 6.5 mVrms MHz ±100 ppm 0 µs RDCL 0.75 µs tCL RDCL 0.75 Data output time tDC RDCL, RDDA 0.75 READY output time tRC RDCL, READY 0.75 µs READY low-level time tRL READY 107 ms µs µS No. 6037-4/8 LC72723, LC72723M Electrical Characteristics at Ta = –40 to +85°C, Vssd = Vssa = 0 V, Vddd = Vdda Parameter Symbol Rmpxin Input resistance Rcin Internal feedback resistance Rf Ratings Conditions min typ MPXIN-Vssa: f = 57 KHz Unit max 23 KΩ CIN-Vssa: f = 57 KHz 100 KΩ XIN 1.0 MΩ Center frequency fc FLOUT 56.5 57.0 57.5 KHz –3dB bandwidth BW–3dB FLOUT 2.5 3.0 3.5 KHz Gain MPXIN-FLOUT: f = 57 KHz 28 31 34 dB Att1 FLOUT: ∆f = ±7 KHz 30 dB Att2 FLOUT: f < 45 KHz, f > 70 KHz 40 dB Att3 FLOUT: f < 20 KHz 50 Reference voltage output Vref Vref: Vdda = 5 V Hysteresis VHIS TEST, MODE, RST, RDCL VOL1 RDDA, RDCL : I = 2 mA 0.4 VOL2 RDS-ID (READY): I = 8 mA 0.4 VOH RDDA, RDCL : I = 2 mA IIH1 TEST, MODE, RST, RDCL : VI = 6.5 V IIH2 XIN: VI = Vddd IIL1 TEST, MODE, RST, RDCL : VI = 0 V IIL2 XIN: VI = 0 V Output off leakage current IOFF RDS-ID (READY): VO = 6.5 V Current drain Idd Vddd + Vdda Gain Stop band attenuation Low-level output voltage High-level output voltage High-level input current Low-level input current dB 2.5 V 0.1 Vddd V Vddd – 0.4 V V V 2.0 2.0 5.0 µA 11 µA 5.0 µA 11 µA 5.0 8 µA mA Inputs and Outputs TEST MODE 0 0 Master mode Circuit operating mode Clock output RDCL pin RDS-ID/READY pin RDS-ID output 0 1 Slave mode Clock input READY output 1 0 Standby mode (crystal oscillator stopped) — — 1 1 IC test mode (Cannot be set by users.) — — RST pin RST = 0 Normal operation RST = 1 The RDS-ID and demodulation circuits are cleared, and (in slave mode) the READY state and memory are cleared. RDS ID/READY pin Master mode RDS-ID output (active low) Slave mode Readout data ready output (active low) Note: The RDS-ID (READY) pin is an n-channel open-drain output, and data is read out by connecting a pull-up resistor. No. 6037-5/8 LC72723, LC72723M RDCL/RDDA Output Timing • Master mode RST Operation • Master mode Caution: After an RST input, the RDCL and RDDA outputs stop at the high level until the first RDS ID detection. RDCL Control in Slave Mode Parameter Symbol Conditions Ratings min typ Unit max RDCL setup time tCS RDCL, RDDA 0 µs RDCL high-level time tCH RDCL 0.75 µs RDCL low-level time tCL RDCL 0.75 Data output time tDC RDCL, RDDA 0.75 READY output time tRC RDCL, READY 0.75 µs Ready low-level time tRL READY 107 ms µs µs Notes:1. Start RDCL clock input after the READY signal goes low. Applications must stand by with RDCL held low when the READY pin is high. 2. Each time the RDCL input is switched from low to high to low, the application must check the READY signal level after the period tRC has elapsed once RDCL has been set low. If READY is at the low level, the application may apply the next RDCL clock cycle. If READY is high, the application must stop RDCL input at that point. 3. When the above timing conditions are met, RDDA can be read at either the rise or fall of the RDCL signal. 4. After the last data from memory has been read, READY will be high once the period tRC has elapsed after the fall of the RDCL signal. If even 1 bit of data has been written to memory, READY will be low and the application will be able to read that data. No. 6037-6/8 LC72723, LC72723M 5. When switching channels, it is desirable to immediately reset memory and the READY pin with an RST input. If this is not done, data received on the previous channel may remain in memory. When the IC is reset, data is not written until the RDS-ID is detected, and therefore, the READY signal will go low after the RDS-ID is detected. (Although the RDS-ID is not output in slave mode, it is detected internally in the IC.) After an RST input, once an RDSID has been detected, all received data will be written to memory regardless of the RDS-ID detection state. 6. The readout mode may be switched between master and slave modes during readout. Applications must observe the following points to assure data continuity during this operation. • Data acquisition timing in master mode Data must be read on the falling edge of RDCL. • Timing of the switch from master mode to slave mode After the RDCL output goes low and the RDDA data has been acquired, the application must set MODE high immediately. Then, the microcontroller starts output by setting the RDCL signal low. The microcontroller RDCL output must start within 840 µs (tms) after RDCL went low. In this case, if the last data read in master mode was data item n, then data starting with item n+1 will be written to memory. • Timing of the switch from slave mode to master mode After all data has been read from memory and READY has gone high, the application must then wait until READY goes low once again the next time (timing A in the figure), immediately read out one bit of data and input the RDCL clock. Then, at the point READY goes high, the microcontroller must terminate RDCL output and then set MODE low. The application must switch MODE to low within 840 µs (tms) after READY goes low (timing A in the figure). RDCL (microcontroller status) RDCL (IC status) No. 6037-7/8 LC72723, LC72723M LC72723 Sample Application Connection Circuit (for slave mode operation) Caution: If the RST pin is unused, it must be connected to ground. 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Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of April, 1999. Specifications and information herein are subject to change without notice. PS No. 6037-8/8