Ordering number : ENN6488 CMOS IC LC72720Y, 72720YV Single-Chip RDS Signal-Processing System IC Overview Features The LC72720Y and LC72720YV are single-chip system ICs that implement the signal processing required by the European Broadcasting Union RDS (Radio Data System) standard and by the US NRSC (National Radio System Committee) RDBS (Radio Broadcast Data System) standard. These ICs include band-pass filter, demodulator, synchronization, and error correction circuits as well as data buffer RAM on chip and perform effective error correction using a soft-decision error correction technique. • Error correction capability improved by soft-decision error correction. • The load on the control microprocessor can be reduced by storing decoded data in the on-chip data buffer RAM. • Two synchronization detection circuits provide continuous and stable detection of the synchronization timing. • Data can be read out starting with the backwardprotection block data after a synchronization reset. • Fully adjustment free. • Low voltage (supply voltage: 3.0 V min) type. • Operating power-supply voltage: 3.0 to 3.6 V • Operating temperature: –40 to +85°C • Package: DIP24S, SSOP30 Functions • Band-pass filter: Switched capacitor filter (SCF) • Demodulator: RDS data clock regeneration and demodulated data reliability information • Synchronization: Block synchronization detection (with variable backward and forward protection conditions) • Error correction: Soft-decision/hard-decision error correction • Buffer RAM: Adequate for 24 blocks of data (about 500 ms) and flag memory • Data I/O: CCB interface (power on reset) • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 42800TN (OT) No. 6488-1/14 LC72720Y, 72720YV Package Dimensions unit: mm unit: mm 3067A-DIP24S 3191A-SSOP30 [LC72720Y] [LC72720YV] 21.0 30 24 16 7.6 5.6 0.5 1 0.25 7.62 6.4 13 12 0.48 1.78 9.75 0.15 0.1 (3.25) 0.51min (0.71) 15 3.3 3.9max 1 (1.3) 1.5max 0.9 0.22 0.95 0.65 (0.33) SANYO: SSOP30 SANYO: DIP24S Pin Assignment VREF 1 24 SYR MPXIN 2 VREF 1 23 CE 30 SYR MPXIN 2 29 CE Vdda 3 22 DI Vdda 3 Vssa 4 21 CL NC 4 27 NC FLOUT 5 20 DO Vssa 5 26 CL FLOUT 6 25 DO 19 RDS-ID CIN 6 T1 7 LC72720Y 28 DI 18 SYNC CIN 7 17 T7(CORREC/ARI-ID/BEO) NC 8 T3(RDCL) 9 16 T6(ERROR/57K/BE1) T1 9 22 SYNC T4(RDDA) 10 15 Vssd T2 10 21 T7(CORREC/ARI-ID/BEO) T5(RSFT) 11 14 Vddd T3(RDCL) 11 T2 8 XOUT 12 24 RDS-ID LC72720YV 23 NC 20 T6(ERROR/57K/BE1) NC 12 13 XIN Top view A13195 19 NC T4(RDDA) 13 18 Vssd T5(RSFT) 14 17 Vddd XOUT 15 16 XIN Top view A13196 Block Diagram VREF +3.3V FLOUT + REFERENCE VOLTAGE – Vssa MPXIN +3.3V CIN Vdda Vddd PLL (57kHz) CLOCK RECOVERY (1187.5Hz) Vssd VREF ANTIALIASING FILTER DO CL DI CE CCB T1 T2 T3 to T7 TEST 57kHz BPF (SCF) SMOOTHING FILTER RAM (24 BLOCK DATA) MEMORY CONTROL DATA DECODER ERROR CORRECTION (SOFT DECISION) SYNC/EC CONTROLLER RDS-ID SYNC SYR CLK(4.332MHz) OSC/DIVIDER XIN SYNC DETECT-1 SYNC DETECT-2 XOUT A13197 No. 6488-2/14 LC72720Y, 72720YV Pin Functions Pin No. Pin name Function I/O Pin circuit Vdda 1 VREF Reference voltage output (Vdda/2) Output Vssa A13198 Vdda 2 MPXIN Baseband (multiplexed) signal input Input Vssa 5/6 FLOUT Subcarrier output (filter output) A13199 – Output + A13200 Vdda 6/7 CIN Subcarrier input (comparator input) + Input – Vssa VREF 3 Vdda Analog system power supply (+3.3 V) — — 4/5 Vssa Analog system ground — — 12 / 15 XOUT Crystal oscillator output (4.332/8.664 MHz) 13 / 16 XIN A13201 Vddd Output XIN XOUT Crystal oscillator input (external reference signal input) Vssd A13202 7/9 8 / 10 T1 Test input (This pin must always be connected to ground.) T2 Test input (standby control) 0: Normal operation, 1: Standby state (crystal oscillator stopped) 9 / 11 T3 (RDCL) Test I/O (RDS clock output) 10 / 13 T4 (RDDA) Test I/O (RDS data output) 11 / 14 T5 (RSFT) 16 / 20 17 / 21 T6 (ERROR/57K/BE1) T7 (CORREC/ARI-ID/BE0) Input S Vssd A13203 Test I/O (soft-decision control data output) Test I/O (error status output, regenerated carrier output, error block count output) I/O* Vssd A13204 Test I/O (Error correction status output, SK detection output, error block count output) 18 / 22 SYNC 19 / 24 RDS-ID Block synchronization detection output 20 / 25 DO Data output 21 / 26 CL Clock input 22 / 28 DI Data input 23 / 29 CE Chip enable 24 / 30 SYR 14 / 17 Vddd Digital system power supply (+3.3 V) — — 15 / 18 Vssd Digital system ground — — RDS detection output Output Serial data interface (CCB) Input Vssd A13205 S Vssd Synchronization and RAM address reset (active high) A13206 Note: * Normally function as an output pin. Used as an I/O pin in test mode, which is not available to user applications. Pins 4, 8, 12, 19, 23, 27 are NC (NO CONNECT) Pins for the SSOP package version. No. 6488-3/14 LC72720Y, 72720YV Specifications Absolute Maximum Ratings at Ta = 25°C, Vssd = Vssa = 0 V Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Maximum output current Allowable power dissipation Symbol Conditions Ratings Unit VDD max Vddd, Vdda –0.3 to +7.0 VIN1 max CL, DI, CE, SYR, T1, T2, T3, T4, T5, T6, T7, SYNC –0.3 to +7.0 V V VIN2 max XIN –0.3 to Vddd +0.3 V VIN3 max MPXIN, CIN –0.3 to Vdda +0.3 V VO1 max DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 VO2 max –0.3 to +7.0 V XOUT –0.3 to Vddd +0.3 V VO3 max FLOUT –0.3 to Vdda +0.3 IO1 max DO, T3, T4, T5, T6, T7 6.0 V mA IO2 max XOUT, FLOUT 3.0 mA IO3 max SYNC, RDS-ID 20.0 mA Ta ≤ 85°C DIP24S: 350 mW Pd max SSOP30: 150 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Allowable Operating Ranges at Ta = –40 to +85°C, Vssd = Vssa = 0 V Parameter Supply voltage Symbol Conditions Ratings min typ VDD1 Vddd, Vdda 3.0 VDD2 Vddd: Serial data hold voltage 2.0 max 3.6 Unit V V Input high-level voltage VIH CL, DI, CE, SYR, T1, T2 0.7 Vddd 6.5 V Input low-level voltage VIL CL, DI, CE, SYR, T1, T2 0 0.3 Vddd V Output voltage DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 6.5 V VIN1 MPXIN : f = 57 ±2 kHz 50 mVrms VIN2 MPXIN : 100% modulation composite 100 VXIN XIN 400 1500 mVrms VO Input amplitude Guaranteed crystal oscillator frequencies Crystal oscillator frequency deviation Xtal TXtal mVrms XIN, XOUT : CI ≤ 120 Ω (XS = 0) 4.332 MHz XIN, XOUT : CI ≤ 70 Ω (XS = 1) 8.664 MHz XIN, XOUT : fO = 4.332 MHz, 8.664 MHz ±100 ppm Data setup time tSU DI, CL 0.75 Data hold time tHD DI, CL 0.75 μs μs Clock low-level time tCL CL 0.75 μs Clock high-level time tCH CL 0.75 μs CE wait time tEL CE, CL 0.75 μs CE setup time tES CE, CL 0.75 μs CE hold time tEH CE, CL 0.75 CE high-level time tCE CE Data latch change time tLC μs 20 ms 1.15 μs tDC DO, CL: Differs depending on the value of the pull-up resistor used. 0.46 μs tDH DO, CE: Differs depending on the value of the pull-up resistor used. 0.46 μs Data output time Electrical Characteristics at Ta = –40 to +85°C, Vssd = Vssa = 0 V Parameter Input resistance Internal feedback resistance Center frequency –3 dB bandwidth Gain Stop band attenuation Symbol Rmpxin Conditions Ratings min typ max Unit MPXIN–Vssa : f = 57 kHz 23 kΩ Rf XIN 1.5 MΩ fc FLOUT 56.5 57.0 57.5 kHz BW – 3 dB FLOUT 2.5 3.0 3.5 kHz 31 34 Gain MPXIN–FLOOUT : f = 57 kHz 28 Att1 FLOUT : Δf = ±7 kHz 30 dB dB Att2 FLOUT : f < 45 kHz, f > 70 kHz 40 dB Att3 FLOUT : f < 20 kHz 50 dB Continued on next page. No. 6488-4/14 LC72720Y, 72720YV Continued from preceding page. Parameter Symbol Group delay deviation G-Delay Conditions Ratings min typ max FLOUT: f = 57 ± 1.2 kHz ± 2.0 Unit μs Reference voltage output Vref VREF : Vdda = 3.3 V Hysteresis VHIS CL, DI, CE, SYR, T1, T2 VOL1 DO, T3, T4, T5, T6, T7 : I = 2 mA 0.5 V VOL2 SYNC, RDS-ID : I = 8 mA 0.5 V 5.0 μA Output low-level voltage Input high-level current Input low-level current IIH1 CL, DI, CE, SYR, T1, T2 : VI = Vddd IIH2 XIN : VI = Vddd IIL1 CL, DI, CE, SYR, T1, T2 : VI = 0 V 1.65 V 0.1 Vddd V 0.9 IIL2 XIN : VI = 0 V Output off leakage current IOFF DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 : VO = 6.5 V 0.9 Current drain IDD Vddd + Vdda, Vddd = Vdda = 3.3 V 6 4.0 μA 5.0 μA 4.0 μA 5.0 μA mA CCB Output Data Format • Each block of output data consists of 32 bits (4 bytes), of which 2 bytes are RDS data and 2 bytes are flag data. • Any number of 32-bit output data blocks can be output consecutively. • When there is no data that can be read out in the internal memory, the system outputs blocks of all-zero data consecutively. • If data readout is interrupted, the next read operation starts with the 32-bit data block whose readout was interrupted. However, if only the last bit is remaining to be read, it will not be possible to reread that whole block. • The check bits (10 bits) are not output. • The data valid / invalid decision is made by referencing the error information flag (E0 to E2) but the offset word detection flag (OWD) must not be referred to. • When the first leading bits are not “1010”, the read in data is invalid, and the read operation is cancelled. CCB address 6C B0 B1 B2 B3 A0 A1 A2 A3 DI 0 0 1 1 0 1 1 0 Output data/first bit DO 1 0 1 Last bit 0 OWD B2 B1 B0 RE RF1 RF0 ARI SYC E2 E1 E0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (8) RDS data (7) Error information flags (6) Synchronization established flag (5) ARI (SK) detection flag (4) RAM data remaining flags (3) Consecutive RAM read out possible flag (2) Offset word information flags (1) Offset word detection flag Fixed pattern (1010) A13207 (1) Offset word detection flag (1 bit): OWD OWD Offset word detection 1 Detected 0 Not detected (protection function operating) No. 6488-5/14 LC72720Y, 72720YV (2) Offset word information flag (3 bits): B0 to B2 B B B 2 1 0 Offset word 0 0 0 0 0 1 A B 0 1 0 C 0 1 1 C’ 1 0 0 D 1 0 1 E 1 1 0 Unused 1 1 1 Unused (3) Consecutive RAM readout possible flag (1 bit): RE RE RAM data information 1 The next data to be read out is in RAM. 0 This data item is the last item in RAM, and the next data is not present. (4) RAM data remaining flag (2 bits): RF0, RF1 RF1 RF0 0 0 Remaining data in RAM (number of blocks) 1 to 7 0 1 8 to 15 1 0 16 to 23 1 1 24 Caution: This value is only meaningful when RE is 1. When RE is 0, there is no data in RAM, even if RF is 0. If a synchronization reset was applied using SYR, then the backward protection block data that was written to memory is also counted in this value. (5) ARI (SK) detection flag (1 bit): ARI ARI SK signal 1 Detected 0 Not detected (6) Synchronization established flag (1 bit): SYC SYC Synchronization detection 1 Synchronized 0 Not synchronized Caution: This flag indicates the synchronization state of the circuit at the point where the data block being output was received. On the other hand, the SYNC pin (pin 18 / 22) output indicates the current synchronization state of the circuit. (7) Error information flags (3 bits): E0 to E2 E E E 2 1 0 Number of bits corrected 0 0 0 0 (no errors) 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 Correction not possible 1 1 1 Unused Caution: If the number of errors exceeds the value of the EC0 to EC2 setting (see the section on the CCB input format), the error information flags will be set to the “Correction not possible” value. When the error flags EC0 to EC2 are 011 (indicating that correction is not possible) the data must be handled as invalid data. (8) RDS data (16 bits): D0 to D15 This data is output with the MSB first and the LSB last. Caution: When error correction was not possible, the input data is output without change. No. 6488-6/14 LC72720Y, 72720YV CCB Input Data Format [1] CCB address 6A IN1 data, first bit B0 B1 B2 B3 A0 A1 A2 A3 FS0FS1FS2FS3 BS SYR DI * OWEEC0 EC1 EC2 * EC3 EC4 CT0 * 0 1 0 1 0 1 1 0 (11) Circuit control (5) Error correction method setting (4) RAM write control (3) Synchronization and RAM address reset (2) Synchronization detection method setting (1) Synchronization protection method setting A13208 [2] CCB address 6B IN2 data, first bit B0 B1 B2 B3 A0 A1 A2 A3 CT1 DI * * * XS PL0 PL1 RM PT0 PT1 PT2 * TS0 TS1 TS2 TS3 1 1 0 1 0 1 1 0 (10) Test mode settings (9) Output pin settings (8) RDS/RBDS selection (7) Demodulation circuit phase control (6) Crystal oscillator frequency selection (11) Circuit control A13209 Caution: The bits labeled with an asterisk must be set to 0. (1) Synchronization protection (forward protection) method setting (4 bits): FS0 to FS3 FS3 = 0: If offset words in the correct order could not be detected continuously during the number of blocks specified by FS0 to FS2, take that to be a lost synchronization state. FS3 = 1: If blocks with uncorrectable errors were received consecutively during the number of blocks specified by FS0 to FS2, take that to be a lost synchronization state. F F F S S S 0 1 2 Condition for detecting lost synchronization 0 0 0 If 3 consecutive blocks matching the FS3 condition are received. 1 0 0 If 4 consecutive blocks matching the FS3 condition are received. 0 1 0 If 5 consecutive blocks matching the FS3 condition are received. 1 1 0 If 6 consecutive blocks matching the FS3 condition are received. 0 0 1 If 8 consecutive blocks matching the FS3 condition are received. 1 0 1 If 10 consecutive blocks matching the FS3 condition are received. 0 1 1 If 12 consecutive blocks matching the FS3 condition are received. 1 1 1 If 16 consecutive blocks matching the FS3 condition are received. Initial value: FS0 = 0, FS1 = 1, FS2 = 0, FS3 = 0 (2) Synchronization detection method setting (1 bit): BS BS Synchronization detection conditions 0 If during 3 blocks, 2 blocks of offset words were detected in the correct order. 1 If the offset words were detected in the correct order in 2 consecutive blocks. Initial value: BS = 0 No. 6488-7/14 LC72720Y, 72720YV (3) Synchronization and RAM address reset (1 bit): SYR SYR Synchronization detection circuit RAM 0 Normal operation (reset cleared) Normal write (See the description of the OWE bit.) 1 Forced to the unsynchronized state (synchronization reset) After the reset is cleared, start writing from the data prior to the establishment of synchronization, i.e. the data in backward protection. Initial value: SYR =0 Caution: 1. To apply a synchronization reset, set SYR to 1 temporarily using the CCB, and then set it back to 0 again using the CCB. The circuit will start synchronization capture operation at the point SYR is set to 0. 2. The SYR pin (pin 24 / 30) also provides an identical reset control operation. Applications can use either method. However, the control method that is not used must be set to 0 at all times. Any pulse with a width of over 250 ns will suffice. 3. A reset must be applied immediately after the reception channel is changed. If a reset is not applied, reception data from the previous channel may remain in memory. 4. Data read out after a synchronization reset is read out starting with the backward protection block data preceding the establishment of synchronization. (4) RAM write control (1 bit): OWE OWE RAM write conditions 0 Only data for which synchronization had been established is written. 1 Data for which synchronization not has been established (unsynchronized data) is also written. (However, this applies when SYR = 0.) Initial value: OWE = 0 (5) Error correction method setting (5 bits): EC0 to EC4 E E E C C C 0 1 2 Number of bits corrected E E C C 3 4 Soft-decision setting 0 0 0 0 (error detection only) 0 0 Mode 0: Hard decision 1 0 0 1 or fewer bits 1 0 Mode 1: Soft decision A 0 1 0 2 or fewer bits 0 1 Mode 2: Soft decision B 1 1 0 3 or fewer bits 1 1 Illegal value 0 0 1 4 or fewer bits 1 0 1 5 or fewer bits 0 1 1 Illegal value 1 1 1 Illegal value Initial values: EC0 = 0, EC1 = 1, EC2 = 0, EC3 = 0, EC4 = 1 Caution: 1. If soft-decision A or soft-decision B is specified, soft-decision control will be performed even if the number of bits corrected is set to 0 (error detection only). With these settings, data will be output for blocks with no errors. 2. As opposed to soft-decision B, the soft-decision A setting suppresses soft decision error correction. (6) Crystal oscillator frequency selection (1 bit): XS XS = 0: 4.332 MHz XS = 1: 8.664 MHz Initial value: XS = 0 (7) Demodulation circuit phase control (2 bits): PL0, PL1 PL0 PL1 Demodulation circuit phase control 0 0/1 <Normal operation> when ARI presence or absence is unclear. 0 If the circuit determines that the ARI signal is absent: 90° phase 1 If the circuit determines that the ARI signal is present: 0° phase 1 Initial values: PL0 = 0, PL1 = 1 Caution: 1. When PL0 is 0 (normal operation), the IC detects the presence or absence of the ARI signal and reproduces the RDS data by automatically controlling the demodulation phase with respect to the reproduced carrier. However, the initial phase following a synchronization reset is set by PL1. 2. If PL0 is set to 1, the demodulation circuit phase is locked according to the PL1 setting at either 90° (PL1 = 0) or 0° (PL1 = 1), allowing RDS data to be reproduced. When ARI is not present, PL1 should be set to 0, since the RDS data is reproduced by detecting at a phase of 90° with respect to the reproduced carrier. When ARI is present, PL1 should be set to 1, since detection is at 0°. In cases where the ARI presence is known in advance, more stable reproduction can be achieved by fixing the demodulation phase in this manner. No. 6488-8/14 LC72720Y, 72720YV (8) RDS/RBDS (MMBS) selection (1 bit): RM RM RBDS support 0 None 1 Provided Decoding method Only RDS data is decoded correctly (Offset word E is not detected.) RDS and MMBS data is decoded correctly (Offset word E is also detected.) Initial value: RM = 0 (9) Output pin settings (3 bits): PT0 to PT2 These bits control the T3, T4, T5, T6, T7, SYNC, and RDS-ID pins. P P P T T3 T4 T5 2 RDCL RDDA RSFT ERROR 57K BE1 CORREC ARI-ID 0 — — — — — — — — — ● ● ● — — — — — — Mode T T 0 1 0 0 0 1 1 0 0 T6 T7 BE0 2 0 1 0 ● ● ● — ● — — ● — 3 1 1 0 ● ● ● ● — — ● — — 4 0 0 1 — — — — — ● — — ● 5 1 0 1 ● ● ● — — — — — — 6 0 1 1 ● ● ● — ● — — ● — 7 1 1 1 ● ● ● ● — — ● — — —: Open, ●, ●: Output enabled (● = reverse polarity) Initial values: PT0 = 1, PT1 = 1, PT2 = 0 (mode 3) Caution: 1. When PT2 is set to 1, the polarity of the T3 (RDCL), T6 (ERROR/57K), T7 (CORREC/ARI-ID) SYNC, and RDS-ID pins changes to active high. 2. The output pins (T3 to T7, SYNC, and RDS-ID) are all open-drain pins, and require external pull-up resistors to output data. Item Pin T3 (RDCL) PT2 = 0 Data (RDDA and RSFT) changes on this pin’s rising edge. PT2 = 1 Data (RDDA and RSFT) changes on this pin’s falling edge. Mode 2 (PT2 = 0) Pin T7 (ARI-ID) No SK High (1) SK present Low (0) Mode 3 (PT2 = 0) Pin T6 (ERROR) Pin T7 (CORREC) Correction not possible Low (0) Low (0) Errors corrected High (1) Low (0) No errors High (1) High (1) Pin T6 (BE1) Pin T7 (BE0) Mode 4 Number of error blocks (B) B=0 Low (0) Low (0) 1 ≤ B ≤ 20 Low (0) High (1) 20 < B ≤ 40 High (1) Low (0) 40 < B ≤ 48 High (1) High (1) These pins indicate the number of blocks in a set of 48 blocks that had errors before correction. The output polarity of these pins is fixed at the values listed in the table. No. 6488-9/14 LC72720Y, 72720YV Mode (PT2 = 0) The SYNC pin 0 to 2 When synchronized: Low (0). When unsynchronized: High (1) 3 When synchronized: Goes high for a fixed period (421 μs) at the start of a block and then goes low. When unsynchronized: High (1) Caution: The output indicates the synchronization state for the previous block. When PT2 = 0 The RDS-ID pin No RDS High (1) RDS present Low (0) (10) Test mode settings (4 bits): TS0 to TS3 Initial values: TS0 = 0, TS1 = 0, TS2 = 0, TS3 = 0 (Applications must set these bits to the above values.) Notes: The T1 and T2 pins (pins 7 and 8) are related to test mode as follows: Pin T1 Pin T2 IC operation 0 0 Normal operating mode Notes 0 1 Standby mode (crystal oscillator stopped) 1 0/1 IC test mode These states are user settable Users cannot use this state The T1 pin must be tied to VSS (0 V). (11) Circuit control (2 bits): CT0 and CT1 Item Control CT0 RSFT control CT1 RDS-ID detection condition When set to 1, soft-decision control data (RSFT) is easier to generate. When set to 1, the RDS-ID detection conditions are made more restrictive. Initial values: CT0 = 0, CT1 = 0 RDCL/RDDA/RSFT and ERROR/CORREC/SYNC Output Timing Timing 1 (modes 1 to 3, PT2 = 0) 421μs 421μs 421μs Tp1 RDCL output RDDA output Note: When PT2 = 0, RDDA and RSFT must be aquired on the falling edge of RDCL. RSFT output 842μs A13210 Error crrection SYNC output Sync NG Sync OK Sync OK Sync OK Sync OK Data corrected No errors No errors Data corrected Tp1 Tp1 Sync OK Sync NG Uncorrectable Input data Uncorrectable Timing 2 (mode 3, PT2 = 0) Sync NG ERROR output CORREC output A13211 No. 6488-10/14 LC72720Y, 72720YV Serial Data Input and Output Methods Data is input and output using the CCB (computer control bus), which is the Sanyo audio IC serial bus format. This IC adopts an 8-bit address CCB format. (LSB) I/O mode Address (MSB) B0 B1 B2 B3 A0 A1 A2 A3 Comment 1 IN1 (6A) 0 1 0 1 0 1 1 0 · Control data input mode, also referred to as “serial data input” mode. · This is a 16-bit data input mode. 2 IN2 (6B) 1 1 0 1 0 1 1 0 · Control data input mode, also referred to as “serial data input” mode. · This is a 16-bit data input mode. 3 OUT (6C) 0 0 1 1 0 1 1 0 · Data output mode, also referred to as “serial data output” mode. · The data for multiple blocks can be output sequentially in this mode. I/O mode determined CE 1 CL 2 B0 DI B1 B2 B3 A0 A1 A2 A3 First Data IN1/2 1 First Data OUT DO 2 First Data OUT ➀ For the CL normal high state ➁ For the CL normal low state A13212 Serial data input (IN1, IN2) tSU, tHD, tEL, tES, tEH ≥ 0.75 μs tLC < 1.15μs tCE < 20 ms CL: Normal high tEL tCE tES tEH CE CL tSU tHD B0 DI B1 B2 B3 A0 A1 A2 A3 FS0 CT1 FS1 0 FS2 0 FS3 0 EC3 TS0 EC4 TS1 CT0 TS2 0 TS3 tLC Internal data A13213 CL: Normal low tEL tCE tES tEH CE CL tSU DI tHD B0 B1 B2 B3 A0 A1 A2 A3 FS0 CT1 FS1 0 FS2 0 FS3 0 EC3 TS0 EC4 TS1 CT0 TS2 0 TS3 tLC Internal data A13214 No. 6488-11/14 LC72720Y, 72720YV Serial data output (OUT) tSU, tHD, tEL, tES, tEH ≥ 0.75 μs tDC, tDH < 0.46 μs tCE < 20 ms CL: Normal high tEL tCE tES tEH CE CL tSU tHD B0 DI B1 B2 B3 A0 A1 A2 A3 tDC tDC 1 DO 0 tDH 1 0 D3 D2 D1 D0 A13215 CL: Normal low tEL tCE tES tEH CE CL tSU tHD B0 DI B1 B2 B3 A0 A1 A2 A3 tDC tDH tDC 1 DO 0 1 0 D3 D2 D1 D0 A13216 Caution: 1. Since the DO pin is an n-channel open-drain output, the transition times (tDC, tDH) will differ according to the value of the pull-up resistor used. 2. The CE, CL, DI, and DO pins can be connected to the corresponding pins on other ICs that use the CCB interface. (However, we recommend connecting the DO and CE pins separately if the number of available microcontroller ports allows it.) 3. Serial data I/O becomes possible after the crystal oscillator starts oscillation. Serial data timing CL: Normal high tCE VIH CE tCL CL VIL tCH VIH VIL tEL VIH VIL DI VIH VIL VIH tES tEH VIH VIL tSU tHD tDC tDH DO tLC Intenal data latch New Old A13217 CL: Normal low tCE VIH CE tCH CL VIH VIL VIH VIL VIL tEL DI VIH VIL tSU VIL tCL VIL tEH tES VIH VIL tHD tDC tDC tDH DO tLC Intenal data latch Old New A13218 No. 6488-12/14 LC72720Y, 72720YV Parameter Symbol Ratings Conditions min typ max Unit Data setup time tSU DI, CL 0.75 Data hold time tHD DI, CL 0.75 μs Clock low-level time tCL CL 0.75 μs Clock high-level time tCH CL 0.75 μs CE wait time tEL CE, CL 0.75 μs CE setup time tES CE, CL 0.75 μs CE hold time tEH CE, CL 0.75 CE high-level time tCE CE Data latch transition time tLC Data output time tDC DO, CL tDH DO, CE Differs with the value of the pull-up resistor used. μs μs 20 ms 1.15 μs 0.46 μs 0.46 μs DO pin operation This IC incorporates a RAM data buffer that can hold up to 24 blocks of data. At the point where one block of data is written to this RAM, the IC issues a read request by switching the DO pin from high to low. The DO pin always goes high for a fixed period (Tdo = 265 μs) after a readout and CE goes low. When all the data in the data buffer has been read out, the DO pin is held in the high state until a new block of data has been written to the RAM. If there is data that has not yet been read remaining in the data buffer, the DO pin goes low after the Tdo time has elapsed. After a synchronization reset, the DO pin is held high until synchronization is established. It goes low at the point where the IC synchronizes. 1. When the DO pin is high following the 265 μs period (Tdo) after data is read out Here, the buffer is in the empty state, i.e. the state where new data has not been written. After this, when the DO pin goes low, applications are guaranteed to be able to read out that data without it being overwritten by new data if they start a readout operation within 480 ms of DO going low. Tdo CE pin T DO pin (Last data) - 1 Last data New data A13219 DO check (Tdo < T) 2. When DO goes low 265 μs after data is read out Here, there is data that has not been read out remaining in the data buffer. In this case, applications are guaranteed to be able to read out that data without it being overwritten by new data if they start a readout operation within 20 ms of DO going low. (Note that this is the worst case condition.) Tdo CE pin T DO pin (Last data) - 2 Last data (Last data) - 1 A13220 DO check (Tdo < T) Notes: 1. Although an application can determine whether or not there is data remaining in the buffer by checking the DO level with the above timing, checking the RE and RF flags in the serial data is a preferable method. 2. Applications are not limited to reading out one block of data at a time, but rather can read out multiple blocks of data continuously as described above. When using this method, if an application references the RE and RF flags in the data while reading out data, it can determine the amount of data remaining. However, the length of the period for data readout (the period the CE pin remains high) must be kept under 20 ms. 3. If the DO pin is shared with other ICs that use the CCB interface, the application must identify which IC issued the readout request. One method is to read out data from the LC72720Y and either check whether meaningful data has been read (if the LC72720Y is not requesting a read, data consisting of all zeros will be read out) or check whether the DO level goes low within the 265 μs following the completion of the read (if the DO pin goes low, then the request was from another IC). No. 6488-13/14 LC72720Y, 72720YV Sample Application Circuit (LC72720Y) 1 10μF + Vssa 2 MPXIN 330pF Vdda 0.1μF 3 4 Vssa 5 560pF 100kΩ 6 7 8 Vssd NC NC NC 9 10 11 12 16pF Vssd VREF SYR MPXIN CE Vdda DI Vssa CL FLOUT CIN DO RDS-ID T1 SYNC T2 T7 T3 T6 T4 Vssd Vddd T5 XOUT XIN 24 SYR 23 Vssd CE 22 DI 21 20 19 18 17 16 DO RDS-ID SYNC NC NC 15 14 CL Vddd 10kΩ Vddd 10kΩ Vddd 10kΩ Vssd 0.1μF Vddd 13 4.332MHz 16pF Vssd A13221 Notes: 1. Determine the value of the DO pin pull-up resistor based on the required serial data transfer speed. 2. A 100-kΩ bias resistor must be connected between the CIN pin and the VREF pin. 3. If the SYR pin is unused, it must be connected to ground. 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Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of April, 2000. Specifications and information herein are subject to change without notice. PS No. 6488-14/14