CYPRESS CY62177DV30_12

CY62177DV30 MoBL®
32-Mbit (2 M × 16) Static RAM
Features
applications such as cellular telephones.The device also has an
automatic power-down feature that significantly reduces power
consumption. The device can also be put into standby mode
when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE
are HIGH). The input/output pins (I/O0 through I/O15) are placed
in a high-impedance state when: deselected (CE1HIGH or CE2
LOW), outputs are disabled (OE HIGH), both Byte High Enable
and Byte Low Enable are disabled (BHE, BLE HIGH), or during
a write operation (CE1 LOW, CE2 HIGH and WE LOW).
■
Very high speed: 55 ns
■
Wide voltage range: 2.20 V–3.60 V
■
Ultra-low active power
❐ Typical active current: 2 mA at f = 1 MHz
❐ Typical active current: 15 mA at f = fmax
■
Ultra low standby power
■
Easy memory expansion with CE1, CE2 and OE features
■
Automatic power-down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
■
Packages offered in a 48-ball fine ball grid array (FBGA)
Writing to the device is accomplished by taking Chip Enables
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If
Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the address
pins (A0 through A20). If Byte High Enable (BHE) is LOW, then
data from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A20).
Reading from the device is accomplished by taking Chip Enables
(CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while
forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)
is LOW, then data from the memory location specified by the
address pins will appear on I/O0 to I/O7. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O8 to
I/O15. See the truth table for a complete description of read and
write modes.
Functional Description
The CY62177DV30 is a high-performance CMOS static RAM
organized as 2M words by 16 bits. This device features
advanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life (MoBL®) in portable
Logic Block Diagram
2048K × 16
RAM Array
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA-IN DRIVERS
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
BHE
WE
OE
CE2
CE1
BLE
Power-down
Circuit
Cypress Semiconductor Corporation
Document Number : 38-05633 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 20, 2012
CY62177DV30 MoBL®
Contents
Pin Configuration .............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics Over the Operating Range ... 4
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics
(Over the Operating Range) ............................................. 5
Data Retention Waveform................................................. 6
Switching Characteristics Over the Operating Range .. 6
Switching Waveforms ...................................................... 7
Document Number : 38-05633 Rev. *G
Truth Table ..................................................................... 10
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagram ............................................................ 11
Reference Information ................................................... 11
Acronyms .................................................................. 11
Document Conventions ............................................. 11
Document History Page ................................................. 12
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support ....................... 13
Products .................................................................... 13
PSoC Solutions ......................................................... 13
Page 2 of 13
CY62177DV30 MoBL®
Pin Configuration[1]
Figure 1. 48-Ball FBGATop View
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
Vcc
D
VCC
I/O12 DNU
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
A19
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
A20
H
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62177DV30LL
Speed
(ns)
Min
Typ[2]
Max
2.2
3.0
3.6
55
Operating ICC(mA)
f = 1 MHz
Standby ISB2(A)
f = fmax
Typ[2]
Max
Typ[2]
Max
Typ[2]
Max
2
4
15
30
5
50
Notes
1. DNU pins have to be left floating or tied to Vss to ensure proper application.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C.
Document Number : 38-05633 Rev. *G
Page 3 of 13
CY62177DV30 MoBL®
Maximum Ratings
Output current into outputs (LOW) .............................. 20 mA
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature with
power applied .......................................... –55 °C to + 125 °C
Supply voltage to ground potential ...... –0.3 V to VCC + 0.3 V
DC voltage applied to outputs
in High Z state[3, 4] ............................... –0.3 V to VCC + 0.3 V
Static discharge voltage........................................... >2001 V
(per MIL-STD-883, method 3015)
Latch-up current..................................................... . >200 mA
Operating Range
Device
CY62177DV30LL
Range
Ambient
Temperature
VCC[5]
Industrial –40 °C to +85 °C
2.20 V to
3.60 V
DC input voltage[3, 4] ............................ –0.3 V to VCC + 0.3 V
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH voltage
VOL
Output LOW voltage
VIH
Input HIGH voltage
VCC = 2.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
Min
Typ[6]
Max
Unit
–
V
IOH = –0.1 mA
VCC = 2.20 V
2.0
–
IOH = –1.0 mA
VCC = 2.70 V
2.4
–
–
V
IOL = 0.1 mA
VCC = 2.20 V
–
–
0.4
V
IOL = 2.1 mA
VCC = 2.70 V
–
–
0.4
V
1.8
–
VCC
+0.3 V
V
2.2
–
VCC
+0.3 V
V
–
0.6
V
VIL
Input LOW voltage
VCC = 2.2 V to 2.7 V
–0.3
VCC = 2.7 V to 3.6 V
–0.3
–
0.8
V
IIX
Input leakage
current
GND  VI  VCC
–1
–
+1
A
IOZ
Output leakage
current
GND  VO  VCC, output disabled
–1
–
+1
A
ICC
VCC operating supply
current
f = fMAX = 1/tRC
15
30
mA
2
4
mA
ISB1
Automatic CE
power-down
current—CMOS
inputs
CE1  VCC0.2 V, CE2 < 0.2 V,
VIN  VCC–0.2 V, VIN  0.2 V)
f = fMAX (address and data only),
f = 0 (OE, WE, BHE and BLE), VCC = 3.60 V
–
5
100
A
ISB2
Automatic CE
power-down
current—CMOS
inputs
CE1  VCC 0.2 V, CE2 < 0.2 V,
VIN VCC – 0.2 V or VIN 0.2 V,
f = 0, VCC = 3.60 V
–
5
50
A
f = 1 MHz
VCC = VCCmax
IOUT = 0 mA
CMOS levels
Notes
3. VIL(min.) = –2.0 V for pulse durations less than 20 ns.
4. VIH(Max) = VCC + 0.75 V for pulse durations less than 20 ns.
5. Full device AC operation requires linear VCC ramp from 0 to VCC(min)  500 s.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C
Document Number : 38-05633 Rev. *G
Page 4 of 13
CY62177DV30 MoBL®
Capacitance
Parameter[7]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max.
Unit
12
pF
12
pF
TA = 25 °C, f = 1 MHz,
VCC = VCC(typ)
Thermal Resistance
Parameter[7]
Description
JA
Thermal resistance
(Junction to ambient)
JC
Thermal resistance
(Junction to case)
Test Conditions
BGA
Unit
55
C/W
16
C/W
Still Air, soldered on a 3 × 4.5 inch, two-layer printed
circuit board
AC Test Loads and Waveforms
R1
VCC
VCC
OUTPUT
50 pF
R2
10%
GND
Rise time = 1 V/ns
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
90%
90%
10%
Fall time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.5 V (2.2 V to 2.7 V)
3.0 V (2.7 V to 3.6 V)
Unit
R1
16667
1103

R2
15385
1554

RTH
8000
645

VTH
1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min
Typ[8]
1.5
–
–
V
–
–
25
A
Max
Unit
VDR
VCC for data retention
ICCDR
Data retention current
tCDR[7]
Chip deselect to data
retention time
0
–
–
ns
tR[9]
Operation recovery
time
55
–
–
ns
VCC= 1.5 V
CE1  VCC 0.2 V, CE2 < 0.2 V,
VIN  VCC – 0.2 V or VIN  0.2 V
Notes
7. Tested initially and after any design or process changes that may affect these parameters.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C
9. Full device operation requires linear VCC ramp from VDR to VCC(min.)  100 s or stable at VCC(min.)  100 s.
Document Number : 38-05633 Rev. *G
Page 5 of 13
CY62177DV30 MoBL®
Data Retention Waveform[10, 11]
DATA RETENTION MODE
VDR  1.5 V
VCC, min.
tCDR
VCC
VCC, min.
tR
CE or
BHE.BLE
Switching Characteristics Over the Operating Range
Parameter[11, 12]
Description
Min
Max
Unit
55
–
ns
READ CYCLE
tRC
Read cycle time
tAA
Address to data valid
–
55
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
55
ns
tDOE
OE LOW to data valid
–
25
ns
Z[13]
5
–
ns
–
20
ns
10
–
ns
–
20
ns
tLZOE
OE LOW to LOW
tHZOE
OE HIGH to High Z[13, 14]
tLZCE
CE LOW to Low
Z[13]
Z[13, 14]
tHZCE
CE HIGH to High
tPU
CE LOW to power-up
0
–
ns
tPD
CE HIGH to power-down
–
55
ns
tDBE
BLE/BHE LOW to data valid
–
55
ns
Z[13]
10
–
ns
–
20
ns
tLZBE
tHZBE
BLE/BHE LOW to Low
BLE/BHE HIGH to HIGH
Z[13, 14]
WRITE CYCLE[15]
tWC
Write cycle time
55
–
ns
tSCE
CE LOW to write end
40
–
ns
tAW
Address set-up to write end
40
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address set-up to write start
0
–
ns
tPWE
WE pulse width
40
–
ns
tBW
BLE/BHE LOW to write end
40
–
ns
tSD
Data set-up to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
WE LOW to High
Z[13, 14]
–
20
ns
WE HIGH to Low
Z[13]
10
–
ns
tHZWE
tLZWE
Notes
10. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
11. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0
to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
15. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Document Number : 38-05633 Rev. *G
Page 6 of 13
CY62177DV30 MoBL®
Switching Waveforms[16]
Figure 2. Read Cycle 1 (Address Transition Controlled)[17, 18]
tRC
ADDRESS
tOHA
DATA I/O
tAA
PREVIOUS DATA VALID
VALID DATA OUT
Figure 3. Read Cycle 2 (OE Controlled)[18, 19, 20]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
BHE/BLE
tLZBE
tDBE
tHZBE
OE
tDOE
DATA I/O
tLZOE
HIGH IMPEDANCE
tHZOE
HIGH
IMPEDANCE
VALID DATA OUT
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes
16. All Read/Write switching waveforms are shown for 16-bit data transactions only.
17. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
18. WE is HIGH for read cycle.
19. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
20. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
Document Number : 38-05633 Rev. *G
Page 7 of 13
CY62177DV30 MoBL®
Switching Waveforms[16] (continued)
Figure 4. Write Cycle 1 (WE Controlled)[21, 22, 23, 24, 25]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA IN
See Note 23
tHZOE
Figure 5. Write Cycle 2 (CE Controlled)[21, 22, 23, 24, 25]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA IN
See Note 23
t
HZOE
Notes
21. Data I/O is high impedance if OE = VIH.
22. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.
23. During this period, the I/Os are in output state and input signals should not be applied.
24. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
25. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Document Number : 38-05633 Rev. *G
Page 8 of 13
CY62177DV30 MoBL®
Switching Waveforms[16] (continued)
Figure 6. Write Cycle 3 (WE Controlled, OE LOW)[26, 27, 28]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
See Note 28
tHD
VALID DATA
tLZWE
tHZWE
Figure 7. Write Cycle 4 (BHE/BLE Controlled, OE LOW)[26, 27, 28]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
See Note 28
tHD
VALID DATA
Notes
26. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
27. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.
28. During this period, the I/Os are in output state and input signals should not be applied.
Document Number : 38-05633 Rev. *G
Page 9 of 13
CY62177DV30 MoBL®
Truth Table
CE1
CE2
WE
OE
BHE
BLE
H
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
H
L
H
H
L
L
H
H
L
H
L
Inputs/Outputs
Mode
Power
High Z
Deselect/power-down
Standby (ISB)
High Z
Deselect/power-down
Standby (ISB)
H
High Z
Deselect/power-down
Standby (ISB)
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
Data out (I/O0–I/O7);
High Z (I/O8–I/O15)
Read
Active (ICC)
H
L
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Read
Active (ICC)
H
H
H
L
H
High Z
Output disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output disabled
Active (ICC)
L
H
H
H
L
L
High Z
Output disabled
Active (ICC)
L
H
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
Data in (I/O0–I/O7);
High Z (I/O8–I/O15)
Write
Active (ICC)
L
H
L
X
L
H
High Z (I/O0–I/O7);
Data in (I/O8–I/O15)
Write
Active (ICC)
Package
Diagram
Package Type
51-85191
48-ball FBGA (8 mm × 9.5 mm × 1.2 mm) (Pb-free)
Ordering Information
Speed
(ns)
55
Ordering Code
CY62177DV30LL-55BAXI
Operating
Range
Industrial
Ordering Code Definitions
CY
621
7
7D V30 LL
55
BAX I
Temperature Grade
I = Industrial
Package Type = BAX :48-ball FBGA (Pb-free)
Speed Grade = 55ns
Low Power
Voltage Range (3 V Typical)
Bus Width = X16
D = 130nm Technology
Density = 32 Mbit
MoBL SRAM Family
Company ID: CY = Cypress
Document Number : 38-05633 Rev. *G
Page 10 of 13
CY62177DV30 MoBL®
Package Diagram
Figure 8. 48 ball FBGA (8 × 9.5 × 1.2 mm) (51-85191)
51-85191 *B
Reference Information
Acronyms
Document Conventions
Acronym
Description
Units of Measure
CMOS
complementary metal oxide semiconductor
I/O
input/output
°C
degrees Celsius
SRAM
static random access memory
A
microampere
FBGA
fine ball grid array
mA
milliampere
MHz
megahertz
ns
nanosecond
pF
picofarad
V
volt

ohm
W
watt
Document Number : 38-05633 Rev. *G
Symbol
Unit of Measure
Page 11 of 13
CY62177DV30 MoBL®
Document History Page
Document Title: CY62177DV30 MoBL® 32-Mbit (2 M × 16) Static RAM
Document #: 38-05633
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
251075
AJU
See ECN
New Datasheet
*A
330363
AJU
See ECN
Changed title of data sheet from CYM62177DV30 to CY62177DV30
Added second chip enable (CE2)
Added footnote #12 on page 5
*B
400960
NXR
See ECN
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed ISB1 from 60 and 40 A to 100 A for the L and LL versions for both
the 55 and the 70 ns speed bins respectively.
*C
469187
NXR
See ECN
Converted from Preliminary to Final
Changed the ISB2(Max) from 40 A to 50 A for LL version of both 45 ns and 55
ns speed bins
Changed the ICCDR(Max) from 20 A to 25 A for LL version
Updated the Ordering Information table
*D
2896036
AJU
03/19/10
Removed inactive parts from Ordering Information.
Updated package diagram.
Updated links in Sales, Solutions, and Legal Information.
*E
3153110
RAME
01/25/2011
Updated datasheet as per template
Removed CY62177DV30L related info
Removed 70 ns speed bin related info
Added Ordering Code Definitions
Added Reference Information and Units of Measure table
*F
3329873
RAME
07/27/11
*G
3685455
MEMJ
Document Number : 38-05633 Rev. *G
Removed footnote # 8 and its reference because of single package availability.
Updated template and styles according to current Cypress standards.
Added acronyms and units.
Removed reference to AN1064 SRAM system guidelines.
07/20/2012 Added Note 16. Updated text in Switching Waveforms diagrams.
Updated Package Diagram.
Page 12 of 13
CY62177DV30 MoBL®
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2006-2012. T6he information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
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integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number : 38-05633 Rev. *G
Revised July 20, 2012
All products and company names mentioned in this document may be the trademarks of their respective holders.
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