LINER LT3512HMSPBF

LT3512
Monolithic High Voltage
Isolated Flyback Converter
FEATURES
DESCRIPTION
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The LT3512 is a high voltage monolithic switching regulator specifically designed for the isolated flyback topology.
No third winding or opto-isolator is required for regulation as the part senses output voltage directly from the
primary-side flyback waveform. The device integrates a
420mA, 150V power switch, high voltage circuitry, and
control into a high voltage 16-lead MSOP package with
four leads removed.
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4.5V to 100V Input Voltage Range
Internal 420mA, 150V Power Switch
Boundary Mode Operation
No Transformer Third Winding or
Opto-Isolator Required for Regulation
Improved Primary-Side Winding Feedback
Load Regulation
VOUT Set with Two External Resistors
BIAS Pin for Internal Bias Supply and Power
Switch Driver
No External Start-Up Resistor
16-Lead MSOP Package
The LT3512 operates from an input voltage range of 4.5V
to 100V and delivers up to 4.5W of isolated output power.
Two external resistors and the transformer turns ratio
easily set the output voltage. Off-the-shelf transformers
are available for several applications. The high level of
integration and the use of boundary mode operation results
in a simple, clean, tightly regulated application solution to
the traditionally tough problem of isolated power delivery.
APPLICATIONS
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Isolated Telecom Power Supplies
Isolated Auxiliary/Housekeeping Power Supplies
Isolated Industrial, Automotive and Medical Power
Supplies
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
and No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 5438499, 7471522.
TYPICAL APPLICATION
48V to 5V Isolated Flyback Converter
1μF
1M
t
VIN
EN/UVLO
43.2k
LT3512
169k
RFB
RREF
10k
TC
SW
VC
11μH
175μH
t
5.25
VOUT+
5V
0.5A
4:1
5.20
5.15
47μF
VOUT–
5.10
VOUT (V)
VIN
36V TO 72V
Output Load and Line Regulation
VIN = 48V
5.05
VIN = 36V
5.00
VIN = 72V
4.95
4.90
4.85
GND BIAS
4.80
57.6k
12.7k
4.75
4.7μF
4.7nF
3512 TA01a
0
100
200
300
400
LOAD CURRENT (mA)
500
3512 TA01b
3512f
1
LT3512
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
SW (Note 4) ............................................................150V
VIN, EN/UVLO..........................................................100V
RFB ............................................................100V, VIN ±6V
BIAS ...................................................................VIN, 20V
RREF,TC, VC .................................................................6V
Operating Junction Temperature Range (Note 2)
LT3512E, LT3512I .............................. –40°C to 125°C
LT3512H ............................................ –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
TOP VIEW
EN/UVLO 1
16 SW
VIN 3
14 RFB
GND
BIAS
NC
GND
5
6
7
8
12
11
10
9
RREF
TC
VC
GND
MS PACKAGE
16(12)-LEAD PLASTIC MSOP
θJA = 90°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3512EMS#PBF
LT3512EMS#TRPBF
3512
16-Lead Plastic MSOP
–40°C to 125°C
LT3512IMS#PBF
LT3512IMS#TRPBF
3512
16-Lead Plastic MSOP
–40°C to 125°C
LT3512HMS#PBF
LT3512HMS#TRPBF
3512
16-Lead Plastic MSOP
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 24V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
l
Input Voltage Range
VIN = BIAS
Quiescent Current
Not Switching
VEN/UVLO = 0.2V
EN/UVLO Pin Threshold
EN/UVLO Pin Voltage Rising
EN/UVLO Pin Current
VEN/UVLO =1.1V
VEN/UVLO =1.4V
l
TYP
MAX
UNITS
100
15
V
V
3.5
0
4.5
mA
μA
1.15
1.21
1.27
V
2.0
2.6
0
3.3
μA
μA
6
4.5
Maximum Switching Frequency
650
Minimum Switching Frequency
kHz
40
kHz
Maximum Current Limit
420
600
800
mA
Minimum Current Limit
80
120
150
mA
Switch VCESAT
ISW = 200mA
RREF Voltage
l
RREF Voltage Line Regulation
6V < VIN < 100V
RREF Pin Bias Current
(Note 3)
Error Amplifier Voltage Gain
Error Amplifier Transconductance
0.5
∆I = 2μA
l
1.18
1.17
V
1.20
1.215
1.23
V
V
0.01
0.03
%/V
80
400
nA
150
V/V
140
μmhos
3512f
2
LT3512
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 24V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TC Current into RREF
RTC = 53.6k
BIAS Pin Voltage
Internally Regulated
3
5.20
5.15
8
4.0
6
3.5
4.95
BIAS VOLTAGE (V)
IQ (mA)
VOUT (V)
5.00
4
4.90
3.0
VIN = 24V
VIN = 48V
VIN = 100V
4.80
4.75
–50 –25
0
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
V
2.5
2
4.85
3.2
BIAS Pin Voltage
5.10
5.05
μA
3.1
TA = 25°C, unless otherwise noted.
Quiescent Current
VIN = 48V
UNITS
125°C operating junction temperature range. The LT3512H is guaranteed
over the full –40°C to 150°C operating junction temperature range. High
junction temperatures degrade operating lifetimes. Operating lifetime is
derated at junction temperatures greater than 125°C.
Note 3: Current flows out of the RREF pin.
Note 4: The SW pin is rated to 150V for transients. Operating waveforms
of the SW pin should keep the pedestal of the flyback waveform below
100V as shown in Figure 5.
TYPICAL PERFORMANCE CHARACTERISTICS
5.25
MAX
9.5
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3512E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3512I is guaranteed to meet performance specifications from –40°C to
Output Voltage
TYP
0
VIN = 24V, 10mA
VIN = 24V, NO LOAD
2.0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3512 G01
0
25 50 75 100 125 150
TEMPERATURE (°C)
3512 G02
Switch VCESAT
3512 G03
Switch Current Limit
2000
Quiescent Current vs VIN
800
5
MAXIMUM CURRENT LIMIT
CURRENT LIMIT (mA)
1600
1200
800
4
600
500
IQ (mA)
SWITCH VCESAT VOLTAGE (mV)
700
400
2
300
200
400
3
MINIMUM CURRENT LIMIT
1
100
0
0
300
100
200
400
SWITCH CURRENT (mA)
500
3512 G04
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3512 G05
0
0
20
60
40
VOLTAGE (V)
80
100
3512 G06
3512f
3
LT3512
TYPICAL PERFORMANCE CHARACTERISTICS
EN/UVLO Pin (Hysteresis) Current
vs Temperature
TA = 25°C, unless otherwise noted.
EN/UVLO Pin Current
vs VEN/UVLO
5
EN/UVLO Threshold
vs Temperature
30
3.0
25
2.5
EN/UVLO PIN CURRENT (μA)
EN/UVLO PIN CURRENT (μA)
4
3
2
1
EN/UVLO THRESHOLD (V)
EN/UVLO = 1.2V
20
15
10
1
25 50 75 100 125 150
TEMPERATURE (°C)
1.0
0
–50 –25
0
0
1.5
0.5
5
0
–50 –25
2.0
20
40
60
80
VEN/UVLO VOLTAGE (V)
100
Maximum Frequency
vs Temperature
3512 G09
Minimum Frequency
vs Temperature
EN/UVLO Shutdown Threshold
vs Temperature
900
90
0.8
800
80
500
400
300
200
100
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
EN/UVLO THRESHOLD (V)
0.9
MINIMUM FREQUENCY (kHz)
100
MAXIMUM FREQUENCY (kHz)
1000
600
25 50 75 100 125 150
TEMPERATURE (°C)
3512 G08
3512 G07
700
0
70
60
40
40
30
0.7
0.6
0.5
0.4
0.3
20
0.2
10
0.1
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3512 G11
3512 G10
3512 G14
Light Load Discontinuous
Mode Waveform
Boundary Mode Waveform
20V/DIV
20V/DIV
2μs/DIV
3512 G12
2μs/DIV
3512 G13
3512f
4
LT3512
PIN FUNCTIONS
EN/UVLO (Pin 1): Enable/Undervoltage Lockout. The EN/
UVLO pin is used to start up the LT3512. Pull the pin to 0V
to shut down the LT3512. This pin has an accurate 1.21V
threshold and can be used to program an undervoltage
lockout (UVLO) threshold using a resistor divider from
supply to ground. A 2.6μA pin current hysteresis allows
the programming of undervoltage lockout (UVLO) hysteresis. EN/UVLO can be directly connected to VIN. If left
open circuit the part will not power up.
VIN (Pin 3): Input Supply Pin. This pin supplies current to
the internal start-up circuitry, and serves as a reference
voltage for the DCM comparator and feedback circuitry.
Must be locally bypassed with a capacitor.
GND (Pin 5, 8, 9): Ground Pins. All three pins should be
tied directly to the local ground plane.
BIAS (Pin 6): Bias Voltage. This pin supplies current to
the switch driver and internal circuitry of the LT3512.
This pin may also be connected to VIN if a third winding
is not used and if VIN < 20V. The part can operate down
to 4.5V when BIAS and VIN are connected together. If a
third winding is used, the BIAS voltage should be lower
than the input voltage and greater than 3.3V for proper
operation. BIAS must be bypassed with a 4.7μF capacitor
placed close to the pin.
VC (Pin 10): Compensation Pin for Internal Error Amplifier.
Connect a series RC from this pin to ground to compensate
the switching regulator. An additional 100pF capacitor from
this pin to ground helps eliminate noise.
TC (Pin 11): Output Voltage Temperature Compensation. Connect a resistor to ground to produce a current
proportional to absolute temperature to be sourced into
the RREF node.
ITC = 0.55V/RTC.
RREF (Pin 12): Input Pin for External Ground-Referred
Reference Resistor. The resistor at this pin should be 10k.
For nonisolated applications, a traditional resistor voltage
divider from VOUT may be connected to this pin.
RFB (Pin 14): Input Pin for External Feedback Resistor.
This pin is connected to the transformer primary (VSW).
The ratio of this resistor to the RREF resistor, times the
internal bandgap reference, determines the output voltage (plus the effect of any non-unity transformer turns
ratio). For nonisolated applications, this pin should be
connected to VIN.
SW (Pin 16): Switch Pin. Collector of the internal power
switch. Minimize trace area at this pin to minimize EMI
and voltage spikes.
3512f
5
LT3512
BLOCK DIAGRAM
D1
VIN
VOUT +
T1
C1
L1A
L1B
C2
R3
VOUT –
N:1
VIN
TC
CURRENT
Q3
SW
RFB
FLYBACK
ERROR
AMP
Q2
TC
R5
I2
1.2V
–g
m
+
–
+
ONE
SHOT
CURRENT
COMPARATOR
A2
–
A1
+
–
VIN
DRIVER
BIAS
RREF
S
R4
+
V1
120mV
R
Q1
Q
S
BIAS
MASTER
LATCH
C4
1.21V
R1
EN/UVLO
+
A5
–
R2
3μA
INTERNAL
REFERENCE
AND
REGULATORS
+
–
A4
RSENSE
0.01Ω
GND
OSCILLATOR
VC
Q4
R6
C3
3512 BD
3512f
6
LT3512
OPERATION
The LT3512 is a current mode switching regulator IC designed specifically for the isolated flyback topology. The
key problem in isolated topologies is how to communicate
information regarding the output voltage from the isolated
secondary side of the transformer to the primary side.
Historically, optoisolators or extra transformer windings
communicate this information across the transformer.
Optoisolator circuits waste output power, and the extra
components increase the cost and physical size of the
power supply. Optoisolators can also exhibit trouble due
to limited dynamic response, nonlinearity, unit-to-unit
variation and aging over life. Circuits employing an extra
transformer winding also exhibit deficiencies. Using an
extra winding adds to the transformer’s physical size and
cost, and dynamic response is often mediocre.
In the LT3512, the primary-side flyback pulse provides
information about the isolated output voltage. In this manner, neither optoisolator nor extra transformer winding is
required for regulation. Two resistors program the output
voltage. Since this IC operates in boundary mode, the part
calculates output voltage from the switch pin when the
secondary current is almost zero.
The Block Diagram shows an overall view of the system.
Many of the blocks are similar to those found in traditional
switching regulators including internal bias regulator, oscillator, logic, current amplifier, current comparator, driver,
and output switch. The novel sections include a special
flyback error amplifier and a temperature compensation
circuit. In addition, the logic system contains additional
logic for boundary mode operation.
The LT3512 features boundary mode control, where the part
operates at the boundary between continuous conduction
mode and discontinuous conduction mode. The VC pin
controls the current level just as it does in normal current
mode operation, but instead of turning the switch on at the
start of the oscillator period, the part turns on the switch
when the secondary-side winding current is zero.
Boundary Mode Operation
Boundary mode is a variable frequency, current mode
switching scheme. The switch turns on and the inductor
current increases until a VC pin controlled current limit.
After the switch turns off, the voltage on the SW pin rises
to the output voltage divided by the secondary-to-primary
transformer turns ratio plus the input voltage. When the
secondary current through the diode falls to zero, the SW
pin voltage falls below VIN. A discontinuous conduction
mode (DCM) comparator detects this event and turns the
switch back on.
Boundary mode returns the secondary current to zero every
cycle, so parasitic resistive voltage drops do not cause load
regulation errors. Boundary mode also allows the use of a
smaller transformer compared to continuous conduction
mode and does not exhibit subharmonic oscillation.
At low output currents, the LT3512 delays turning on the
switch, and thus operates in discontinuous mode. Unlike
traditional flyback converters, the switch has to turn on
to update the output voltage information. Below 0.6V on
the VC pin, the current comparator level decreases to
its minimum value, and the internal oscillator frequency
decreases. With the decrease of the internal oscillator,
the part starts to operate in DCM. The output current is
able to decrease while still allowing a minimum switch off
time for the flyback error amplifier. The typical minimum
internal oscillator frequency with VC equal to 0V is 40kHz.
3512f
7
LT3512
APPLICATIONS INFORMATION
PSUEDO DC THEORY
In the Block Diagram, RREF (R4) and RFB (R3) are external
resistors used to program the output voltage. The LT3512
operates similar to traditional current mode switchers,
except in the use of a unique error amplifier, which derives
its feedback information from the flyback pulse.
Operation is as follows: when the output switch, Q1, turns
off, its collector voltage rises above the VIN rail. The amplitude of this flyback pulse, i.e., the difference between
it and VIN, is given as:
VFLBK = (VOUT + VF + ISEC • ESR) • NPS
VF = D1 forward voltage
ISEC = Transformer secondary current
ESR = Total impedance of secondary circuit
NPS = Transformer effective primary-to-secondary turns
ratio
RFB and Q2 convert the flyback voltage into a current. Nearly
all of this current flows through RREF to form a groundreferred voltage. The resulting voltage forms the input
to the flyback error amplifier. The flyback error amplifier
samples the voltage information when the secondary side
winding current is zero. The bandgap voltage, 1.20V, acts
as the reference for the flyback error amplifier.
The relatively high gain in the overall loop will then cause
the voltage at RREF to be nearly equal to the bandgap
reference voltage VBG. The resulting relationship between
VFLBK and VBG approximately equals:
⎛ VFLBK ⎞ VBG
⎛ R ⎞
or VFLBK = VBG ⎜ FB ⎟
⎜⎝ R ⎟⎠ = R
⎝ RREF ⎠
FB
REF
VBG = Internal bandgap reference
Combination of the preceding expression with earlier
derivation of VFLBK results in the following equation:
⎛ R ⎞⎛ 1 ⎞
VOUT = VBG ⎜ FB ⎟ ⎜
− VF − ISEC (ESR)
⎝ RREF ⎠ ⎝ NPS ⎟⎠
The expression defines VOUT in terms of the internal reference, programming resistors, transformer turns ratio
and diode forward voltage drop. Additionally, it includes
the effect of nonzero secondary output impedance (ESR).
Boundary control mode minimizes the effect of this impedance term.
Temperature Compensation
The first term in the VOUT equation does not have temperature dependence, but the diode forward drop has a
significant negative temperature coefficient. A positive
temperature coefficient current source connects to the
RREF pin to compensate. A resistor to ground from the
TC pin sets the compensation current.
The following equation explains the cancellation of the
temperature coefficient:
R
1
δVF
= − FB •
•
NPS
δT
R TC
−R
1
R TC = FB •
NPS δVF / δT
δVTC
or,
δT
δV
R
• TC ≈ FB
δT
NPS
(δVF /δT) = Diode’s forward voltage temperature coefficient
(δVTC /δT) = 2mV
VTC = 0.55V
Experimentally verify the resulting value of RTC and adjust as
necessary to achieve optimal regulation over temperature.
The addition of a temperature coefficient current modifies
the expression of output voltage as follows:
⎛ R ⎞⎛ 1 ⎞
VOUT = VBG ⎜ FB ⎟ ⎜
− VF
⎝ RREF ⎠ ⎝ NPS ⎟⎠
⎛V ⎞ R
− ⎜ TC ⎟ • FB – ISEC (ESR)
⎝ R TC ⎠ NPS
Output Power
A flyback converter has a complicated relationship between the input and output current compared to a buck
or a boost. A boost has a relatively constant maximum
input current regardless of input voltage and a buck has a
relatively constant maximum output current regardless of
input voltage. This is due to the continuous nonswitching
behavior of the two currents. A flyback converter has both
discontinuous input and output currents which makes it
3512f
8
LT3512
APPLICATIONS INFORMATION
similar to a nonisolated buck-boost. The duty cycle will
affect the input and output currents, making it hard to
predict output power. In addition, the winding ratio can
be changed to multiply the output current at the expense
of a higher switch voltage.
One design example would be a 5V output converter with
a minimum input voltage of 36V and a maximum input
voltage of 72V. A four-to-one winding ratio fits this design
example perfectly and outputs close to 3.0W at 72V but
lowers to 2.5W at 36V.
The graphs in Figures 1-4 show the typical maximum
output power possible for the output voltages 3.3V, 5V,
12V and 24V. The maximum power output curve is the
calculated output power if the switch voltage is 100V
during the off-time. 50V of margin is left for leakage voltage spike. To achieve this power level at a given input, a
winding ratio value must be calculated to stress the switch
to 100V, resulting in some odd ratio values. The following
curves are examples of common winding ratio values
and the amount of output power at given input voltages.
The equations below calculate output power:
Power = η • VIN • D • IPEAK • 0.5
Efficiency = η = ~83%
Duty cycle = D =
Peak switch current = IPEAK = 0.44A
5.0
5.0
4.0
N = NPS(MAX)
N = 12
N = 10
N=8
3.0
N=6
2.0
N=4
1.0
N=5
N = NPS(MAX)
4.0
OUTPUT POWER (W)
N = 15
OUTPUT POWER (W)
( VOUT + VF ) •NPS
( VOUT + VF ) •NPS + VIN
N=4
N=3
N=2
3.0
2.0
N=1
1.0
N=2
0
0
0
20
40
60
INPUT VOLTAGE (V)
80
0
100
20
40
60
INPUT VOLTAGE (V)
80
3512 F03
3512 F01
Figure 3. Output Power for 12V Output
Figure 1. Output Power for 3.3V Output
5.0
5.0
N = NPS(MAX)
N=8
N=7
N=6
N=5
N=4
3.0
N=3
2.0
N=2
N=1
1.0
N=2
4.0
OUTPUT POWER (W)
N = NPS(MAX)
4.0
OUTPUT POWER (W)
100
3.0
N=1
2.0
1.0
0
0
0
20
40
60
INPUT VOLTAGE (V)
80
100
3512 F02
Figure 2. Output Power for 5V Output
0
20
40
60
INPUT VOLTAGE (V)
80
100
3512 F04
Figure 4. Output Power for 24V Output
3512f
9
LT3512
APPLICATIONS INFORMATION
Table 1. Predesigned Transformers
TRANSFORMER
PART NUMBER
LPRI (μH)
LEAKAGE (μH)
NP:NS:NB
ISOLATION (V)
SATURATION
CURRENT (mA)
VENDOR
TARGET APPLICATIONS
750311559
175
1.5
4:1:1
1500
800
Würth
Elektronik
750311573
200
2
6:1:2
1500
800
Würth
Elektronik
750311662
151
2
1:1:0.2
1500
800
750311661
150
1.85
2:1:0.66
1500
1.1A
Würth
Elektronik
Würth
Elektronik
48V to 5V, 0.5A
24V to 5V, 0.38A
12V to 5V, 0.2A
48V to 3.3V, 0.59A
24V to 3.3V, 0.48A
12V to 3.3V, 0.29A
24V to 5V, 0.45A
12V to 5V, 0.23A
48V to 3.3V, 0.7A
24V to 3.3V, 0.59A
12V to 3.3V, 0.33A
48V to 24V, 0.11A
750311839
200
3
2:1:1
1500
800
Würth
Elektronik
750311964
100
0.7
1:5:5
1500
900
Würth
Elektronik
750311966
120
0.45
1:5:0.5
1500
900
750311692
80
2
1:5:5
1500
1.0A
10396-T025
200
2.0
4:1:1.2
1500
800
Würth
Elektronik
Würth
Elektronik
Sumida
10396-T027
200
2.0
6:1:2
1500
800
Sumida
01355-T058
10396-T023
125
200
2.0
2.0
1:1:0.2
2:1:0.33
1500
1500
800
800
Sumida
Sumida
10396-T029
200
2.5
2:1:1
1500
800
Sumida
01355-T061
100
2
1:5:5
1500
800
Sumida
48V to 15V, 0.2A
48V to 12V, 0.22A
24V to 15V, 0.15A
12V to 15V, 0.075A
48V to ±15V, 0.1A
48V to ±12V, 0.11A
24V to ±15V, 0.075A
12V to ± 70V, 0.007A
12V to ± 100V, 0.005A
12V to ± 150V, 0.004A
12V to +120V& -12V, 0.005A
12V ± 70V, 0.007A
48V to 5V, 0.5A
24V to 5V, 0.38A
12V to 5V, 0.2A
48V to 3.3V, 0.59A
24V to 3.3V, 0.48A
12V to 3.3V, 0.29A
24V to 5V, 0.45A
12V to 5V, 0.23A
48V to 3.3V, 0.7A
24V to 3.3V, 0.59A
12V to 3.3V, 0.33A
48V to 24V, 0.11A
48V to 15V, 0.2A
48V to 12V, 0.22A
24V to 15V, 0.15A
12V to 15V, 0.075A
48V to ±15V, 0.1A
48V to ±12V, 0.11A
24V to ±15V, 0.075A
12V to ± 70V, 0.007A
12V to ± 100V, 0.005A
12V to ± 150V, 0.004A
3512f
10
LT3512
APPLICATIONS INFORMATION
TRANSFORMER DESIGN CONSIDERATIONS
Successful application of the LT3512 relies on proper
transformer specification and design. Carefully consider
the following information in addition to the traditional
guidelines associated with high frequency isolated power
supply transformer design.
For lower output power levels, choose a 1:1 or 1:N
transformer for the absolute smallest transformer size. A
1:N transformer will minimize the magnetizing inductance
(and minimize size), but will also limit the available output
power. A higher 1:N turns ratio makes it possible to have
very high output voltages without exceeding the breakdown
voltage of the internal power switch.
Linear Technology has worked with several leading magnetic component manufacturers to produce pre-designed
flyback transformers for use with the LT3512. Table 1
shows the details of these transformers.
The turns ratio is an important element in the isolated
feedback scheme. Make sure the transformer manufacturer
guarantees turns ratio accuracy within ±1%.
Turns Ratio
Saturation Current
Note that when using an RFB/RREF resistor ratio to set
output voltage, the user has relative freedom in selecting
a transformer turns ratio to suit a given application. In
contrast, the use of simple ratios of small integers, e.g.,
1:1, 2:1, 3:2, provides more freedom in setting total turns
and mutual inductance.
The current in the transformer windings should not exceed its rated saturation current. Energy injected once the
core is saturated will not be transferred to the secondary
and will instead be dissipated in the core. Information on
saturation current should be provided by the transformer
manufacturers. Table 1 lists the saturation current of the
transformers designed for use with the LT3512.
Typically, choose the transformer turns to maximize available output power. For low output voltages (3.3V or 5V), a
N:1 turns ratio can be used with multiple primary windings
relative to the secondary to maximize the transformer’s
current gain (and output power). However, remember that
the SW pin sees a voltage that is equal to the maximum
input supply voltage plus the output voltage multiplied by
the turns ratio. In addition, leakage inductance will cause
a voltage spike (VLEAKAGE) on top of this reflected voltage.
This total quantity needs to remain below the absolute
maximum rating of the SW pin to prevent breakdown of
the internal power switch. Together these conditions place
an upper limit on the turns ratio, N, for a given application.
Choose a turns ratio low enough to ensure:
N<
150V – VIN(MAX) – VLEAKAGE
VOUT + VF
For larger N:1 values, a transformer with a larger physical
size is needed to deliver additional current and provide a
large enough inductance value to ensure that the off-time
is long enough to accurately measure the output voltage.
For larger N:1 values, choose a transformer with a larger
physical size to deliver additional current. In addition,
choose a large enough inductance value to ensure that
the off-time is long enough to measure the output voltage.
Primary Inductance Requirements
The LT3512 obtains output voltage information from the
reflected output voltage on the switch pin. The conduction
of secondary winding current reflects the output voltage
on the primary. The sampling circuitry needs a minimum
of 400ns to settle and sample the reflected output voltage.
In order to ensure proper sampling, the secondary winding
needs to conduct current for a minimum of 400ns. The
following equation gives the minimum value for primaryside magnetizing inductance:
LPRI ≥
tOFF(MIN) •NPS • ( VOUT + VF )
IPEAK(MIN)
tOFF(MIN) = 400ns
IPEAK(MIN) = 100mA
Leakage Inductance and Clamp Circuits
Transformer leakage inductance (on either the primary or
secondary) causes a voltage spike to appear at the primary
after the output switch turns off. This spike is increasingly
prominent at higher load currents where more stored energy must be dissipated. When designing an application,
3512f
11
LT3512
APPLICATIONS INFORMATION
LS
adequate margin should be kept for the effect of leakage
voltage spikes. In most cases the reflected output voltage
on the primary plus VIN should be kept below 100V. This
leaves at least 50V of margin for the leakage spike across
line and load conditions. A larger voltage margin will be
needed for poorly wound transformers or for excessive
leakage inductance. Figure 5 illustrates this point. Minimize
transformer leakage inductance.
A clamp circuit is recommended for most applications.
Two circuits that can protect the internal power switch
include the RCD (resistor-capacitor-diode) clamp and the
DZ (diode-Zener) clamp. The clamp circuits dissipate the
stored energy in the leakage inductance. The DZ clamp
is the recommended clamp for the LT3512. Simplicity of
design, high clamp voltages, and low power levels make the
DZ clamp the preferred solution. Additionally, a DZ clamp
ensures well defined and consistent clamping voltages.
Figure 5 shows the clamp effect on the switch waveform
and Figure 6 shows the connection of the DZ clamp.
Z
D
3512 F06
Figure 6. DZ Clamp
Proper care must be taken when choosing both the diode
and the Zener diode. Schottky diodes are typically the best
choice, but some PN diodes can be used if they turn on
fast enough to limit the leakage inductance spike. Choose
a diode that has a reverse-voltage rating higher than the
maximum input voltage. The Zener diode breakdown voltage should be chosen to balance power loss and switch
voltage protection. The best compromise is to choose the
largest voltage breakdown. Use the following equation to
make the proper choice:
VZENER(MAX) ≤ 150V – VIN(MAX)
For an application with a maximum input voltage of 72V,
choose a 68V VZENER which has VZENER(MAX) at 72V, which
will be below the 78V maximum.
VSW
<150V
VLEAKAGE
<100V
t OFF > 400ns
TIME
tSP < 150ns
without Clamp
The power loss in the clamp will determine the power rating of the Zener diode. Power loss in the clamp is highest
at maximum load and minimum input voltage. The switch
current is highest at this point along with the energy stored
in the leakage inductance. A 0.5W Zener will satisfy most
applications when the highest VZENER is chosen. Choosing
a low value for VZENER will cause excessive power loss as
shown in the following equations:
1
DZ Power Loss = •L C •IPK(VIN(MIN))2 • fSW •
2
⎞
⎛
NPS • ( VOUT + VF )
⎟
⎜ 1+ V
⎝
ZENER – NPS • ( VOUT + VF ) ⎠
L C = Leakage Inductance
VSW
<150V
<140V
<100V
IPK(VIN(MIN)) =
t OFF > 400ns
tSP < 150ns
3512 F05
TIME
with Clamp
Figure 5. Maximum Voltages for SW Pin Flyback Waveform
fSW =
VOUT •IOUT • 2
η • VIN(MIN) •DVIN(MIN)
1
1
=
L
•I
tON + tOFF
PRI PK(VIN(MIN)) LPRI •IPK(VIN(MIN))
+
VIN(MIN)
NPS • ( VOUT + VF )
3512f
12
LT3512
APPLICATIONS INFORMATION
Table 2 and 3 show some recommended diodes and Zener
diodes.
Table 2. Recommended Zener Diodes
VZENER
(V)
POWER
(W)
MMSZ5266BT1G
68
0.5
SOD-123 On Semi
MMSZ5270BT1G
91
0.5
SOD-123
CMHZ5266B
68
0.5
CMHZ5267B
75
0.5
SOD-123 Central
SOD-123 Semiconductor
BZX84J-68
68
0.5
SOD323F NXP
BZX100A
100
0.5
SOD323F
PART
CASE
VENDOR
Table 3. Recommended Diodes
PART
I (A)
VREVERSE
(V)
DFLS1100
1.0
100
DFLS1150
1.0
150
pulse. The smaller flyback pulse results in a higher regulated
output voltage. The inductive divider effect of secondary
leakage inductance is load independent. RFB/RREF ratio
adjustments can accommodate this effect to the extent
secondary leakage inductance is a constant percentage
of mutual inductance (over manufacturing variations).
Winding Resistance Effects
Resistance in either the primary or secondary will reduce
overall efficiency (POUT/PIN). Good output voltage regulation will be maintained independent of winding resistance
due to the boundary mode operation of the LT3512.
Bifilar Winding
VENDOR
Diodes Inc.
Leakage Inductance Blanking
When the power switch turns off, the flyback pulse appears. However, a finite time passes before the transformer primary-side voltage waveform approximately
represents the output voltage. Rise time on the SW node
and transformer leakage inductance cause the delay. The
leakage inductance also causes a very fast voltage spike
on the primary side of the transformer. The amplitude of
the leakage spike is largest when power switch current is
highest. Introduction of an internal fixed delay between
switch turn-off and the start of sampling provides immunity to the phenomena discussed above. The LT3512
sets internal blanking to 150ns. In certain cases leakage
inductance spikes last longer than the internal blanking,
but will not significantly affect output regulation.
Secondary Leakage Inductance
In addition to primary leakage inductance, secondary leakage inductance exhibits an important effect on application
design. Secondary leakage inductance forms an inductive
divider on the transformer secondary. The inductive divider
effectively reduces the size of the primary-referred flyback
A bifilar, or similar winding technique, is a good way to
minimize troublesome leakage inductances. However, remember that this will also increase primary-to-secondary
capacitance and limit the primary-to-secondary breakdown
voltage, so bifilar winding is not always practical. The
Linear Technology applications group is available and
extremely qualified to assist in the selection and/or design
of the transformer.
APPLICATION DESIGN CONSIDERATIONS
Iterative Design Process
The LT3512 uses a unique sampling scheme to regulate
the isolated output voltage. The use of this isolated scheme
requires a simple iterative process to choose feedback
resistors and temperature compensation. Feedback resistor values and temperature compensation resistance
is heavily dependent on the application, transformer and
output diode chosen.
Once resistor values are fixed after iteration, the values
will produce consistent output voltages with the chosen
transformer and output diode. Remember, the turns ratio
of the transformer must be guaranteed within ±1%. The
transformer vendors mentioned in this data sheet can
build transformers to this specification.
3512f
13
LT3512
APPLICATIONS INFORMATION
Selecting RFB and RREF Resistor Values
The following section provides an equation for setting
RFB and RREF values. The equation should only serve
as a guide. Follow the procedure outlined in the Design
Procedure to set accurate values for RFB, RREF and RTC
using the iterative design procedure.
Rearrangement of the expression for VOUT in the Temperature Compensation section, developed in the Operations
section, yields the following expression for RFB :
RFB =
R1
EN/UVLO
RUN/STOP
CONTROL
(OPTIONAL)
R2
LT3512
GND
3512 F07
RREF • NPS ⎡⎣( VOUT + VF ) + VTC ⎤⎦
Figure 7. Undervoltage Lockout (UVLO)
VBG
In addition, the EN/UVLO pin draws 2.6μA when the voltage at the pin is below 1.21V. This current provides user
programmable hysteresis based on the value of R1. The
effective UVLO thresholds are:
where:
VOUT = Output voltage
VF = Switching diode forward voltage
NPS = Effective primary-to-secondary turns ratio
VTC = 0.55V
This equation assumes:
R TC =
VIN
RFB
NPS
The equation assumes the temperature coefficients of
the diode and VTC are equal, which is a good first order
approximation.
Strictly speaking, the above equation defines RFB not as an
absolute value, but as a ratio of RREF . So the next question
is, what is the proper value for RREF? The answer is that
RREF should be approximately 10k. The LT3512 is trimmed
and specified using this value of RREF . If the impedance of
RREF varies considerably from 10k, additional errors will
result. However, a variation in RREF of several percent is
acceptable. This yields a bit of freedom in selecting standard 1% resistor values to yield nominal RFB/RREF ratios.
Undervoltage Lockout (UVLO)
A resistive divider from VIN to the EN/UVLO pin implements undervoltage lockout (UVLO). Figure 7 shows this
configuration. The EN/UVLO pin threshold is set at 1.21V.
1.2V • (R1+ R2)
+ 2.6µA • R1
R2
1.2V • (R1+ R2)
VIN(UVLO,FALLING) =
R2
VIN(UVLO,RISING) =
Figure 7 also shows the implementation of external shutdown control while still using the UVLO function. The
NMOS grounds the EN/UVLO pin when turned on, and
puts the LT3512 in shutdown with quiescent current draw
of less than 1μA.
Minimum Load Requirement
The LT3512 recovers output voltage information using the
flyback pulse. The flyback pulse occurs once the switch
turns off and the secondary winding conducts current. In
order to regulate the output voltage, the LT3512 needs to
sample the flyback pulse. The LT3512 delivers a minimum
amount of energy even during light load conditions to
ensure accurate output voltage information. The minimum
delivery of energy creates a minimum load requirement
of 20mA to 25mA depending on the specific application.
Verify minimum load requirements for each application.
A Zener diode with a Zener breakdown of 20% higher
than the output voltage can serve as a minimum load if
pre-loading is not acceptable. For a 5V output, use a 6V
Zener with cathode connected to the output.
3512f
14
LT3512
APPLICATIONS INFORMATION
BIAS Pin Considerations
The BIAS pin powers the internal circuitry of the LT3512.
Three unique configurations exist for regulation of the BIAS
pin. In the first configuration, the internal LDO drives the
BIAS pin internally from the VIN supply. In the second setup,
the VIN supply directly drives the BIAS pin through a direct
connection bypassing the internal LDO. This configuration
will allow the part to operate down to 4.5V and up to 15V.
In the third configuration, an external supply or third winding drives the BIAS pin. Use this option when a voltage
supply exists lower than the input supply. Drive the BIAS
pin with a voltage supply higher than 3.3V to disable the
internal LDO. The lower voltage supply provides a more
efficient source of power for internal circuitry.
LT3512
VIN
6V TO 100V
LDO
3V
BIAS
LT3512
VIN
An external resistor-capacitor network compensates the
LT3512 on the VC pin. Typical compensation values are in
the range of RC = 15k and CC = 4.7nF (see the numerous
schematics in the Typical Applications section for other possible values). Proper choice of both RC and CC is important
to achieve stability and acceptable transient response. For
example, vulnerability to high frequency noise and jitter
result when RC is too large. On the other hand, if RC is
too small, transient performance suffers. The inverse is
true with respect to the value of CC. Transient response
suffers with too large of a CC, and instability results from
too small a CC. The specific value for RC and CC will vary
based on the application and transformer choice. Verify
specific choices with board level evaluation and transient
response performance.
Use the following design procedure as a guide to designing applications for the LT3512. Remember, the unique
sampling architecture requires an iterative process for
choosing correct resistor values.
BIAS
OPTIONAL
VIN
Loop Compensation
DESIGN PROCEDURE/DESIGN EXAMPLE
4.5V TO 15V
LDO
LT3512
improves overall system efficiency. Design the third winding to output a voltage between 3.3V and 12V. For a typical 48VIN application, overdriving the BIAS pin improves
efficiency 4% to 5%.
The design example involves designing a 15V output with
a 200mA load current and an input range from 36V to 72V.
VIN(MIN) = 36V, VIN(NOM) = 48V, VIN(MAX) = 72V, VOUT =
15V and IOUT = 200mA
6V TO 100V
LDO
3.3V < BIAS < 20V
BIAS
EXTERNAL
SUPPLY
3512 F08
Figure 8. BIAS Pin Configurations
Overdriving the BIAS Pin with a Third Winding
The LT3512 provides excellent output voltage regulation
without the need for an opto-coupler, or third winding,
but for some applications with higher input voltages
(>20V), an additional winding (often called a third winding)
Step 1: Select the transformer turns ratio.
NPS <
VSW(MAX) – VIN(MAX) – VLEAKAGE
VOUT + VF
VSW(MAX) = Max rating of internal switch = 150V
VLEAKAGE = Margin for transformer leakage spike = 40V
VF = Forward voltage of output diode = assume approximately ~ 0.5V
Example:
3512f
15
LT3512
APPLICATIONS INFORMATION
NPS <
Step 3: Determine primary inductance, switching
frequency and saturation current.
NPS = 2
Primary inductance for the transformer must be set
above a minimum value to satisfy the minimum off time
requirement.
150V – 72V – 40V
15V + 0.5V
NPS < 2.45
The choice of turns ratio is critical in determining output
power as shown earlier in the Output Power section. At
this point, a third winding can be added to the transformer
to drive the BIAS pin of the LT3512 for higher efficiencies.
Choose a turns ratio that sets the third winding voltage
to regulate between 3.3V and 6V for maximum efficiency.
Choose a third winding ratio to drive BIAS winding with
5V. (Optional)
Example:
NTHIRD VTHIRD 5V
=
=
= 0.33
NS
VOUT 15V
The turns ratio of the transformer chosen is as follows
NPRIMARY: NSECONDARY: NTHIRD = 2:1:0.33.
Step 2: Calculate maximum power output at minimum
VIN.
POUT(VIN(MIN)) = η • VIN(MIN) • IIN = η • VIN(MIN) • D •
IPEAK • 0.5
D=
( VOUT + VF ) •NPS
( VOUT + VF ) •NPS + VIN(MIN)
η = Efficiency = ~83%
IPEAK = Peak switch current = 0.44A
Example:
D = 0.46
POUT(VIN(MIN)) = 3W
IOUT(VIN(MIN)) = POUT(VIN(MIN))/VOUT = 0.2A
The chosen turns ratio satisfies the output current requirement of 200mA. If the output current was too low,
the minimum input voltage could be adjusted higher. The
turns ratio in this example is set to its highest ratio given
switch voltage requirements and margin for leakage inductance voltage spike.
LPRI ≥
tOFF(MIN) •NPS • ( VOUT + VF )
IPEAK(MIN)
tOFF(MIN) = 400ns
IPEAK(MIN) = 100mA
Example:
400ns • 2 • (15 + 0.5)
0.1
LPRI ≥ 124µH
LPRI ≥
In addition, primary inductance will determine switching
frequency.
fSW =
1
1
=
LPRI •IPEAK
tON + tOFF LPRI •IPEAK
+
VIN
NPS • ( VOUT + VF )
IPEAK =
VOUT •IOUT • 2
η • VIN •D
Example:
Let’s calculate switching frequency at our nominal VIN
of 48V.
D=
(15 + 0.5) • 2 = 0.39
(15 + 0.5) • 2 + 48
IPEAK =
15V • 0.2A • 2
= 0.39A
0.83 • 48V • 0.39
Let’s choose LPRI = 200μH. Remember, most transformers specify primary inductance with a tolerance of ±20%.
fSW = 240kHz
Finally, the transformer needs to be rated for the correct
saturation current level across line and load conditions.
In the given example, the worst-case condition for switch
current is at minimum VIN and maximum load.
3512f
16
LT3512
APPLICATIONS INFORMATION
Step 5: Choose an output capacitor.
VOUT •IOUT • 2
η • VIN • D
15V • 0.2A • 2
IPEAK =
= 0.44A
0.83 • 36V • 0.46
IPEAK =
The output capacitor choice should minimize output voltage
ripple and balance the trade-off between size and cost for
a larger capacitor. Use the equation below at nominal VIN:
Ensure that the saturation current covers steady-state
operation, start-up and transient conditions. To satisfy
these conditions, choose a saturation current 50% or more
higher than the steady-state calculation. In this example, a
saturation current between 700mA and 800mA is chosen.
Table 1 presents a list of pre-designed flyback transformers.
For this application, the Sumida 10396-T023 transformer
will be used.
Step 4: Choose the correct output diode.
The two main criteria for choosing the output diode include
forward current rating and reverse voltage rating. The
maximum load requirement is a good first-order guess
at the average current requirement for the output diode.
A better metric is RMS current.
IRMS =IPEAK(VIN(MIN)) •NPS •
1– DVIN(MIN)
3
Example:
1– 0.46
IRMS = 0.44 • 2 •
= 0.37A
3
Next calculate reverse voltage requirement using maximum VIN:
VREVERSE = VOUT +
VIN(MAX)
NPS
Example:
VREVERSE = 15V +
72V
= 51V
2
A 1.0A, 60V diode from Diodes Inc. (DFLS160) will be used.
C=
IOUT •D
ΔVOUT • fSW
Example:
Design for ripple levels below 50mV.
C=
0.2A • 0.39
= 6.5µF
0.05V • 240kHz
A 22μF, 25V output capacitor is chosen. Remember ceramic capacitors lose capacitance with applied voltage.
The capacitance can drop to 40% of quoted capacitance
at the max voltage rating.
Step 6: Design clamp circuit.
The clamp circuit protects the switch from leakage inductance spike. A DZ clamp is the preferred clamp circuit. The
Zener and the diode need to be chosen.
The maximum Zener value is set according to the maximum VIN:
VZENER(MAX) ≤ 150V – VIN(MAX)
Example:
VZENER(MAX) ≤ 150V – 72V
VZENER(MAX) ≤ 78V
In addition, power loss in the clamp circuit is inversely
related to the clamp voltage as shown previously. Higher
clamp voltages lead to lower power loss.
A 68V Zener with a maximum of 72V will provide optimal
protection and minimize power loss. Half-watt Zeners will
satisfy most clamp applications involving the LT3512.
Power loss can be calculated using the equations presented
in the Leakage Inductance and Clamp Circuit section.
The Zener chosen is a 68V 0.5W Zener from On Semiconductor (MMSZ5266BT1G).
3512f
17
LT3512
APPLICATIONS INFORMATION
Choose a diode that is fast and has sufficient reverse
voltage breakdown:
VREVERSE > VIN(MAX)
Example:
The diode needs to handle the peak switch current of the
switch which was determined to be 0.45A. A 100V, 1.0A
diode from Diodes Inc. (DFLS1100) is chosen.
Step 7: Compensation.
Compensation will be optimized towards the end of the
design procedure. Connect a resistor and capacitor from
the VC node to ground. Use a 15k resistor and a 4.7nF
capacitor.
Step 8: Select RFB and RTC Resistors.
Use the following equations to choose starting values for
RFB and RTC. Set RREF to 10k.
( VOUT + VF + 0.55V ) •NPS •RREF
1.2V
RREF = 10k
R TC =
R TC =
VOUT
VOUT(MEAS)
•RFB(OLD)
Example:
RFB(NEW) =
15V
• 267k = 237k
16.7V
Step 10: Remove RTC and measure output voltage
over temperature.
Measure output voltage in a controlled temperature environment like an oven to determine the output temperature
coefficient. Measure output voltage at a consistent load
current and input voltage, across the temperature range
of operation. This procedure will optimize line and load
regulation over temperature.
Calculate the temperature coefficient of VOUT :
ΔVOUT VOUT(HOT) – VOUT(COLD)
=
ΔTemp
THOT(°C) – TCOLD(°C)
RFB
NPS
Example:
Example:
RFB =
Power up the application with application components
connected and measure the regulated output voltage.
Readjust RFB based on the measured output voltage.
RFB(NEW) =
VREVERSE > 72V
RFB =
Step 9: Adjust RFB based on output voltage.
(15 + 0.5 + 0.55V ) • 2 • 10k = 267k
1.2V
267k
= 133k
2
VOUT measured at 200mA and 48VIN
ΔVOUT 15.42V – 15.02V
=
= 2.26mV °C
ΔTemp 125°C – ( −50°C)
3512f
18
LT3512
APPLICATIONS INFORMATION
Step 11: Calculate new value for RTC.
R TC(NEW) =
RFB 1.85mV °C
•
ΔVOUT
NPS
ΔTemp
Example:
R TC(NEW) =
237k 1.85
•
= 97.6k
2
2.26
VOUT
VOUT(MEAS)
•RFB(OLD)
Example:
RFB(NEW) =
Check minimum load requirement at maximum input
voltage. The minimum load occurs at the point where the
output voltage begins to climb up as the converter delivers
more energy than what is consumed at the output.
Example:
Step 12: Place new value for RTC, measure VOUT , and
readjust RFB due to RTC change.
RFB(NEW) =
Step 15: Ensure minimum load.
The minimum load at an input voltage of 72V is:
11mA
Step 16: EN/UVLO resistor values.
Determine amount of hysterysis required.
Voltage hysteresis = 2.6μA • R1
Example:
Choose 2V of hysteresis.
15V
• 237k = 243k
14.7V
Step 13: Verify new values of RFB and RTC over
temperature.
Measure output voltage over temperature with RTC
connected.
Step 14: Optimize compensation.
Now that values for RFB and RTC are fixed, optimize the
compensation. Compensation should be optimized for
transient response to load steps on the output. Check
transient response across the load range.
Example:
The optimal compensation for the application is:
RC = 18.7k, CC = 4.7nF
R1=
2V
= 768k
2.6µA
Determine UVLO Threshold.
1.2V • (R1+R2)
R2
1.2V •R1
R2 =
VIN(UVLO,FALLING) – 1.2V
VIN(UVLO,FALLING) =
Set UVLO falling threshold to 30V.
1.2V • 768k
= 32.4k
30V – 1.2V
1.2V • (R1+R2)
VIN(UVLO,FALLING) =
R2
1.2V • ( 768k + 32.4k )
=
= 30V
32.4k
R2 =
VIN(UVLO,RISING) = VIN(UVLO,FALLING) + 2.6μA • R1 = 30V
+ 2.6μA • 768k = 32V
3512f
19
LT3512
TYPICAL APPLICATIONS
48V to 5V Isolated Flyback Converter
VIN
36V TO 72V
4:1:1
C1
1μF
R1
1M
Z1
VIN
EN/UVLO
R2
43.2k
RFB
RREF
TC
R5
57.6k
VOUT–
C1: TAIYO YUDEN HMK316B7105KL-T
C3: TAIYO YUDEN EMK212B7475KG
C4: TAIYO YUDEN LMK325B7476MM-TR
D1: DIODES INC. SBR2A40P1
D2: CENTRAL SEMI CMDSH-3
D3: DIODES INC. DFLS1100
T1: WÜRTH 750311559
Z1: ON SEMI MMSZ5266BT1G
R4
10k
SW
VC
GND
BIAS
D2
R6
12.7k
C2
4.7nF
VOUT+
5V
0.5A
C4
47μF
11μH
D3
R3
169k
LT3512
T1
175μH
D1
L1C
11μH
C3
4.7μF
3512 TA02
OPTIONAL THIRD
WINDING FOR
HV OPERATION
48V to 15V Isolated Flyback Converter
VIN
36V TO 72V
C1
1μF
D1
2:1
R1
1M
Z1
VIN
T1
200μH
EN/UVLO
R2
43.2k
R3
243k
RFB
RREF
LT3512
TC
R5
97.6k
GND
D2
VOUT–
C1: TAIYO YUDEN HMK316B7105KL-T
C3: TAIYO YUDEN EMK212B7475KG
C4: MURATA GRM32ER71E226KE15B
D1: DIODES INC. DFLS160
D2: DIODES INC. DFLS1100
T1: SUMIDA 10396-T023
Z1: ON SEMI MMSZ5266BT1G
R4
10k
BIAS
R6
18.7k
C2
4.7nF
C4
22μF
50μH
SW
VC
VOUT+
15V
0.2A
C3
4.7μF
3512 TA03
48V to 24V Isolated Flyback Converter
VIN
36V TO 72V
C1
1μF
1:1
R1
1M
Z1
VIN
EN/UVLO
R2
43.2k
R3
187k
RFB
RREF
LT3512
TC
SW
VC
R5
162k
R4
10k
GND
BIAS
R6
24.3k
C2
2.2nF
D2
T1
151μH
D1
151μH
VOUT+
24V
110mA
C4
10μF
VOUT–
C1: TAIYO YUDEN HMK316B7105KL-T
C3: TAIYO YUDEN EMK212B7475KG
C4: TAIYO YUDEN UMK316AB7475KL-T
D1: DIODES INC. SBR1U150SA
D2: DIODES INC. DFLS1100
T1: WÜRTH 750311662
Z1: ON SEMI MMSZ5266BT1G
C3
4.7μF
3512 TA04
3512f
20
LT3512
TYPICAL APPLICATIONS
24V to 5V Isolated Flyback Converter
VIN
20V TO 30V
R1
1M
Z1
VIN
T1
200μH
EN/UVLO
R2
80.6k
R3
249k
LT3512
RFB
RREF
5.5μH
R5
69.8k
GND
VOUT–
C1: TAIYO YUDEN UMK316AB7475KL-T
C3: TAIYO YUDEN EMK212B7475KG
C4: TAIYO YUDEN LMK32587476MM-TR
D1: DIODES INC. SBR2A30P1
D2: DIODES INC. DFLS1100
T1: SUMIDA 10396-T027
Z1: ON SEMI MMSZ5270BT1G
R4
10k
BIAS
R6
6.49k
C2
4.7nF
C4
47μF
D2
SW
TC
VC
VOUT+
5V
0.45A
D1
6:1
C1
4.7μF
C3
4.7μF
3512 TA05
24V to 15V Isolated Flyback Converter
VIN
20V TO 30V
R1
1M
Z1
VIN
EN/UVLO
R2
80.6k
R3
237k
LT3512
RFB
RREF
T1
200μH
VC
R5
150k
GND
C4
22μF
VOUT–
C1: TAIYO YUDEN UMK316AB7475KL-T
C3: TAIYO YUDEN EMK212B7475KG
C4: MURATA GRM32ER71E226KE158
D1: DIODES INC. SBR140S3
D2: DIODES INC. DFLS1100
T1: SUMIDA 10396-T023
Z1: ON SEMI MMSZ5270BT1G
R4
10k
BIAS
R6
20k
C2
4.7nF
50μH
D2
SW
TC
VOUT+
15V
0.15A
D1
2:1
C1
4.7μF
C3
4.7μF
3512 TA06
12V to 15V Isolated Flyback Converter
VIN
8V TO 20V
2:1
C1
4.7μF
R1
1M
Z1
VIN
T1
150μH
EN/UVLO
R2
562k
R3
237k
LT3512
RFB
RREF
SW
TC
VC
R5
107k
GND
BIAS
R6
21.5k
C2
6.8nF
C3
4.7μF
R4
10k
D2
VOUT+
15V
70mA
D1
38μH
C4
10μF
Z2
VOUT–
OPTIONAL
MINIMUM LOAD
C1: TAIYO YUDEN UMK316AB7475KL-T
C3: TAIYO YUDEN EMK212B7475KG
C4: MURATA GRM32ER7IE226K
D1: DIODES INC. SBR2A40P1
D2: DIODES INC. DFLS1100
T1: WÜRTH 750311661
Z1: ON SEMI MMSZ5270BT1G
3512 TA08
3512f
21
LT3512
TYPICAL APPLICATIONS
12V to ±70V Isolated Flyback Converter
C6
R7 10pF
3k
VIN
10V TO 20V
D1
1:5:5
C1
2.2μF
R1
1M
VIN
Z1
EN/UVLO
R2
562k
R3
100k
T1
100μH
VOUT1+
70V
7mA
C4
0.47μF
D3
C7
R8 10pF
3k
VOUT1–
LT3512
D2
RFB
RREF
R4
10k
SW
TC
VC
R5
1M
GND
BIAS
R6
24.9k
C2
6.8nF
C3
4.7μF
3512 TA07
VOUT2+
7mA
C5
0.47μF
VOUT2–
–70V
C1: TAIYO YUDEN UMK316AB7475KL-T
C3: TAIYO YUDEN EMK212B7475KG
C4, C5: NIPPON CHEMI-CON KTS251B474M43N0T00
D1, D2: DIODES INC. ES1G
D3: DIODES INC. DFLS1100
T1: WÜRTH 750311692
Z1: ON SEMI MMS2527OBT1G
48V to 3.3V Non-Isolated Flyback Converter
VIN
36V TO 72V
6:1
C1
1μF
R1
1M
Z1
VIN
RFB
EN/UVLO
R3
1M
R2
43.2k
LT3512
VC
R5
1M
GND
T1
200μH
D2
5.5μH
VOUT+
3.3V
0.7A
C4
47μF
×2
VOUT–
8.66k
VOUT
RREF
R4
5k
SW
TC
D1
BIAS
R6
9.53k
C2
4.7nF
C1: TAIYO YUDEN HMK316B7105KL-T
C3: TAIYO YUDEN EMK212B7475KG
C4: TAIYO YUDEN LMK325B7476MM-TR ×2
D1: DIODES INC. SBR3U30P1
D2: DIODES INC. DFLS1100
T1: WÜRTH 750311573
Z1: ON SEMI MMSZ5266BT1G
C3
4.7μF
3512 TA09
3512f
22
LT3512
TYPICAL APPLICATIONS
48V to 12V Isolated Flyback Converter
VIN
36V TO 72V
R1
1M
Z1
VIN
T1
200μH
EN/UVLO
R2
43.2k
R3
191k
RFB
RREF
LT3512
TC
R5
75k
GND
VOUT–
C1: TAIYO YUDEN HMK316B7105KL-T
C3: TAIYO YUDEN EMK212B7475KG
C4: TAIYO YUDEN TMK316AB7106KL-T
D1: DIODES INC. DFLS160
D2: DIODES INC. DFLS1100
T1: SUMIDA 10396-T023
Z1: ON SEMI MMSZ5266BT1G
R4
10k
BIAS
R6
5.23k
C2
4.7nF
C4
10μF
50μH
D2
SW
VC
VOUT+
12V
0.2A
D1
2:1
C1
1μF
C3
4.7μF
3512 TA10
PACKAGE DESCRIPTION
MS Package
Varitation: MS16 (12)
16-Lead Plastic MSOP with 4 Pins Removed
(Reference LTC DWG # 05-08-1847 Rev A)
1.0
(.0394)
BSC
5.23
(.206)
MIN
0.889 p 0.127
(.035 p .005)
3.20 – 3.45
(.126 – .136)
4.039 p 0.102
(.159 p .004)
(NOTE 3)
16 14 121110 9
0.305 p 0.038
(.0120 p .0015)
TYP
0.50
(.0197)
BSC
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.280 p 0.076
(.011 p .003)
REF
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
DETAIL “A”
0o – 6o TYP
1
GAUGE PLANE
0.53 p 0.152
(.021 p .006)
DETAIL “A”
0.18
(.007)
SEATING
PLANE
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
3 567 8
1.0
(.0394)
BSC
0.86
(.034)
REF
0.1016 p 0.0508
(.004 p .002)
MSOP (MS12) 0510 REV A
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3512f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT3512
TYPICAL APPLICATION
48V to ±15V Isolated Flyback Converter
VIN
36V TO 72V
2:1:1
C1
1μF
R1
1M
Z1
VIN
T1
200μH
EN/UVLO
R2
43.2k
TC
VC
R5
287k
R4
10k
GND
BIAS
C3
4.7μF
3512 TA11
VOUT1–
50μH
VOUT2+
100mA
C5
10μF
VOUT2–
–15V
SW
R6
8.66k
C2
6.8nF
C4
10μF
D2
RFB
RREF
50μH
D3
R3
237k
LT3512
VOUT1+
15V
100mA
D1
C1: TAIYO YUDEN HMK316B7105KL-T
C3: TAIYO YUDEN EMK212B7475KG
C4, C5: TAIYO YUDEN TMK316AB7106KL-T
D1, D2: DIODES INC. SBR0560S1
D3: DIODES INC. DFLS1100
T1: WÜRTH 750311839
Z1: ON SEMI MMSZ5266BT16
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT3511
Monolithic High Voltage Isolated Flyback Converter
4.5V ≤ VIN ≤ 100V, 240mA/150V Onboard Power Switch, MSOP-16 with
High Voltage Spacing
LT3748
100V Isolated Flyback Controller
5V ≤ VIN ≤ 100V, No Opto-Isolator or “Third Winding” Required, Onboard
Gate Driver, MSOP-16 with High Voltage Pin Spacing
LT3958
High Input Voltage Boost, Flyback, SEPIC and
Inverting Converter
5V ≤ VIN ≤ 80V, 3.3A/84V Onboard Power Switch, 5mm × 6mm QFN-36
with High Voltage Pin Spacing
LT3957
Boost, Flyback, SEPIC and Inverting Converter
3V ≤ VIN ≤ 40V, 5A/40V Onboard Power Switch, 5mm × 6mm QFN-36 with
High Voltage Pin Spacing
LT3956
Constant-Current, Constant-Voltage Boost, Buck,
Buck-Boost, SEPIC or Flyback Converter
4.5V ≤ VIN ≤ 80V, 3.3A/84V Onboard Power Switch, True PWM Dimming,
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LT3575
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3V ≤ VIN ≤ 40V, No Opto-Isolator or “Third Winding” Required,
Up to 14W, TSSOP-16E
LT3573
Isolated Flyback Switching Regulator with 60V/1.25A
Integrated Switch
3V ≤ VIN ≤ 40V, No Opto-Isolator or “Third Winding” Required, Up to 7W,
MSOP-16E
LT3574
Isolated Flyback Switching Regulator with 60V/0.65A
Integrated Switch
3V ≤ VIN ≤ 40V, No Opto-Isolator or “Third Winding” Required, Up to 3W,
MSOP-16
LT3757
Boost, Flyback, SEPIC and Inverting Controller
2.9V ≤ VIN ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency,
3mm × 3mm DFN-10 and MSOP-10E Package
LT3758
Boost, Flyback, SEPIC and Inverting Controller
5.5V ≤ VIN ≤ 100V, 100kHz to 1MHz Programmable Operating Frequency,
3mm × 3mm DFN-10 and MSOP-10E Package
LTC1871/LTC1871-1/ No RSENSE™ Low Quiescent Current Flyback, Boost
LTC1871-7
and SEPIC Controller
2.5V ≤ VIN ≤ 36V, Burst Mode® Operation at Light Loads, MSOP-10
3512f
24 Linear Technology Corporation
LT 0211 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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© LINEAR TECHNOLOGY CORPORATION 2011