CYV15G0204RB
Independent Clock Dual HOTLink II™
Reclocking Deserializer
Features
• Second-generation HOTLink® technology
• Compliant to SMPTE 292M and SMPTE 259M video
standards
• Dual-channel video reclocking deserializer
— 195- to 1500-Mbps serial data signaling rate
— Simultaneous operation at different signaling rates
• Supports reception of either 1.485 or 1.485/1.001 Gbps data
rate with the same training clock
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external PLL
components
• Selectable differential PECL-compatible serial inputs
•
•
•
•
— Internal DC-restoration
Synchronous LVTTL parallel interface
JTAG boundary scan
Built-In Self-Test (BIST) for at-speed link testing
Link Quality Indicator
The CYV15G0204RB satisfies the SMPTE-259M and
SMPTE-292M compliance as per SMPTE EG34-1999 Pathological Test Requirements.
As a second-generation HOTLink device, the
CYV15G0204RB extends the HOTLink family with
enhanced levels of integration and faster data rates,
while maintaining serial-link compatibility (data and BIST)
with other HOTLink devices.
Each channel of the CYV15G0204RB Dual HOTLink II device
accepts a serial bit-stream from one of two selectable
PECL-compatible differential line receivers, and using a
completely integrated Clock and Data Recovery PLL, recovers
the timing information necessary for data reconstruction. The
recovered bit-stream is reclocked and retransmitted through
the reclocker serial outputs. Also, the recovered serial data is
deserialized and presented to the destination host system.
— Analog signal detect
•
•
•
•
•
and SMPTE 259 video applications. It supports signaling rates
in the range of 195 to 1500 Mbps per serial link. The two
channels are independent and can simultaneously operate at
different rates. Each receive channel accepts serial data and
converts it to 10-bit parallel characters and presents these
characters to an Output Register. The received serial data can
also be reclocked and retransmitted through the reclocker
serial outputs. Figure 1 illustrates typical connections between
independent video co-processors and corresponding
CYV15G0204RB
Reclocking
Deserializer
and
CYV15G0203TB Serializer chips.
— Digital signal detect
Low-power 2W @ 3.3V typical
Single 3.3V supply
Thermally enhanced BGA
Pb-Free package option available
0.25μ BiCMOS technology
Each channel contains an independent BIST pattern checker.
This BIST hardware allows at-speed testing of the high-speed
serial data paths in each receive section of this device, each
transmit section of a connected HOTLink II device, and across
the interconnecting links.
Functional Description
The CYV15G0204RB Independent Clock Dual HOTLink II™
Deserializing Reclocker is a point-to-point or point-to-multipoint communications building block enabling transfer of data
over a variety of high-speed serial links including SMPTE 292
The CYV15G0204RB is ideal for SMPTE applications where
different data rates and serial interface standards are
necessary for each channel. Some applications include
multi-format routers, switchers, format converters, SDI
monitors, and camera control units.
Figure 1. HOTLink II™ System Connections
Reclocked
Output
Video Coprocessor
10
Independent
Channel
CYV15G0203TB
Serializer
Independent
Channel
CYV15G0204RB
Reclocking Deserializer
Serial Links
10
Video Coprocessor
10
10
Reclocked
Output
Cypress Semiconductor Corporation
Document #: 38-02103 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 2, 2007
[+] Feedback
CYV15G0204RB
Document #: 38-02103 Rev. *C
TRGCLKB±
RXDB[9:0]
RXDA[9:0]
TRGCLKA±
CYV15G0204RB Deserializing Reclocker Logic Block Diagram
Reclocker
RX
Reclocker
RX
INB1±
INB2±
Deserializer
ROUTB1±
ROUTB2±
Deserializer
INA1±
INA2±
x10
ROUTA1±
ROUTA2±
x10
Page 2 of 24
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CYV15G0204RB
Reclocking Deserializer Path Block Diagram
= Internal Signal
RESET
TRST
TRGRATEA
JTAG
Boundary
Scan
Controller
x2
TRGCLKA
SDASEL[2..1]A[1:0]
TMS
TCLK
TDI
TDO
LDTDEN
Clock &
Data
Recovery
PLL
INA2+
INA2–
ULCA
10
10
Output
Register
INA1+
INA1–
Shifter
INSELA
BIST LFSR
LFIA
Receive
Signal
Monitor
10
BISTSTA
÷2
SPDSELA
RXDA[9:0]
RXCLKA+
RXCLKA–
RXBISTA[1:0]
RXRATEA
RXPLLPDA
Recovered Character Clock
Recovered Serial Data
Reclocker
Output PLL
Clock Multiplier A
RECLKOA
Register
ROE[2..1]A
ROE[2..1]A
ROUTA1+
ROUTA1–
ROUTA2+
ROUTA2–
Character-Rate Clock A
REPDOA
TRGRATEB
x2
TRGCLKB
SDASEL[2..1]B[1:0]
LDTDEN
Clock &
Data
Recovery
PLL
INB2+
INB2–
ULCB
10
10
Output
Register
INB1+
INB1–
Shifter
INSELB
BIST LFSR
LFIB
Receive
Signal
Monitor
10
BISTSTB
÷2
SPDSELB
RXDB[9:0]
RXCLKB+
RXCLKB–
RXBISTB[1:0]
RXRATEB
RXPLLPDB
Recovered Character Clock
Recovered Serial Data
Reclocker
Output PLL
Clock Multiplier B
RECLKOB
ROE[2..1]B
Register
ROE[2..1]B
ROUTB1+
ROUTB1–
ROUTB2+
ROUTB2–
Character-Rate Clock B
REPDOB
Document #: 38-02103 Rev. *C
Page 3 of 24
[+] Feedback
CYV15G0204RB
Device Configuration and Control Block Diagram
WREN
ADDR[2:0]
Device Configuration
and Control Interface
DATA[6:0]
Document #: 38-02103 Rev. *C
= Internal Signal
RXBIST[A..B]
RXRATE[A..B]
SDASEL[A..B][1:0]
RXPLLPD[A..B]
ROE[2..1][A..B]
Page 4 of 24
[+] Feedback
CYV15G0204RB
Pin Configuration (Top View)[1]
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
NC
NC
NC
VCC
IN
B1–
ROUT
B1–
GND
IN
B2–
ROUT
B2–
IN
A1–
ROUT
A1–
GND
IN
A2–
ROUT
A2–
VCC
VCC
NC
VCC
NC
VCC
NC
VCC
NC
VCC
IN
B1+
ROUT
B1+
GND
IN
B2+
ROUT
B2+
IN
A1+
ROUT
A1+
GND
IN
A2+
ROUT
A2+
VCC
NC
NC
NC
NC
TDI
TMS
VCC
VCC
VCC
ULCB
NC
GND
DATA
[6]
DATA
[4]
DATA
[2]
DATA
[0]
GND
NC
SPD
SELB
VCC
LDTD
EN
TRST
GND
TDO
VCC
ULCA
NC
GND
DATA
[5]
DATA
[3]
DATA
[1]
GND
GND
GND
NC
VCC
NC
VCC
SCAN TMEN3
EN2
TCLK
RESET INSELB INSELA
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
VCC
VCC
VCC
NC
NC
NC
GND
WREN
GND
GND
NC
NC
SPD
SELA
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
NC
NC
NC
GND
GND
NC
NC
NC
NC
NC
NC
NC
GND
NC
NC
NC
GND
NC
NC
NC
NC
NC
NC
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
NC
GND
GND
GND
GND
NC
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RX
DB[4]
RX
DB[3]
GND
GND
ADDR
[0]
TRG
CLKB–
VCC
VCC
VCC
RX
DB[8]
VCC
RX
DB[5]
RX
DB[1]
GND
BIST
STB
GND
VCC
VCC
LFIB
RX
CLKB–
VCC
RX
DB[6]
RX
DB[0]
GND
ADDR
[2]
VCC
VCC
RX
DB[9]
RX
CLKB+
VCC
RX
DB[7]
RX
DB[2]
GND
RE
CLKOB
GND
GND
VCC
VCC
RX
DA[4]
VCC
BIST
STA
RX
DA[0]
TRG
RE
CLKB+ CLKOA
GND
GND
VCC
VCC
RX
DA[9]
RX
DA[5]
RX
DA[2]
RX
DA[1]
ADDR
[1]
RX
CLKA+
RE
PDOA
GND
GND
VCC
VCC
LFIA
TRG
CLKA+
RX
DA[6]
RX
DA[3]
NC
GND
RX
CLKA–
GND
GND
VCC
VCC
RE
PDOB
TRG
CLKA–
RX
DA[8]
RX
DA[7]
GND
Note
1. NC = Do not connect.
Document #: 38-02103 Rev. *C
Page 5 of 24
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CYV15G0204RB
Pin Configuration (Bottom View)[1]
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NC
VCC
NC
VCC
VCC
ROUT
A2–
IN
A2–
GND
ROUT
A1–
IN
A1–
ROUT
B2–
IN
B2–
GND
ROUT
B1–
IN
B1–
VCC
NC
NC
NC
NC
NC
NC
NC
NC
VCC
ROUT
A2+
IN
A2+
GND
ROUT
A1+
IN
A1+
ROUT
B2+
IN
B2+
GND
ROUT
B1+
IN
B1+
VCC
NC
VCC
NC
VCC
TDO
GND
TRST
LDTD
EN
VCC
SPD
SELB
NC
GND
DATA
[0]
DATA
[2]
DATA
[4]
DATA
[6]
GND
NC
ULCB
VCC
VCC
VCC
TMS
TDI
TMEN3 SCAN
EN2
VCC
NC
VCC
NC
GND
GND
GND
DATA
[1]
DATA
[3]
DATA
[5]
GND
NC
ULCA
VCC
INSELA INSELB RESET
TCLK
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
NC
VCC
VCC
VCC
NC
NC
NC
SPD
SELA
NC
NC
GND
GND
WREN
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
NC
GND
GND
GND
GND
NC
NC
NC
NC
GND
GND
NC
NC
GND
NC
NC
NC
GND
NC
NC
NC
GND
NC
NC
NC
NC
NC
NC
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
NC
VCC
VCC
VCC
VCC
NC
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RX
DA[0]
BIST
STA
VCC
RX
DA[4]
VCC
VCC
GND
GND
RX
DA[1]
RX
DA[2]
RX
DA[5]
RX
DA[9]
VCC
VCC
GND
RX
DA[3]
RX
DA[6]
TRG
CLKA+
LFIA
VCC
VCC
RX
DA[7]
RX
DA[8]
TRG
CLKA–
RE
PDOB
VCC
VCC
Document #: 38-02103 Rev. *C
TRG
CLKB–
ADDR
[0]
GND
GND
RX
DB[3]
RX
DB[4]
VCC
VCC
VCC
VCC
VCC
GND
RE
TRG
CLKOA CLKB+
GND
BIST
STB
GND
RX
DB[1]
RX
DB[5]
VCC
RX
DB[8]
VCC
VCC
VCC
GND
GND
RE
PDOA
RX
CLKA+
ADDR
[1]
ADDR
[2]
GND
RX
DB[0]
RX
DB[6]
VCC
RX
CLKB–
LFIB
VCC
VCC
GND
GND
RX
CLKA–
GND
NC
RE
CLKOB
GND
RX
DB[2]
RX
DB[7]
VCC
RX
CLKB+
RX
DB[9]
VCC
VCC
GND
Page 6 of 24
[+] Feedback
CYV15G0204RB
Pin Definitions
CYV15G0204RB Dual HOTLink II Deserializing Reclocker
Name
I/O Characteristics Signal Description
Receive Path Data and Status Signals
RXDA[9:0]
RXDB[9:0]
LVTTL Output,
synchronous to the
RXCLK± output
Parallel Data Output. RXDx[9:0] parallel data outputs change relative to the receive
interface clock. If RXCLKx± is a full-rate clock, the RXCLKx± clock outputs are
complementary clocks operating at the character rate. The RXDx[9:0] outputs for the
associated receive channels follow rising edge of RXCLKx+ or falling edge of
RXCLKx–. If RXCLKx± is a half-rate clock, the RXCLKx± clock outputs are complementary clocks operating at half the character rate. The RXDx[9:0] outputs for the
associated receive channels follow both the falling and rising edges of the associated
RXCLKx± clock outputs.
When BIST is enabled on the receive channel, the BIST status is presented on the
RXDx[1:0] and BISTSTx outputs. See Table 5 on page 14 for each status reported
by the BIST state machine. Also, while BIST is enabled, the RXDx[9:2] outputs
should be ignored.
BISTSTA
BISTSTB
LVTTL Output,
synchronous to the
RXCLKx ± output
BIST Status Output. When RXBISTx[1:0] = 10, BISTSTx (along with RXDx[1:0])
displays the status of the BIST reception. See Table 5 on page 14 for the BIST status
reported for each combination of BISTSTx and RXDx[1:0].
When RXBISTx[1:0] ≠ 10, BISTSTx should be ignored.
REPDOA
REPDOB
Asynchronous to
reclocker output
channel
enable / disable
Reclocker Powered Down Status Output. REPDOx is asserted HIGH, when the
associated channel’s reclocker output logic is powered down. This occurs when
ROE2x and ROE1x are both disabled by setting ROE2x = 0 and ROE1x = 0.
Receive Path Clock Signals
TRGCLKA±
TRGCLKB±
Differential LVPECL CDR PLL Training Clock. TRGCLKx± clock inputs are used as the reference source
for the frequency detector (Range Controller) of the associated receive PLL to
or single-ended
reduce PLL acquisition time.
LVTTL input clock
In the presence of valid serial data, the recovered clock output of the receive CDR
PLL (RXCLKx±) has no frequency or phase relationship with TRGCLKx±.
When driven by a single-ended LVCMOS or LVTTL clock source, connect the clock
source to either the true or complement TRGCLKx input, and leave the alternate
TRGCLKx input open (floating). When driven by an LVPECL clock source, the clock
must be a differential clock, using both inputs.
RXCLKA±
RXCLKB±
LVTTL Output Clock Receive Clock Output. RXCLKx± is the receive interface clock used to control
timing of the RXDx[9:0] parallel outputs. These true and complement clocks are used
to control timing of data output transfers. These clocks are output continuously at
either the half-character rate (1/20th the serial bit-rate) or character rate (1/10th the
serial bit-rate) of the data being received, as selected by RXRATEx.
RECLKOA
RECLKOB
LVTTL Output
Reclocker Clock Output. RECLKOx output clock is synthesized by the associated
reclocker output PLL and operates synchronous to the internal recovered character
clock. RECLKOx operates at either the same frequency as RXCLKx± (RXRATEx =
0), or at twice the frequency of RXCLKx± (RXRATEx = 1).The reclocker clock outputs
have no fixed phase relationship to RXCLKx±.
Device Control Signals
RESET
LVTTL Input,
asynchronous,
internal pull-up
Document #: 38-02103 Rev. *C
Asynchronous Device Reset. RESET initializes all state machines, counters, and
configuration latches in the device to a known state. RESET must be asserted LOW
for a minimum pulse width. When the reset is removed, all state machines, counters
and configuration latches are at an initial state. As per the JTAG specifications the
device RESET cannot reset the JTAG controller. Therefore, the JTAG controller has
to be reset separately. Refer to “JTAG Support” on page 14 for the methods to reset
the JTAG state machine. See Table 3 on page 13 for the initialize values of the device
configuration latches.
Page 7 of 24
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CYV15G0204RB
Pin Definitions (continued)
CYV15G0204RB Dual HOTLink II Deserializing Reclocker
Name
I/O Characteristics Signal Description
LDTDEN
LVTTL Input,
internal pull-up
Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal Level
Detector, Range Controller, and Transition Density Detector are all enabled to
determine if the RXPLL tracks TRGCLKx± or the selected input serial data stream.
If the Signal Level Detector, Range Controller, or Transition Density Detector are out
of their respective limits while LDTDEN is HIGH, the RXPLL locks to TRGCLKx± until
such a time they become valid. The SDASEL[A..D][1:0] inputs are used to configure
the trip level of the Signal Level Detector. The Transition Density Detector limit is one
transition in every 60 consecutive bits. When LDTDEN is LOW, only the Range
Controller is used to determine if the RXPLL tracks TRGCLKx± or the selected input
serial data stream. It is recommended to set LDTDEN = HIGH.
ULCA
ULCB
LVTTL Input,
internal pull-up
Use Local Clock. When ULCx is LOW, the RXPLL is forced to lock to TRGCLKx±
instead of the received serial data stream. While ULCx is LOW, the LFIx for the
associated channel is LOW indicating a link fault.
When ULCx is HIGH, the RXPLL performs Clock and Data Recovery functions on
the input data streams. This function is used in applications in which a stable
RXCLKx± is needed. In cases when there is an absence of valid data transitions for
a long period of time, or the high-gain differential serial inputs (INx±) are left floating,
there may be brief frequency excursions of the RXCLKx± outputs from TRGCLKx±.
SPDSELA
SPDSELB
3-Level Select[2]
static control input
Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate range
of each channel’s receive PLL.
LOW = 195–400 MBd
MID = 400–800 MBd
HIGH = 800–1500 MBd.
INSELA
INSELB
LVTTL Input,
asynchronous
Receive Input Selector. The INSELx input determines which external serial bit
stream is passed to the receiver’s Clock and Data Recovery circuit. When INSELx
is HIGH, the Primary Differential Serial Data Input, INx1±, is selected for the
associated receive channel. When INSELx is LOW, the Secondary Differential Serial
Data Input, INx2±, is selected for the associated receive channel.
LFIA
LFIB
LVTTL Output,
asynchronous
Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the
logical OR of six internal conditions. LFIx is asserted LOW when any of the following
conditions is true:
• Received serial data rate outside expected range
• Analog amplitude below expected levels
• Transition density lower than expected
• Receive channel disabled
• ULCx is LOW
• Absence of TRGCLKx±.
Device Configuration and Control Bus Signals
WREN
LVTTL input,
asynchronous,
internal pull-up
Control Write Enable. The WREN input writes the values of the DATA[6:0] bus into
the latch specified by the address location on the ADDR[2:0] bus.[3]
ADDR[2:0]
LVTTL input
asynchronous,
internal pull-up
Control Addressing Bus. The ADDR[2:0] bus is the input address bus used to
configure the device. The WREN input writes the values of the DATA[6:0] bus into
the latch specified by the address location on the ADDR[2:0] bus.[3] Table 3 on page
13 lists the configuration latches within the device, and the initialization value of the
latches upon the assertion of RESET. Table 4 on page 14 shows how the latches are
mapped in the device.
Notes
2. 3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually
implemented by direct connection to VSS (ground). The HIGH level is usually implemented by direct connection to VCC (power). The MID level is usually
implemented by not connecting the input (left floating), which allows it to self bias to the proper level.
3. See “Device Configuration and Control Interface” on page 12 for detailed information on the operation of the Configuration Interface.
Document #: 38-02103 Rev. *C
Page 8 of 24
[+] Feedback
CYV15G0204RB
Pin Definitions (continued)
CYV15G0204RB Dual HOTLink II Deserializing Reclocker
Name
DATA[6:0]
I/O Characteristics Signal Description
LVTTL input
asynchronous,
internal pull-up
Control Data Bus. The DATA[6:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[6:0] bus into the latch
specified by address location on the ADDR[2:0] bus.[3] Table 3 on page 13 lists the
configuration latches within the device, and the initialization value of the latches upon
the assertion of RESET. Table 4 on page 14 shows how the latches are mapped in
the device.
Internal Device Configuration Latches
RXRATE[A..B]
Internal Latch[4]
SDASEL[2..1][A..B] Internal Latch
[1:0]
RXPLLPD[A..B]
[4]
Internal Latch[4]
[4]
Receive Clock Rate Select.
Signal Detect Amplitude Select.
Receive Channel Power Control.
Receive Bist Disabled.
RXBIST[A..B][1:0]
Internal Latch
ROE2[A..B]
Internal Latch[4]
Reclocker Differential Serial Output Driver 2 Enable.
ROE1[A..B]
Latch[4]
Reclocker Differential Serial Output Driver 1 Enable.
Internal
Factory Test Modes
SCANEN2
LVTTL input,
internal pull-down
Factory Test 2. SCANEN2 input is for factory testing only. This input may be left as
a NO CONNECT, or GND only.
TMEN3
LVTTL input,
internal pull-down
Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a
NO CONNECT, or GND only.
ROUTA1±
ROUTB1±
CML Differential
Output
Primary Differential Serial Data Output. The ROUTx1± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.
ROUTA2±
ROUTB2±
CML Differential
Output
Secondary Differential Serial Data Output. The ROUTx2± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.
INA1±
INB1±
Differential Input
Primary Differential Serial Data Input. The INx1± input accepts the serial data
stream for deserialization. The INx1± serial stream is passed to the receive CDR
circuit to extract the data content when INSELx = HIGH.
INA2±
INB2±
Differential Input
Secondary Differential Serial Data Input. The INx2± input accepts the serial data
stream for deserialization. The INx2± serial stream is passed to the receiver CDR
circuit to extract the data content when INSELx = LOW.
TMS
LVTTL Input,
internal pull-up
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained
high for ≥5 TCLK cycles, the JTAG test controller is reset.
TCLK
LVTTL Input,
internal pull-down
JTAG Test Clock.
TDO
3-State LVTTL
Output
Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not
selected.
TDI
LVTTL Input,
internal pull-up
Test Data In. JTAG data input port.
TRST
LVTTL Input,
internal pull-up
JTAG reset signal. When asserted (LOW), this input asynchronously resets the
JTAG test access port controller.
Analog I/O
JTAG Interface
Note
4. See “Device Configuration and Control Interface” on page 12 for detailed information on the internal latches.
Document #: 38-02103 Rev. *C
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CYV15G0204RB
Pin Definitions (continued)
CYV15G0204RB Dual HOTLink II Deserializing Reclocker
Name
I/O Characteristics Signal Description
Power
VCC
+3.3V Power.
GND
Signal and Power Ground for all internal circuits.
CYV15G0204RB HOTLink II Operation
The CYV15G0204RB is a highly configurable, independent
clocking, dual-channel reclocking deserializer designed to
support reliable transfer of large quantities of digital video
data, using high-speed serial links from multiple sources to
multiple destinations. This device supports two 10-bit
channels.
CYV15G0204RB Receive Data Path
Serial Line Receivers
Two differential Line Receivers, INx1± and INx2±, are
available on each channel for accepting serial data streams.
The active Serial Line Receiver on a channel is selected using
the associated INSELx input. The Serial Line Receiver inputs
are differential, and can accommodate wire interconnect and
filtering losses or transmission line attenuation greater than
16 dB. For normal operation, these inputs should receive a
signal of at least VIDIFF > 100 mV, or 200 mV peak-to-peak
differential. Each Line Receiver can be DC- or AC-coupled to
+3.3V powered fiber-optic interface modules (any ECL/PECL
family, not limited to 100K PECL) or AC-coupled to +5V
powered optical modules. The common-mode tolerance of
these line receivers accommodates a wide range of signal
termination voltages. Each receiver provides internal
DC-restoration, to the center of the receiver’s common mode
range, for AC-coupled signals.
Signal Detect/Link Fault
Each selected Line Receiver (i.e., that routed to the clock and
data recovery PLL) is simultaneously monitored for
• analog amplitude above amplitude level selected by
SDASELx
• transition density above the specified limit
• range controls report the received data stream inside
normal frequency range (±1500[21] ppm)
• receive channel enabled
• Presence of reference clock
• ULCx is not asserted.
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFIx (Link Fault Indicator) output associated with each
receive channel, which changes synchronous to the receive
interface clock.
Analog Amplitude
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable to allow
operation with highly attenuated signals, or in high-noise
environments. The analog amplitude level detection is set by
the SDASELx latch via device configuration interface. The
SDASELx latch sets the trip point for the detection of a valid
signal at one of three levels, as listed in Table 1. This control
input affects the analog monitors for both receive channels.
The Analog Signal Detect monitors are active for the Line
Receiver as selected by the associated INSELx input.
Table 1. Analog Amplitude Detect Valid Signal Levels[5]
SDASEL Typical Signal with Peak Amplitudes Above
00
Analog Signal Detector is disabled
01
140 mV p-p differential
10
280 mV p-p differential
11
420 mV p-p differential
Transition Density
The Transition Detection logic checks for the absence of
transitions spanning greater than six transmission characters
(60 bits). If no transitions are present in the data received, the
Detection logic for that channel asserts LFIx.
Range Controls
The CDR circuit includes logic to monitor the frequency of the
PLL Voltage Controlled Oscillator (VCO) used to sample the
incoming data stream. This logic ensures that the VCO
operates at, or near the rate of the incoming data stream for
two primary cases:
• when the incoming data stream resumes after a time in
which it has been “missing.”
• when the incoming data stream is outside the acceptable
signaling rate range.
To perform this function, the frequency of the RXPLL VCO is
periodically compared to the frequency of the TRGCLKx±
input. If the VCO is running at a frequency beyond
±1500 ppm[21] as defined by the TRGCLKx± frequency, it is
periodically forced to the correct frequency (as defined by
TRGCLKx±, SPDSELx, and TRGRATEx) and then released in
an attempt to lock to the input data stream.
The sampling and relock period of the Range Control is calculated as follows: RANGE_CONTROL_ SAMPLING_PERIOD
= (RECOVERED BYTE CLOCK PERIOD) * (4096).
Note
5. The peak amplitudes listed in this table are for typical waveforms that have generally 3–4 transitions for every ten bits. In a worse case environment the signals
may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase
the values in the table above by approximately 100 mV.
Document #: 38-02103 Rev. *C
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CYV15G0204RB
During the time that the Range Control forces the RXPLL VCO
to track TRGCLKx±, the LFIx output is asserted LOW. After a
valid serial data stream is applied, it may take up to one
RANGE CONTROL SAMPLING PERIOD before the PLL
locks to the input data stream, after which LFIx will be HIGH.
The operating serial signaling-rate and allowable range of
TRGCLK± frequencies are listed in Table 2.
Table 2. Operating Speed Settings
SPDSELx
TRGRATEx
TRGCLKx±
Frequency
(MHz)
Signaling
Rate (Mbps)
LOW
1
reserved
195–400
0
19.5–40
1
20–40
0
40–80
MID (Open)
HIGH
1
40–75
0
80–150
400–800
800–1500
Receive Channel Enabled
The CYV15G0204RB contains two receive channels that can
be independently enabled and disabled. Each channel can be
enabled or disabled separately through the RXPLLPDx input
latch as controlled by the device configuration interface. When
the RXPLLPDx latch = 0, the associated PLL and analog
circuitry of the channel is disabled. Any disabled channel
indicates a constant link fault condition on the LFIx output.
When RXPLLPDx = 1, the associated PLL and receive
channel is enabled to receive a serial stream.
Note. When a disabled receive channel is reenabled, the
status of the associated LFIx output and data on the parallel
outputs for the associated channel may be indeterminate for
up to 2 ms.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from each
received serial stream is performed by a separate CDR block
within each receive channel. The clock extraction function is
performed by an integrated PLL that tracks the frequency of
the transitions in the incoming bit stream and align the phase
of the internal bit-rate clock to the transitions in the selected
serial data stream.
Each CDR accepts a character-rate (bit-rate ÷ 10) or
half-character-rate (bit-rate ÷ 20) training clock from the
associated TRGCLKx± input. This TRGCLKx± input is used to
• ensure that the VCO (within the CDR) is operating at the
correct frequency (rather than a harmonic of the bit-rate)
• reduce PLL acquisition time
• limit unlocked frequency excursions of the CDR VCO when
there is no input data present at the selected Serial Line
Receiver.
Regardless of the type of signal present, the CDR attempts to
recover a data stream from it. If the signalling rate of the
recovered data stream is outside the limits set by the range
control monitors, the CDR tracks TRGCLKx± instead of the
data stream. Once the CDR output (RXCLK±) frequency
returns back close to TRGCLKx± frequency, the CDR input is
Document #: 38-02103 Rev. *C
switched back to the input data stream. If no data is present at
the selected line receiver, this switching behavior may result
in brief RXCLK± frequency excursions from TRGCLKx±.
However, the validity of the input data stream is indicated by
the LFIx output. The frequency of TRGCLKx± is required to be
within ±1500ppm[21] of the frequency of the clock that drives
the reference clock input of the remote transmitter to ensure a
lock to the incoming data stream. This large ppm tolerance
allows the CDR PLL to reliably receive a 1.485 or 1.485/1.001
Gbps SMPTE HD-SDI data stream with a constant TRGCLK
frequency.
For systems using multiple or redundant connections, the LFIx
output can be used to select an alternate data stream. When
an LFIx indication is detected, external logic can toggle
selection of the associated INx1± and INx2± input through the
associated INSELx input. When a port switch takes place, it is
necessary for the receive PLL for that channel to reacquire the
new serial stream.
Reclocker
Each receive channel performs a reclocker function on the
incoming serial data. To do this, the Clock and Data Recovery
PLL first recovers the clock from the data. The data is retimed
by the recovered clock and then passed to an output register.
Also, the recovered character clock from the receive PLL is
passed to the reclocker output PLL which generates the bit
clock that is used to clock the retimed data into the output
register. This data stream is then transmitted through the
differential serial outputs.
Reclocker Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for 50Ω transmission lines. These drivers accept data from the
reclocker output register in the reclocker channel. These
drivers have signal swings equivalent to that of standard PECL
drivers, and are capable of driving AC-coupled optical
modules or transmission lines.
Reclocker Output Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled via the configuration interface, it is
internally powered down to reduce device power. If both
reclocker serial drivers for a channel are in this disabled state,
the associated internal reclocker logic is also powered down.
The deserialization logic and parallel outputs will remain
enabled. A device reset (RESET sampled LOW) disables all
output drivers.
Note. When the disabled reclocker function (i.e., both outputs
disabled) is re-enabled, the data on the reclocker serial
outputs may not meet all timing specifications for up to 250 μs.
Output Bus
Each receive channel presents a 10-bit data signal (and a
BIST status signal when RXBISTx[1:0] = 10).
Receive BIST Operation
Each receiver channel contains an internal pattern checker
that can be used to validate both device and link operation.
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CYV15G0204RB
These pattern checkers are enabled by the associated
RXBISTx[1:0] latch via the device configuration interface.
When enabled, a register in the associated receive channel
becomes a signature pattern generator and checker by
logically converting to a Linear Feedback Shift Register
(LFSR). This LFSR generates a 511-character sequence. This
provides a predictable yet pseudo-random sequence that can
be matched to an identical LFSR in the attached Transmitter(s). When synchronized with the received data stream,
the associated Receiver checks each character from the
deserializer with each character generated by the LFSR and
indicates compare errors and BIST status at the RXDx[1:0]
and BISTSTx bits of the Output Register.
The BIST status bus {BISTSTx, RXDx[0], RXDx[1]} indicates
010b or 100b for one character period per BIST loop to
indicate loop completion. This status can be used to check test
pattern progress.
The specific status reported by the BIST state machine is listed
in Table 5. These same codes are reported on the receive
status outputs.
If the number of invalid characters received ever exceeds the
number of valid characters by 16, the receive BIST state
machine aborts the compare operations and resets the LFSR
to look for the start of the BIST sequence again.
A device reset (RESET sampled LOW) presets the BIST
Enable Latches to disable BIST on both channels.
BIST Status State Machine
When a receive path is enabled to look for and compare the
received data stream with the BIST pattern, the {BISTSTx,
RXDx[0], RXDx[1]} bits identify the present state of the BIST
compare operation.
The BIST state machine has multiple states, as shown in
Figure 2 and Table 5. When the receive PLL detects an
out-of-lock condition, the BIST state is forced to the
Start-of-BIST state, regardless of the present state of the BIST
state machine. If the number of detected errors ever exceeds
the number of valid matches by greater than 16, the state
machine is forced to the WAIT_FOR_BIST state where it
monitors the receive path for the first character of the next
BIST sequence.
Power Control
The CYV15G0204RB supports user control of the powered up
or down state of each transmit and receive channel. The
receive channels are controlled by the RXPLLPDx latch via the
device configuration interface. When RXPLLPDx = 0, the
associated PLL and analog circuitry of the channel is disabled.
The transmit channels are controlled by the OE1x and the
OE2x latches via the device configuration interface. The
reclocker function is controlled by the ROE1x and the ROE2x
latches via the device configuration interface. When a driver is
disabled via the configuration interface, it is internally powered
Document #: 38-02103 Rev. *C
down to reduce device power. If both serial drivers for a
channel are in this disabled state, the associated internal logic
for that channel is also powered down. When the reclocker
serial drivers are disabled, the reclocker function will be
disabled, but the deserialization logic and parallel outputs will
remain enabled.
Device Reset State
When the CYV15G0204RB is reset by assertion of RESET, all
state machines, counters, and configuration latches in the
device are initialized to a reset state. Additionally, the JTAG
controller must also be reset for valid operation (even if JTAG
testing is not performed). See “JTAG Support” on page 14 for
JTAG state machine initialization. See Table 3 on page 13 for
the initialize values of the configuration latches.
Following a device reset, it is necessary to enable the receive
channels used for normal operation. This can be done by
sequencing the appropriate values on the device configuration
interface.[3]
Device Configuration and Control Interface
The CYV15G0204RB is highly configurable via the configuration interface. The configuration interface allows each
channel to be configured independently. Table 3 on page 13
lists the configuration latches within the device including the
initialization value of the latches upon the assertion of RESET.
Table 4 on page 14 shows how the latches are mapped in the
device. Each row in the Table 4 maps to a 7-bit latch bank.
There are 6 such write-only latch banks. When WREN = 0, the
logic value in the DATA[6:0] is latched to the latch bank
specified by the values in ADDR[2:0]. The second column of
Table 4 specifies the channels associated with the corresponding latch bank. For example, the first three latch banks
(0,1 and 2) consist of configuration bits for channel A.
Latch Types
There are two types of latch banks: static (S) and dynamic (D).
Each channel is configured by 2 static and 1 dynamic latch
banks. The S type contain those settings that normally do not
change for a given application, whereas the D type controls
the settings that could change during the application's lifetime.
The first and second rows of each channel (address numbers
0, 1, 5, and 6) are the static control latches. The third row of
latches for each channel (address numbers 2, 7) are the
dynamic control latches that are associated with enabling
dynamic functions within the device. Address numbers 3 and
4 are internal test registers.
Static Latch Values
There are some latches in the table that have a static value (ie.
1, 0, or X). The latches that have a ‘1’ or ‘0’ must be configured
with their corresponding value each time that their associated
latch bank is configured. The latches that have an ‘X’ are don’t
cares and can be configured with any value.
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CYV15G0204RB
Table 3. Device Configuration and Control Latch Descriptions
Name
Signal Description
RXRATEA
RXRATEB
Receive Clock Rate Select. The initialization value of the RXRATEx latch = 1. RXRATEx is used to select
the rate of the RXCLKx± clock output.
When RXRATEx = 1, the RXCLKx± clock outputs are complementary clocks that follow the recovered
clock operating at half the character rate. Data for the associated receive channels should be latched
alternately on the rising edge of RXCLKx+ and RXCLKx–.
When RXRATEx = 0, the RXCLKx± clock outputs are complementary clocks that follow the recovered
clock operating at the character rate. Data for the associated receive channels should be latched on the
rising edge of RXCLKx+ or falling edge of RXCLKx–.
SDASEL1A[1:0]
SDASEL1B[1:0]
Primary Serial Data Input Signal Detector Amplitude Select. The initialization value of the
SDASEL1x[1:0] latch = 10. SDASEL1x[1:0] selects the trip point for the detection of a valid signal for the
INx1± Primary Differential Serial Data Inputs.
When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled.
When SDASEL1x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.
When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.
When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.
SDASEL2A[1:0]
SDASEL2B[1:0]
Secondary Serial Data Input Signal Detector Amplitude Select. The initialization value of the
SDASEL2x[1:0] latch = 10. SDASEL2x[1:0] selects the trip point for the detection of a valid signal for the
INx2± Secondary Differential Serial Data Inputs.
When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled
When SDASEL2x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.
When SDASEL2x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.
When SDASEL2x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.
TRGRATEA
TRGRATEB
Training Clock Rate Select. The initialization value of the TRGRATEx latch = 0. TRGRATEx is used to
select the clock multiplier for the training clock input to the associated CDR PLL. When TRGRATEx = 0,
the associated TRGCLKx± input is not multiplied before it is passed to the CDR PLL. When TRGRATEx
= 1, the TRGCLKx± input is multiplied by 2 before it is passed to the CDR PLL. TRGRATEx = 1 and
SPDSELx = LOW is an invalid state and this combination is reserved.
RXPLLPDA
RXPLLPDB
Receive Channel Enable. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects if the
associated receive channel is enabled or powered-down. When RXPLLPDx = 0, the associated receive
PLL and analog circuitry are powered-down. When RXPLLPDx = 1, the associated receive PLL and
analog circuitry are enabled.
RXBISTA[1:0]
RXBISTB[1:0]
Receive Bist Disable / SMPTE Receive Enable. The initialization value of the RXBISTx[1:0] latch = 11.
For SMPTE data reception, RXBISTx[1:0] should not remain in this initialization state (11). RXBISTx[1:0]
selects if receive BIST is disabled or enabled and sets the associated channel for SMPTE data reception.
When RXBISTx[1:0] = 01, the receiver BIST function is disabled and the associated channel is set to
receive SMPTE data. When RXBISTx[1:0] = 10, the receive BIST function is enabled and the associated
channel is set to receive BIST data. RXBISTx[1:0] = 00 and RXBISTx[1:0] = 11 are invalid states.
ROE2A
ROE2B
Reclocker Secondary Differential Serial Data Output Driver Enable. The initialization value of the
ROE2x latch = 0. ROE2x selects if the ROUT2± secondary differential output drivers are enabled or
disabled. When ROE2x = 1, the associated serial data output driver is enabled allowing data to be
transmitted from the transmit shifter. When ROE2x = 0, the associated serial data output driver is disabled.
When a driver is disabled via the configuration interface, it is internally powered down to reduce device
power. If both serial drivers for a channel are in this disabled state, the associated internal logic for that
channel is also powered down. A device reset (RESET sampled LOW) disables all output drivers.
ROE1A
ROE1B
Reclocker Primary Differential Serial Data Output Driver Enable. The initialization value of the ROE1x
latch = 0. ROE1x selects if the ROUT1± primary differential output drivers are enabled or disabled. When
ROE1x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the
transmit shifter. When ROE1x = 0, the associated serial data output driver is disabled. When a driver is
disabled via the configuration interface, it is internally powered down to reduce device power. If both serial
drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered
down. A device reset (RESET sampled LOW) disables all output drivers.
Document #: 38-02103 Rev. *C
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CYV15G0204RB
Device Configuration Strategy
The following is a series of ordered events needed to load the
configuration latches on a per channel basis:
1. Pulse RESET Low after device power-up. This operation
resets both channels. Initialize the JTAG state machine to
its reset state as detailed in JTAG Support.
2. Set the static latch banks for the target channel. [Optional
step if the default settings match the desired configuration.]
3. Set the dynamic bank of latches for the target channel.
Enable the Receive PLLs and set each channel for SMPTE
data reception (RXBISTx[1:0] = 01) or BIST data reception
(RXBISTx[1:0] = 10). [Required step]
To ensure valid device operation after power-up (including
non-JTAG operation), the JTAG state machine should also be
initialized to a reset state. This should be done in addition to
the device reset (using RESET). The JTAG state machine can
be initialized using TRST (asserting it LOW and de-asserting
it or leaving it asserted), or by asserting TMS HIGH for at least
5 consecutive TCLK cycles. This is necessary in order to
ensure that the JTAG controller does not enter any of the test
modes after device power-up. In this JTAG reset state, the rest
of the device will be in normal operation.
Note. The order of device reset (using RESET) and JTAG
initialization does not matter.
3-Level Select Inputs
JTAG Support
The CYV15G0204RB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan, and bypass are supported. This
capability is present only on the LVTTL inputs and outputs and
the TRGCLKx± clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain.
Each 3-Level select inputs reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11 respectively
JTAG ID
The JTAG device ID for the CYV15G0204RB is ‘0C811069’x.
Table 4. Device Control Latch Configuration Table
ADDR
Channel
Type
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Reset
Value
0
(000b)
A
S
1
0
X
X
0
0
RXRATEA
101111
1
(001b)
A
S
SDASEL2A[1]
SDASEL2A[0]
SDASEL1A[1]
SDASEL1A[0]
X
X
TRGRATEA
101011
2
(010b)
A
D
RXBISTA[1]
RXPLLPDA
RXBISTA[0]
X
ROE2A
ROE1A
X
101100
5
(101b)
B
S
1
0
X
X
0
0
RXRATEB
101111
6
(110b)
B
S
SDASEL2B[1]
SDASEL2B[0]
SDASEL1B[1]
SDASEL1B[0]
X
X
TRGRATEB
101011
7
(111b)
B
D
RXBISTB[1]
RXPLLPDB
RXBISTB[0]
X
ROE2B
ROE1B
X
101100
Table 5. Receive BIST Status Bits
Description
{BISTSTx, RXDx[0], RXDx[1]}
000, 001
Receive BIST Status
(Receive BIST = Enabled)
BIST Data Compare. Character compared correctly.
010
BIST Last Good. Last Character of BIST sequence detected and valid.
011
Reserved.
100
BIST Last Bad. Last Character of BIST sequence detected invalid.
101
BIST Start. Receive BIST is enabled on this channel, but character compares have not yet
commenced. This also indicates a PLL Out of Lock condition.
110
BIST Error. While comparing characters, a mismatch was found in one or more of the character
bits.
111
BIST Wait. The receiver is comparing characters. but has not yet found the start of BIST
character to enable the LFSR.
Document #: 38-02103 Rev. *C
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CYV15G0204RB
Figure 2. Receive BIST State Machine
Monitor Data
Received
Receive BIST
{BISTSTx, RXDx[0], Detected LOW
RXDx[1]} =
BIST_START (101)
RX PLL
Out of Lock
{BISTSTx, RXDx[0], RXDx[1]} =
BIST_WAIT (111)
Start of
BIST Detected
No
Yes, {BISTSTx, RXDx[0], RXDx[1]} =
BIST_DATA_COMPARE (000, 001)
Compare
Next Character
Mismatch
Yes
Match
Auto-Abort
Condition
{BISTSTx, RXDx[0], RXDx[1]} =
BIST_DATA_COMPARE (000, 001)
No
End-of-BIST
State
End-of-BIST
State
Yes, {BISTSTx, RXDx[0], RXDx[1]} =
BIST_LAST_BAD (100)
Yes, {BISTSTx, RXDx[0], RXDx[1]} =
BIST_LAST_GOOD (010)
No
No, {BISTSTx, RXDx[0], RXDx[1]} =
BIST_ERROR (110)
Document #: 38-02103 Rev. *C
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CYV15G0204RB
Maximum Ratings
Static Discharge Voltage.......................................... > 2000 V
(per MIL-STD-883, Method 3015)
Above which the useful life may be impaired. User guidelines
only, not tested
Latch-up Current..................................................... > 200 mA
Storage Temperature .................................. –65°C to +150°C
Power-up Requirements
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
The CYV15G0204RB requires one power-supply. The Voltage
on any input or I/O pin cannot exceed the power pin during
power-up.
Supply Voltage to Ground Potential ............... –0.5V to +3.8V
DC Voltage Applied to LVTTL Outputs
in High-Z State .......................................–0.5V to VCC + 0.5V
Output Current into LVTTL Outputs (LOW)..................60 mA
Operating Range
Range
Ambient Temperature
VCC
Commercial
0°C to +70°C
+3.3V ±5%
DC Input Voltage....................................–0.5V to VCC + 0.5V
CYV15G0204RB DC Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
LVTTL-compatible Outputs
VOHT
Output HIGH Voltage
IOH = − 4 mA, VCC = Min.
VOLT
Output LOW Voltage
IOL = 4 mA, VCC = Min.
0V[6],
IOST
Output Short Circuit Current
VOUT =
IOZL
High-Z Output Leakage Current
VOUT = 0V, VCC
VCC = 3.3V
2.4
V
0.4
V
–20
–100
mA
–20
20
µA
LVTTL-compatible Inputs
VIHT
Input HIGH Voltage
2.0
VCC + 0.3
V
VILT
Input LOW Voltage
–0.5
0.8
V
IIHT
Input HIGH Current
TRGCLKx Input, VIN = VCC
1.5
mA
Other Inputs, VIN = VCC
+40
µA
–1.5
mA
IILT
Input LOW Current
TRGCLKx Input, VIN = 0.0V
Other Inputs, VIN = 0.0V
–40
µA
IIHPDT
Input HIGH Current with internal pull-down
VIN = VCC
+200
µA
IILPUT
Input LOW Current with internal pull-up
VIN = 0.0V
–200
µA
VCC
mV
LVDIFF Inputs: TRGCLKx±
VDIFF[7]
Input Differential Voltage
400
VIHHP
Highest Input HIGH Voltage
1.2
VCC
V
VILLP
Lowest Input LOW voltage
0.0
VCC/2
V
Common Mode Range
1.0
VCC – 1.2V
V
VCOMREF
[8]
3-Level Inputs
VIHH
Three-Level Input HIGH Voltage
Min. ≤ VCC ≤ Max.
0.87 * VCC
VCC
V
VIMM
Three-Level Input MID Voltage
Min. ≤ VCC ≤ Max.
0.47 * VCC
0.53 * VCC
V
VILL
Three-Level Input LOW Voltage
Min. ≤ VCC ≤ Max.
0.0
0.13 * VCC
V
IIHH
Input HIGH Current
VIN = VCC
200
µA
IIMM
Input MID current
VIN = VCC/2
IILL
Input LOW current
VIN = GND
–50
50
µA
–200
µA
Notes
6. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
7. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the
true (+) input is more positive than the complement (−) input. A logic-0 exists when the complement (−) input is more positive than true (+) input.
8. The common mode range defines the allowable range of TRGCLKx+ and TRGCLKx− when TRGCLKx+ = TRGCLKx−. This marks the zero-crossing between
the true and complement inputs as the signal switches between a logic-1 and a logic-0.
Document #: 38-02103 Rev. *C
Page 16 of 24
[+] Feedback
CYV15G0204RB
CYV15G0204RB DC Electrical Characteristics (continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
100Ω differential load
VCC – 0.5
VCC – 0.2
V
150Ω differential load
VCC – 0.5
VCC – 0.2
V
100Ω differential load
VCC – 1.4
VCC – 0.7
V
150Ω differential load
VCC – 1.4
VCC – 0.7
V
100Ω differential load
450
900
mV
150Ω differential load
560
1000
mV
100
1200
mV
VCC
V
1350
μA
Differential CML Serial Outputs: ROUTA1±, ROUTA2±, ROUTB1±, ROUTB2±
VOHC
Output HIGH Voltage
(VCC Referenced)
VOLC
Output LOW Voltage
(VCC Referenced)
Output Differential Voltage
|(OUT+) − (OUT−)|
VODIF
Differential Serial Line Receiver Inputs: INA1±, INA2±, INB1±, INB2±
VDIFFs[7]
Input Differential Voltage |(IN+) − (IN−)|
VIHE
Highest Input HIGH Voltage
VILE
Lowest Input LOW Voltage
IIHE
Input HIGH Current
VIN = VIHE Max.
Input LOW Current
VIN = VILE Min.
–700
Common Mode input range
((VCC – 2.0V)+0.5)min,
(VCC – 0.5V) max.
+1.25
+3.1
IILE
VICOM
[9]
VCC – 2.0
Power Supply
ICC [10, 11]
ICC
Max Power Supply Current
[10, 11]
Typical Power Supply Current
V
μA
V
Typ.
Max.
TRGCLKx = Commercial
MAX
Industrial
620
720
mA
1320
mA
TRGCLKx = Commercial
125 MHz
Industrial
600
700
mA
1320
mA
AC Test Loads and Waveforms
3.3V
RL = 100Ω
R1
R1 = 590Ω
R2 = 435Ω
CL
CL ≤ 7 pF
(Includes fixture and
probe capacitance)
RL
(Includes fixture and
probe capacitance)
R2
(b) CML Output Test Load
[12]
(a) LVTTL Output Test Load[12]
3.0V
Vth = 1.4V
GND
2.0V
0.8V
2.0V
VIHE
VIHE
Vth = 1.4V
0.8V
≤ 1 ns
VILE
≤ 1 ns
(c) LVTTL Input Test Waveform
[13]
80%
80%
20%
≤ 270 ps
20%
VILE
≤ 270 ps
(d) CML/LVPECL Input Test Waveform
Notes
9. The common mode range defines the allowable range of INPUT+ and INPUT− when INPUT+ = INPUT−. This marks the zero-crossing between the true and
complement inputs as the signal switches between a logic-1 and a logic-0.
10. Maximum ICC is measured with VCC = MAX, TA = 25°C, with both channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and
outputs unloaded.
11. Typical ICC is measured under similar conditions except with VCC = 3.3V, TA = 25°C, with both channels enabled and one Serial Line Driver per transmit channel
sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.
12. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
13. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.
Document #: 38-02103 Rev. *C
Page 17 of 24
[+] Feedback
CYV15G0204RB
CYV15G0204RB AC Electrical Characteristics
Parameter
Description
Min.
Max
Unit
CYV15G0204RB Receiver LVTTL Switching Characteristics Over the Operating Range
fRS
RXCLKx± Clock Output Frequency
9.75
150
MHz
tRXCLKP
RXCLKx± Period = 1/fRS
6.66
102.56
ns
RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate)
–1.0
+1.0
ns
tRXCLKD
tRXCLKR
[14]
RXCLKx± Rise Time
0.3
1.2
ns
tRXCLKF [14]
RXCLKx± Fall Time
0.3
1.2
ns
tRXDv–[18]
Status and Data Valid Time to RXCLKx± (RXRATEx = 0) (Full Rate)
5UI–2.0[19]
ns
Status and Data Valid Time to RXCLKx± (RXRATEx = 1) (Half Rate)
5UI–1.3[19]
ns
Status and Data Valid Time to RXCLKx± (RXRATEx = 0) (Full Rate)
5UI–1.8
[19]
ns
5UI–2.6
[19]
tRXDv+[18]
Status and Data Valid Time to RXCLKx± (RXRATEx = 1) (Half Rate)
ns
fROS
RECLKOx Clock Frequency
19.5
150
MHz
tRECLKO
RECLKOx Period=1/fROS
6.66
51.28
ns
tRECLKOD
RECLKOx Duty Cycle centered at 60% HIGH time
–1.9
0
ns
CYV15G0204RB TRGCLKx Switching Characteristics Over the Operating Range
fTRG
TRGCLKx Clock Frequency
19.5
150
MHz
tTRGCLK
TRGCLKx Period = 1/fREF
6.6
51.28
ns
tTRGH
TRGCLKx HIGH Time (TRGRATEx = 1)(Half Rate)
5.9
TRGCLKx HIGH Time (TRGRATEx = 0)(Full Rate)
2.9[14]
ns
TRGCLKx LOW Time (TRGRATEx = 1)(Half Rate)
5.9
ns
TRGCLKx LOW Time (TRGRATEx = 0)(Full Rate)
2.9[14]
ns
tTRGL
tTRGD
[20]
TRGCLKx Duty Cycle
30
tTRGR [14, 15, 16, 17] TRGCLKx Rise Time (20%–80%)
tTRGF[14, 15, 16, 17] TRGCLKx Fall Time (20%–80%)
tTRGRX[21]
TRGCLKx Frequency Referenced to Received Clock Frequency
–0.15
ns
70
%
2
ns
2
ns
+0.15
%
CYV15G0204RB Bus Configuration Write Timing Characteristics Over the Operating Range
tDATAH
Bus Configuration Data Hold
0
ns
tDATAS
Bus Configuration Data Setup
10
ns
tWRENP
Bus Configuration WREN Pulse Width
10
ns
CYV15G0204RB JTAG Test Clock Characteristics Over the Operating Range
fTCLK
JTAG Test Clock Frequency
tTCLK
JTAG Test Clock Period
20
MHz
50
ns
30
ns
CYV15G0204RB Device RESET Characteristics Over the Operating Range
tRST
Device RESET Pulse Width
Notes
14. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
15. The ratio of rise time to falling time must not vary by greater than 2:1.
16. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
17. All transmit AC timing parameters measured with 1ns typical rise time and fall time.
18. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
19. Receiver UI (Unit Interval) is calculated as 1/(fTRG* 20) (when TRGRATEx = 1) or 1/(fTRG * 10) (when TRGRATEx = 0). In an operating link this is equivalent to tB.
20. The duty cycle specification is a simultaneous condition with the tREFH and tREFL parameters. This means that at faster character rates the TRGCLKx± duty
cycle cannot be as large as 30%–70%.
21. TRGCLKx± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.
TRGCLKx± must be within ±1500 PPM (±0.15%) of the transmitter PLL reference (REFCLKx±) frequency. Although transmitting to a HOTLink II receiver channel
necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be
within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard.
Document #: 38-02103 Rev. *C
Page 18 of 24
[+] Feedback
CYV15G0204RB
CYV15G0204RB AC Electrical Characteristics (continued)
Parameter
Description
Min.
Max
Unit
Min.
Max.
Unit
CYV15G0204RB Reclocker Serial Output Characteristics Over the Operating Range
Parameter
Description
Condition
tB
Bit Time
tRISE[14]
CML Output Rise Time 20−80% (CML Test Load)
tFALL[14]
CML Output Fall Time 80−20% (CML Test Load)
5128
660
ps
SPDSELx = HIGH
50
270
ps
SPDSELx = MID
100
500
ps
SPDSELx =LOW
180
1000
ps
SPDSELx = HIGH
50
270
ps
SPDSELx = MID
100
500
ps
SPDSELx =LOW
180
1000
ps
PLL Characteristics
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
CYV15G0204RB Reclocker Output PLL Characteristics
tJRGENSD[14, 22]
Reclocker Jitter Generation - SD Data Rate
TRGCLKx = 27 MHz
133
ps
tJRGENHD[14, 22]
Reclocker Jitter Generation - HD Data Rate
TRGCLKx = 148.5 MHz
107
ps
CYV15G0204RB Receive PLL Characteristics Over the Operating Range
tRXLOCK
tRXUNLOCK
Receive PLL lock to input data stream (cold start)
376k
UI
Receive PLL lock to input data stream
376k
UI
46
UI
Receive PLL Unlock Rate
Capacitance [14]
Max.
Unit
CINTTL
Parameter
TTL Input Capacitance
Description
TA = 25°C, f0 = 1 MHz, VCC = 3.3V
Test Conditions
7
pF
CINPECL
PECL input Capacitance
TA = 25°C, f0 = 1 MHz, VCC = 3.3V
4
pF
Switching Waveforms for the CYV15G0204RB HOTLink II Receiver
Receive Interface
Read Timing
tRXCLKP
RXRATEx = 0
RXCLKx+
RXCLKx–
tRXDV–
RXDx[9:0]
tRXDV+
Note
22. Receiver input stream is BIST data from the transmit channel. This data is reclocked and output to a wide-bandwidth digital sampling oscilloscope. The measurement was recorded after 10,000 histogram hits, time referenced to REFCLKx± of the transmit channel.
Document #: 38-02103 Rev. *C
Page 19 of 24
[+] Feedback
CYV15G0204RB
Switching Waveforms for the CYV15G0204RB HOTLink II Receiver (continued)
Receive Interface
Read Timing
tRXCLKP
RXRATEx = 1
RXCLKx+
RXCLKx–
tRXDV–
RXDx[9:0]
tRXDV+
CYV15G0204RB HOTLink II Bus Configuration Switching Waveforms
Bus Configuration
Write Timing
ADDR[2:0]
DATA[6:0]
tWRENP
WREN
tDATAS
tDATAH
Document #: 38-02103 Rev. *C
Page 20 of 24
[+] Feedback
CYV15G0204RB
Table 6. Package Coordinate Signal Allocation
Ball
ID
Signal Name
Signal Type
Ball
ID
Signal Name
Signal Type
Ball
ID
Signal Name
A01
NC
NO CONNECT
A02
NC
NO CONNECT
C07
NC
NO CONNECT
F17
VCC
POWER
C08
GND
GROUND
F18
NC
NO CONNECT
A03
NC
NO CONNECT
C09
DATA[6]
LVTTL IN PU
F19
NC
NO CONNECT
A04
A05
NC
NO CONNECT
C10
DATA[4]
LVTTL IN PU
F20
NC
NO CONNECT
VCC
POWER
C11
DATA[2]
LVTTL IN PU
G01
GND
GROUND
Signal Type
A06
INB1–
CML IN
C12
DATA[0]
LVTTL IN PU
G02
WREN
LVTTL IN PU
A07
ROUTB1–
CML OUT
C13
GND
GROUND
G03
GND
GROUND
A08
GND
GROUND
C14
NC
NO CONNECT
G04
GND
GROUND
A09
INB2–
CML IN
C15
SPDSELB
3-LEVEL SEL
G17
NC
NO CONNECT
A10
ROUTB2–
CML OUT
C16
VCC
POWER
G18
NC
NO CONNECT
A11
INA1–
CML IN
C17
LDTDEN
LVTTL IN PU
G19
SPDSELA
3-LEVEL SEL
A12
ROUTA1–
CML OUT
C18
TRST
LVTTL IN PU
G20
NC
NO CONNECT
A13
GND
GROUND
C19
GND
GROUND
H01
GND
GROUND
A14
INA2–
CML IN
C20
TDO
LVTTL 3-S OUT
H02
GND
GROUND
A15
ROUTA2–
CML OUT
D01
TCLK
LVTTL IN PD
H03
GND
GROUND
A16
VCC
POWER
D02
RESET
LVTTL IN PU
H04
GND
GROUND
A17
VCC
POWER
D03
INSELB
LVTTL IN
H17
GND
GROUND
A18
NC
NO CONNECT
D04
INSELA
LVTTL IN
H18
GND
GROUND
A19
VCC
POWER
D05
VCC
POWER
H19
GND
GROUND
A20
NC
NO CONNECT
D06
ULCA
LVTTL IN PU
H20
GND
GROUND
B01
VCC
POWER
D07
NC
NO CONNECT
J01
GND
GROUND
B02
NC
NO CONNECT
D08
GND
GROUND
J02
GND
GROUND
B03
VCC
POWER
D09
DATA[5]
LVTTL IN PU
J03
GND
GROUND
B04
NC
NO CONNECT
D10
DATA[3]
LVTTL IN PU
J04
GND
GROUND
B05
VCC
POWER
D11
DATA[1]
LVTTL IN PU
J17
NC
NO CONNECT
B06
INB1+
CML IN
D12
GND
GROUND
J18
NC
NO CONNECT
B07
ROUTB1+
CML OUT
D13
GND
GROUND
J19
NC
NO CONNECT
B08
GND
GROUND
D14
GND
GROUND
J20
NC
NO CONNECT
B09
INB2+
CML IN
D15
NC
NO CONNECT
K01
NC
NO CONNECT
B10
ROUTB2+
CML OUT
D16
VCC
POWER
K02
NC
NO CONNECT
B11
INA1+
CML IN
D17
NC
NO CONNECT
K03
GND
GROUND
B12
ROUTA1+
CML OUT
D18
VCC
POWER
K04
GND
GROUND
B13
GND
GROUND
D19
SCANEN2
LVTTL IN PD
K17
NC
NO CONNECT
B14
INA2+
CML IN
D20
TMEN3
LVTTL IN PD
K18
NC
NO CONNECT
B15
ROUTA2+
CML OUT
E01
VCC
POWER
K19
NC
NO CONNECT
B16
VCC
POWER
E02
VCC
POWER
K20
NC
NO CONNECT
B17
NC
NO CONNECT
E03
VCC
POWER
L01
NC
NO CONNECT
B18
NC
NO CONNECT
E04
VCC
POWER
L02
NC
NO CONNECT
B19
NC
NO CONNECT
E17
VCC
POWER
L03
NC
NO CONNECT
B20
NC
NO CONNECT
E18
VCC
POWER
L04
GND
GROUND
C01
TDI
LVTTL IN PU
E19
VCC
POWER
L17
NC
NO CONNECT
C02
TMS
LVTTL IN PU
E20
VCC
POWER
L18
NC
NO CONNECT
C03
VCC
POWER
F01
NC
NO CONNECT
L19
NC
NO CONNECT
Document #: 38-02103 Rev. *C
Page 21 of 24
[+] Feedback
CYV15G0204RB
Table 6. Package Coordinate Signal Allocation (continued)
Ball
ID
Signal Name
Signal Type
Ball
ID
Signal Name
Signal Type
Ball
ID
Signal Name
Signal Type
C04
VCC
POWER
F02
NC
NO CONNECT
L20
GND
GROUND
C05
VCC
POWER
F03
VCC
POWER
M01
NC
NO CONNECT
C06
ULCB
LVTTL IN PU
F04
VCC
POWER
M02
NC
NO CONNECT
M03
NC
NO CONNECT
U03
VCC
POWER
W03
LFIB
LVTTL OUT
M04
NC
NO CONNECT
U04
VCC
POWER
W04
RXCLKB–
LVTTL OUT
M17
NC
NO CONNECT
U05
VCC
POWER
W05
VCC
POWER
M18
NC
NO CONNECT
U06
RXDB[4]
LVTTL OUT
W06
RXDB[6]
LVTTL OUT
M19
NC
NO CONNECT
U07
RXDB[3]
LVTTL OUT
W07
RXDB[0]
LVTTL OUT
M20
GND
GROUND
U08
GND
GROUND
W08
GND
GROUND
N01
GND
GROUND
U09
GND
GROUND
W09
ADDR [2]
LVTTL IN PU
N02
GND
GROUND
U10
ADDR [0]
LVTTL IN PU
W10
ADDR [1]
LVTTL IN PU
N03
GND
GROUND
U11
TRGCLKB–
PECL IN
W11
RXCLKA+
LVTTL OUT
N04
GND
GROUND
U12
GND
GROUND
W12
REPDOA
LVTTL OUT
N17
GND
GROUND
U13
GND
GROUND
W13
GND
GROUND
N18
GND
GROUND
U14
GND
GROUND
W14
GND
GROUND
N19
GND
GROUND
U15
VCC
POWER
W15
VCC
POWER
N20
GND
GROUND
U16
VCC
POWER
W16
VCC
POWER
P01
NC
NO CONNECT
U17
RXDA[4]
LVTTL OUT
W17
LFIA
LVTTL OUT
P02
NC
NO CONNECT
U18
VCC
POWER
W18
TRGCLKA+
PECL IN
P03
NC
NO CONNECT
U19
BISTSTA
LVTTL OUT
W19
RXDA[6]
LVTTL OUT
P04
NC
NO CONNECT
U20
RXDA[0]
LVTTL OUT
W20
RXDA[3]
LVTTL OUT
P17
GND
GROUND
V01
VCC
POWER
Y01
VCC
POWER
P18
GND
GROUND
V02
VCC
POWER
Y02
VCC
POWER
P19
GND
GROUND
V03
VCC
POWER
Y03
RXDB[9]
LVTTL OUT
P20
GND
GROUND
V04
RXDB[8]
LVTTL OUT
Y04
RXCLKB+
LVTTL OUT
R01
NC
NO CONNECT
V05
VCC
POWER
Y05
VCC
POWER
R02
NC
NO CONNECT
V06
RXDB[5]
LVTTL OUT
Y06
RXDB[7]
LVTTL OUT
R03
NC
NO CONNECT
V07
RXDB[1]
LVTTL OUT
Y07
RXDB[2]
LVTTL OUT
R04
NC
NO CONNECT
V08
GND
GROUND
Y08
GND
GROUND
R17
VCC
POWER
V09
BISTSTB
LVTTL OUT
Y09
RECLKOB
LVTTL OUT
NO CONNECT
R18
VCC
POWER
V10
GND
GROUND
Y10
NC
R19
VCC
POWER
V11
TRGCLKB+
PECL IN
Y11
GND
GROUND
R20
VCC
POWER
V12
RECLKOA
LVTTL OUT
Y12
RXCLKA–
LVTTL OUT
T01
VCC
POWER
V13
GND
GROUND
Y13
GND
GROUND
T02
VCC
POWER
V14
GND
GROUND
Y14
GND
GROUND
T03
VCC
POWER
V15
VCC
POWER
Y15
VCC
POWER
T04
VCC
POWER
V16
VCC
POWER
Y16
VCC
POWER
T17
VCC
POWER
V17
RXDA[9]
LVTTL OUT
Y17
REPDOB
LVTTL OUT
T18
VCC
POWER
V18
RXDA[5]
LVTTL OUT
Y18
TRGCLKA–
PECL IN
T19
VCC
POWER
V19
RXDA[2]
LVTTL OUT
Y19
RXDA[8]
LVTTL OUT
T20
VCC
POWER
V20
RXDA[1]
LVTTL OUT
Y20
RXDA[7]
LVTTL OUT
U01
VCC
POWER
W01
VCC
POWER
U02
VCC
POWER
W02
VCC
POWER
Document #: 38-02103 Rev. *C
Page 22 of 24
[+] Feedback
CYV15G0204RB
Ordering Information
Speed
Ordering Code
Package
Name
Operating
Range
Package Type
Standard
CYV15G0204RB-BGC
BL256
256-Ball Thermally Enhanced Ball Grid Array
Commercial
Standard
CYV15G0204RB-BGXC
BL256
Pb-Free 256-Ball Thermally Enhanced Ball Grid Array
Commercial
Package Diagram
Figure 3. 256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256
TOP VIEW
0.20(4X)
BOTTOM VIEW (BALL SIDE)
A
27.00±0.13
Ø0.15 M C
Ø0.30 M C
A1 CORNER I.D.
A
B
24.13
A1 CORNER I.D.
Ø0.75±0.15(256X)
14
15
12
13
10
11
8
9
6
7
4
5
27.00±0.13
R 2.5 Max (4X)
A
2
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
12.065
16
17
24.13
18
19
1.27
20
W
Y
0.50 MIN.
B
A
1.57±0.175
0.97 REF.
0.15
26°
TYP.
0.60±0.10
C
0.15
C
C
0.20 MIN
TOP OF MOLD COMPOUND
TO TOP OF BALLS
SEATING PLANE
SIDE VIEW
SECTION A-A
51-85123-*E
HOTLink is a registered trademark and HOTLink II and MultiFrame are trademarks of Cypress Semiconductor. All product and
company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-02103 Rev. *C
Page 23 of 24
© Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CYV15G0204RB
Document History Page
Document Title: CYV15G0204RB Independent Clock Dual HOTLink II™ Reclocking Deserializer
Document Number: 38-02103
REV.
ECN NO.
ISSUE
DATE
ORIG. OF
CHANGE
**
246850
See ECN
FRE
New Data Sheet
*A
338721
See ECN
SUA
Added Pb-Free package option availability
*B
384307
See ECN
AGT
Revised setup and hold times (tRXDV- tRXDV+ tRXDV+)
*C
1034083
See ECN
UKK
Added clarification for the necessity of JTAG controller reset and the
methods to implement it.
Document #: 38-02103 Rev. *C
DESCRIPTION OF CHANGE
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