CYV15G0404RB
Independent Clock Quad HOTLink II™
Deserializing Reclocker
Features
• Second-generation HOTLink® technology
• Compliant to SMPTE 292M and SMPTE 259M video
standards
• Quad channel video reclocking deserializer
— 195 to 1500 Mbps serial data signaling rate
— Simultaneous operation at different signaling rates
• Supports reception of either 1.485 or 1.485/1.001 Gbps data
rate with the same training clock
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external PLL
components
• Selectable differential PECL-compatible serial inputs
•
•
•
•
— Internal DC restoration
Synchronous LVTTL parallel interface
JTAG boundary scan
Built-In Self-Test (BIST) for at-speed link testing
Link Quality Indicator
— Analog signal detect
•
•
•
•
•
— Digital signal detect
Low-power: 3W @ 3.3V typical
Single 3.3V supply
Thermally enhanced BGA
Pb-Free package option available
0.25µ BiCMOS technology
The CYV15G0404RB is SMPTE-259M and SMPTE-292M
compliant according to SMPTE EG34-1999 Pathological Test
Requirements.
As a second generation HOTLink device, the
CYV15G0404RB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data and BIST) with other HOTLink
devices.
Each channel of the CYV15G0404RB Quad HOTLink II device
accepts a serial bit-stream from one of two selectable
PECL-compatible differential line receivers, and using a
completely integrated Clock and Data Recovery PLL, recovers
the timing information necessary for data reconstruction. The
device reclocks and retransmits recovered bit-stream through
the reclocker serial outputs. It also deserializes the recovered
serial data and presents it to the destination host system.
Each channel contains an independent BIST pattern checker.
This BIST hardware enables at speed testing of the
high-speed serial data paths in each receive section of this
device, each transmit section of a connected HOTLink II
device, and across the interconnecting links.
Functional Description
The CYV15G0404RB Independent Clock Quad HOTLink II™
Deserializing Reclocker is a point-to-point or point-to-multipoint communications building block enabling data transfer
over a variety of high speed serial links including SMPTE 292
Cypress Semiconductor Corporation
Document #: 38-02102 Rev. *C
and SMPTE 259 video applications. It supports signaling rates
in the range of 195 to 1500 Mbps for each serial link. The four
channels are independent and can simultaneously operate at
different rates. Each receive channel accepts serial data and
converts it to 10-bit parallel characters and presents these
characters to an Output Register. The received serial data can
also be reclocked and retransmitted through the reclocker
serial outputs. Figure 1, "HOTLink II™ System Connections,"
on page 2 illustrates typical connections between independent
video coprocessors and corresponding CYV15G0404RB
Reclocking Deserializer and CYV15G0403TB Serializer chips.
•
The CYV15G0404RB is ideal for SMPTE applications where
different data rates and serial interface standards are
necessary for each channel. Some applications include
multi-format routers, switchers, format converters, SDI
monitors, and camera control units.
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 16, 2007
[+] Feedback
CYV15G0404RB
Figure 1. HOTLink II™ System Connections
Reclocked
Outputs
10
10
Video Coprocessor
Independent
Channel
CYV15G0403TB
Serializer
10
Independent
Channel
CYV15G0404RB
Reclocking Deserializer
Serial Links
Video Coprocessor
10
10
10
10
10
Reclocked
Outputs
TRGCLKD±
RXDD[9:0]
TRGCLKC±
RXDC[9:0]
TRGCLKB±
RXDB[9:0]
RXDA[9:0]
TRGCLKA±
CYV15G0404RB Deserializing Reclocker Logic Block Diagram
Deserializer
RX
Reclocker
RX
Reclocker
RX
Reclocker
Document #: 38-02102 Rev. *C
RX
IND1±
IND2±
Reclocker
ROUTD1±
ROUTD2±
Deserializer
INC1±
INC2±
Deserializer
ROUTC1±
ROUTC2±
Deserializer
INB1±
INB2±
x10
ROUTB1±
ROUTB2±
x10
INA1±
INA2±
x10
ROUTA1±
ROUTA2±
x10
Page 2 of 27
[+] Feedback
CYV15G0404RB
Reclocking Deserializer Path Block Diagram
= Internal Signal
RESET
TRST
TRGRATEA
JTAG
Boundary
Scan
Controller
x2
TRGCLKA
SDASEL[2..1]A[1:0]
TMS
TCLK
TDI
TDO
LDTDEN
Clock &
Data
Recovery
PLL
INA2+
INA2–
ULCA
10
10
Output
Register
INA1+
INA1–
Shifter
INSELA
BIST LFSR
LFIA
Receive
Signal
Monitor
10
BISTSTA
÷2
SPDSELA
RXDA[9:0]
RXCLKA+
RXCLKA–
RXBISTA[1:0]
RXRATEA
RXPLLPDA
Recovered Character Clock
Recovered Serial Data
Reclocker
Output PLL
Clock Multiplier A
RECLKOA
Register
ROE[2..1]A
ROE[2..1]A
ROUTA1+
ROUTA1–
ROUTA2+
ROUTA2–
Character-Rate Clock A
REPDOA
TRGRATEB
x2
TRGCLKB
SDASEL[2..1]B[1:0]
LDTDEN
Clock &
Data
Recovery
PLL
INB2+
INB2–
ULCB
10
10
Output
Register
INB1+
INB1–
Shifter
INSELB
BIST LFSR
LFIB
Receive
Signal
Monitor
10
BISTSTB
÷2
SPDSELB
RXDB[9:0]
RXCLKB+
RXCLKB–
RXBISTB[1:0]
RXRATEB
RXPLLPDB
Recovered Character Clock
Recovered Serial Data
Reclocker
Output PLL
Clock Multiplier B
RECLKOB
ROE[2..1]B
Register
ROE[2..1]B
ROUTB1+
ROUTB1–
ROUTB2+
ROUTB2–
Character-Rate Clock B
REPDOB
Document #: 38-02102 Rev. *C
Page 3 of 27
[+] Feedback
CYV15G0404RB
Reclocking Deserializer Path Block Diagram (continued)
= Internal Signal
TRGRATEC
x2
TRGCLKC
SDASEL[2..1]C[1:0]
LDTDEN
Clock &
Data
Recovery
PLL
INC2+
INC2–
ULCC
10
10
Output
Register
INC1+
INC1–
Shifter
INSELC
BIST LFSR
LFIC
Receive
Signal
Monitor
10
BISTSTC
÷2
SPDSELC
RXDC[9:0]
RXCLKC+
RXCLKC–
RXBISTC[1:0]
RXRATEC
RXPLLPDC
Recovered Character Clock
Recovered Serial Data
Reclocker
Output PLL
Clock Multiplier C
RECLKOC
Register
ROE[2..1]C
ROE[2..1]C
ROUTC1+
ROUTC1–
ROUTC2+
ROUTC2–
Character-Rate Clock C
REPDOC
TRGRATED
x2
TRGCLKD
SDASEL[2..1]D[1:0]
LDTDEN
Clock &
Data
Recovery
PLL
IND2+
IND2–
ULCD
10
10
Output
Register
IND1+
IND1–
Shifter
INSELD
BIST LFSR
LFID
Receive
Signal
Monitor
10
BISTSTD
÷2
SPDSELD
RXDD[9:0]
RXCLKD+
RXCLKD–
RXBISTD[1:0]
RXRATED
RXPLLPDD
Recovered Character Clock
Recovered Serial Data
Reclocker
Output PLL
Clock Multiplier D
RECLKOD
ROE[2..1]D
Register
ROE[2..1]D
ROUTD1+
ROUTD1–
ROUTD2+
ROUTD2–
Character-Rate Clock D
REPDOD
Document #: 38-02102 Rev. *C
Page 4 of 27
[+] Feedback
CYV15G0404RB
Device Configuration and Control Block Diagram
WREN
ADDR[3:0]
Device Configuration
and Control Interface
DATA[7:0]
Document #: 38-02102 Rev. *C
= Internal Signal
RXBIST[A..D]
RXRATE[A..D]
SDASEL[A..D][1:0]
RXPLLPD[A..D]
ROE[2..1][A..D]
GLEN[11..0]
FGLEN[2..0]
Page 5 of 27
[+] Feedback
CYV15G0404RB
Pin Configuration (Top View)[1]
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
IN
C1–
ROUT
C1–
IN
C2–
ROUT
C2–
VCC
IN
D1–
ROUT
D1–
GND
IN
D2–
ROUT
D2–
IN
A1–
ROUT
A1–
GND
IN
A2–
ROUT
A2–
VCC
IN
B1–
ROUT
B1–
IN
B2–
ROUT
B2–
IN
C1+
ROUT
C1+
IN
C2+
ROUT
C2+
VCC
IN
D1+
ROUT
D1+
GND
IN
D2+
ROUT
D2+
IN
A1+
ROUT
A1+
GND
IN
A2+
ROUT
A2+
VCC
IN
B1+
ROUT
B1+
IN
B2+
ROUT
B2+
TDI
TMS
INSELC INSELB
VCC
ULCD
ULCC
GND
DATA
[7]
DATA
[5]
DATA
[3]
DATA
[1]
GND
VCC
SPD
SELD
VCC
LDTD
EN
TRST
GND
TDO
RESET INSELD INSELA
VCC
ULCA
SPD
SELC
GND
DATA
[6]
DATA
[4]
DATA
[2]
DATA
[0]
GND
GND
ULCB
VCC
NC
VCC
SCAN TMEN3
EN2
TCLK
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RX
DC[8]
RX
DC[9]
VCC
VCC
VCC
RX
DB[0]
RE
CLKOB
RX
DB[1]
GND
WREN
GND
GND
SPD
SELB
NC
SPD
SELA
RX
DB[3]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
BIST
STB
RX
DB[2]
RX
DB[7]
RX
DB[4]
RX
DC[4]
TRG
CLKC–
GND
GND
RX
DB[5]
RX
DB[6]
RX
DB[9]
LFIB
RX
DC[5]
TRG
CLKC+
LFIC
GND
RX
DB[8]
RX
DC[6]
RX
DC[7]
VCC
RE
PDOC
GND
GND
GND
GND
GND
RX
DC[3]
RX
DC[2]
RX
DC[1]
RX
DC[0]
BIST
STC
RX
RX
CLKB+ CLKB–
TRG
TRG
CLKB+ CLKB–
RE
RX
RX
CLKOC CLKC+ CLKC–
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RX
DD[4]
RX
DD[3]
GND
GND
ADDR
TRG
[0]
CLKD–
VCC
VCC
VCC
RX
DD[8]
VCC
RX
DD[5]
RX
DD[1]
GND
BIST
STD
VCC
VCC
LFID
RX
CLKD–
VCC
RX
DD[6]
RX
DD[0]
GND
VCC
VCC
RX
DD[9]
RX
CLKD+
VCC
RX
DD[7]
RX
DD[2]
GND
GND
RE
PDOB
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
VCC
VCC
RX
DA[4]
VCC
BIST
STA
RX
DA[0]
ADDR
TRG
RE
[2]
CLKD+ CLKOA
GND
GND
VCC
VCC
RX
DA[9]
RX
DA[5]
RX
DA[2]
RX
DA[1]
ADDR
[3]
ADDR
[1]
RX
CLKA+
RE
PDOA
GND
GND
VCC
VCC
LFIA
TRG
CLKA+
RX
DA[6]
RX
DA[3]
RE
CLKOD
NC
GND
RX
CLKA–
GND
GND
VCC
VCC
RE
TRG
PDOD CLKA–
RX
DA[8]
RX
DA[7]
GND
Note
1. NC = Do not connect.
Document #: 38-02102 Rev. *C
Page 6 of 27
[+] Feedback
CYV15G0404RB
Pin Configuration (Bottom View)[1]
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
ROUT
B2–
IN
B2–
ROUT
B1–
IN
B1–
VCC
ROUT
A2–
IN
A2–
GND
ROUT
A1–
IN
A1–
ROUT
D2–
IN
D2–
GND
ROUT
D1–
IN
D1–
VCC
ROUT
C2–
IN
C2–
ROUT
C1–
IN
C1–
B
ROUT
B2+
IN
B2+
ROUT
B1+
IN
B1+
VCC
ROUT
A2+
IN
A2+
GND
ROUT
A1+
IN
A1+
ROUT
D2+
IN
D2+
GND
ROUT
D1+
IN
D1+
VCC
ROUT
C2+
IN
C2+
ROUT
C1+
IN
C1+
C
TDO
GND
TRST
LDTD
EN
VCC
SPD
SELD
VCC
GND
DATA
[1]
DATA
[3]
DATA
[5]
DATA
[7]
GND
ULCC
ULCD
VCC
INSELB INSELC
TMS
TDI
TMEN3 SCAN
EN2
VCC
NC
VCC
ULCB
GND
GND
DATA
[0]
DATA
[2]
DATA
[4]
DATA
[6]
GND
SPD
SELC
ULCA
VCC
INSELA INSELD RESET
D
TCLK
E
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
F
RX
DB[1]
RE
CLKOB
RX
DB[0]
VCC
VCC
VCC
RX
DC[9]
RX
DC[8]
G
RX
DB[3]
SPD
SELA
NC
SPD
SELB
GND
GND
WREN
GND
H
GND
GND
GND
GND
GND
GND
GND
GND
J
RX
DB[4]
RX
DB[7]
RX
DB[2]
BIST
STB
GND
GND
GND
GND
K
LFIB
RX
DB[9]
RX
DB[6]
RX
DB[5]
GND
GND
TRG
CLKC–
RX
DC[4]
L
GND
RX
RX
CLKB– CLKB+
RX
DB[8]
GND
LFIC
TRG
CLKC+
RX
DC[5]
M
GND
RE
PDOB
TRG
TRG
CLKB– CLKB+
RE
PDOC
VCC
RX
DC[7]
RX
DC[6]
N
GND
GND
GND
GND
GND
GND
GND
GND
P
GND
GND
GND
GND
RX
DC[0]
RX
DC[1]
RX
DC[2]
RX
DC[3]
R
VCC
VCC
VCC
VCC
T
VCC
VCC
VCC
VCC
U
RX
DA[0]
BIST
STA
VCC
RX
DA[4]
VCC
VCC
GND
GND
V
RX
DA[1]
RX
DA[2]
RX
DA[5]
RX
DA[9]
VCC
VCC
GND
W
RX
DA[3]
RX
DA[6]
TRG
CLKA+
LFIA
VCC
VCC
Y
RX
DA[7]
RX
DA[8]
TRG
RE
CLKA– PDOD
VCC
VCC
Document #: 38-02102 Rev. *C
RX
RX
RE
CLKC– CLKC+ CLKOC
BIST
STC
VCC
VCC
VCC
VCC
TRG
ADDR
CLKD–
[0]
GND
GND
RX
DD[3]
RX
DD[4]
VCC
VCC
VCC
VCC
VCC
GND
RE
TRG
ADDR
CLKOA CLKD+
[2]
BIST
STD
GND
RX
DD[1]
RX
DD[5]
VCC
RX
DD[8]
VCC
VCC
VCC
GND
GND
RE
PDOA
RX
CLKA+
ADDR
[1]
ADDR
[3]
GND
RX
DD[0]
RX
DD[6]
VCC
RX
CLKD–
LFID
VCC
VCC
GND
GND
RX
CLKA–
GND
NC
RE
CLKOD
GND
RX
DD[2]
RX
DD[7]
VCC
RX
CLKD+
RX
DD[9]
VCC
VCC
GND
Page 7 of 27
[+] Feedback
CYV15G0404RB
Pin Definitions
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
Name
IO Characteristics
Signal Description
Receive Path Data and Status Signals
RXDA[9:0]
RXDB[9:0]
RXDC[9:0]
RXDD[9:0]
LVTTL Output,
synchronous to the
RXCLK± output
Parallel Data Output. RXDx[9:0] parallel data outputs change relative to the
receive interface clock. If RXCLKx± is a full-rate clock, the RXCLKx± clock outputs
are complementary clocks operating at the character rate. The RXDx[9:0] outputs
for the associated receive channels follow the rising edge of RXCLKx+ or the
falling edge of RXCLKx–. If RXCLKx± is a half-rate clock, the RXCLKx± clock
outputs are complementary clocks operating at half the character rate. The
RXDx[9:0] outputs for the associated receive channels follow both the falling and
rising edges of the associated RXCLKx± clock outputs.
When BIST is enabled on the receive channel, the RXDx[1:0] and BISTSTx
outputs present the BIST status. See Table 5, “Receive BIST Status Bits,” on
page 17 for each status that the BIST state machine reports. Also, while BIST is
enabled, ignore the RXDx[9:2] outputs.
BISTSTA
BISTSTB
BISTSTC
BISTSTD
LVTTL Output,
synchronous to the
RXCLKx± output
REPDOA
REPDOB
REPDOC
REPDOD
Asynchronous to
reclocker output
channel
enable / disable
BIST Status Output. When RXBISTx[1:0] = 10, BISTSTx (along with RXDx[1:0])
displays the status of the BIST reception. See Table 5, “Receive BIST Status Bits,”
on page 17 for the BIST status for each combination of BISTSTx and RXDx[1:0].
When RXBISTx[1:0] ≠ 10, ignore BISTSTx.
Reclocker Powered Down Status Output. REPDOx asserts HIGH when the
associated channel’s reclocker output logic powers down. This occurs when
disabling ROE2x and ROE1x by setting ROE2x = 0 and ROE1x = 0.
Receive Path Clock Signals
TRGCLKA±
TRGCLKB±
TRGCLKC±
TRGCLKD±
Differential LVPECL or CDR PLL Training Clock. The frequency detector (Range Controller) of the
single-ended
associated receive PLL uses the TRGCLKx± clock inputs as the reference source
LVTTL input clock
to reduce PLL acquisition time.
In the presence of valid serial data, the recovered clock output of the receive CDR
PLL (RXCLKx±) has no frequency or phase relationship with TRGCLKx±.
When a single-ended LVCMOS or LVTTL clock source drives the clock, connect
the clock source to either the true or complement TRGCLKx input, and leave the
alternate TRGCLKx input open (floating). When an LVPECL clock source drives
it, the clock must be a differential clock, using both inputs.
RXCLKA±
RXCLKB±
RXCLKC±
RXCLKD±
LVTTL Output Clock
Receive Clock Output. RXCLKx± is the receive interface clock that controls
timing of the RXDx[9:0] parallel outputs. These true and complement clocks
control timing of data output transfers. These clocks output continuously at either
the half-character rate (1/20 the serial bit-rate) or character rate (1/10 the serial
bit-rate) of the data being received, as selected by RXRATEx.
RECLKOA
RECLKOB
RECLKOC
RECLKOD
LVTTL Output
Reclocker Clock Output. The associated reclocker output PLL synthesizes the
RECLKOx output clock, which operates synchronous to the internal recovered
character clock. RECLKOx operates at either the same frequency as RXCLKx±
(RXRATEx = 0), or at twice the frequency of RXCLKx± (RXRATEx = 1). The
reclocker clock outputs have no fixed phase relationship to RXCLKx±.
Device Control Signals
RESET
LVTTL Input,
asynchronous,
internal pull up
Document #: 38-02102 Rev. *C
Asynchronous Device Reset. RESET initializes all state machines, counters,
and configuration latches in the device to a known state. RESET must assert LOW
for a minimum pulse width. When the reset is removed, all state machines,
counters and configuration latches are at an initial state. According to the JTAG
specifications, the device RESET cannot reset the JTAG controller. Therefore, the
JTAG controller has to be reset separately. Refer to “JTAG Support” on page 17
for the methods to reset the JTAG state machine. See Table 3, “Device Configuration and Control Latch Descriptions,” on page 14 for the initialize values of the
device configuration latches.
Page 8 of 27
[+] Feedback
CYV15G0404RB
Pin Definitions (continued)
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
Name
IO Characteristics
Signal Description
LDTDEN
LVTTL Input,
internal pull up
Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal
Level Detector, Range Controller, and Transition Density Detector are all enabled
to determine if the RXPLL tracks TRGCLKx± or the selected input serial data
stream. If the Signal Level Detector, Range Controller, or Transition Density
Detector are out of their respective limits while LDTDEN is HIGH, the RXPLL locks
to TRGCLKx± until they become valid. The SDASEL[A..D][1:0] inputs configure
the trip level of the Signal Level Detector. The Transition Density Detector limit is
one transition in every 60 consecutive bits. When LDTDEN is LOW, only the
Range Controller determines if the RXPLL tracks TRGCLKx± or the selected input
serial data stream. Set LDTDEN = HIGH.
ULCA
ULCB
ULCC
ULCD
LVTTL Input,
internal pull up
Use Local Clock. When ULCx is LOW, the RXPLL locks to TRGCLKx± instead
of the received serial data stream. While ULCx is LOW, the LFIx for the associated
channel is LOW, indicating a link fault.
When ULCx is HIGH, the RXPLL performs Clock and Data Recovery functions on
the input data streams. This function is used in applications that need a stable
RXCLKx±. When valid data transitions are absent for a long time, or the high-gain
differential serial inputs (INx±) are left floating, the RXCLKx± outputs may briefly
be different from TRGCLKx±.
SPDSELA
SPDSELB
SPDSELC
SPDSELD
3-Level Select[2]
static control input
Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate
range of each channel’s receive PLL.
LOW = 195–400 MBd
MID = 400–800 MBd
HIGH = 800–1500 MBd.
INSELA
INSELB
INSELC
INSELD
LVTTL Input,
asynchronous
Receive Input Selector. The INSELx input determines which external serial bit
stream passes to the receiver’s Clock and Data Recovery circuit. When INSELx
is HIGH, the Primary Differential Serial Data Input, INx1±, is the associated receive
channel. When INSELx is LOW, the Secondary Differential Serial Data Input,
INx2±, is the associated receive channel.
LFIA
LFIB
LFIC
LFID
LVTTL Output,
asynchronous
Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the
logical OR of six internal conditions. LFIx asserts LOW when any of the following
conditions is true:
• Received serial data rate is outside expected range
• Analog amplitude is below expected levels
• Transition density is lower than expected
• Receive is channel disabled
• ULCx is LOW
• TRGCLKx± is absent.
Device Configuration and Control Bus Signals
WREN
LVTTL input,
asynchronous,
internal pull up
Control Write Enable. The WREN input writes the values of the DATA[7:0] bus
into the latch specified by the address location on the ADDR[3:0] bus.[3]
ADDR[3:0]
LVTTL input
asynchronous,
internal pull up
Control Addressing Bus. The ADDR[3:0] bus is the input address bus that
configures the device. The WREN input writes the values of the DATA[7:0] bus
into the latch specified by the address location on the ADDR[3:0] bus.[3] Table 3,
“Device Configuration and Control Latch Descriptions,” on page 14 lists the configuration latches within the device, and the initialization value of the latches when
RESET is asserted. Table 4, “Device Control Latch Configuration Table,” on
page 16 shows how the latches are mapped in the device.
Notes
2. Use 3-Level Select inputs for static configuration. These are ternary inputs that use logic levels of LOW, MID, and HIGH. To implement the LOW level, connect
directly to VSS (ground). To implement the HIGH level, connect directly to VCC (power). To implement the MID level, do not connect the input (leave floating),
which allows it to self bias to the proper level.
3. See “Device Configuration and Control Interface” on page 13 for detailed information about the operation of the Configuration Interface.
Document #: 38-02102 Rev. *C
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Pin Definitions (continued)
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
Name
DATA[7:0]
IO Characteristics
LVTTL input
asynchronous,
internal pull-up
Signal Description
Control Data Bus. The DATA[7:0] bus is the input data bus that configures the
device. The WREN input writes the values of the DATA[7:0] bus into the latch
specified by address location on the ADDR[3:0] bus.[3] Table 3, “Device Configuration and Control Latch Descriptions,” on page 14 lists the configuration latches
within the device, and the initialization value of the latches when RESET is
asserted. Table 4, “Device Control Latch Configuration Table,” on page 16 shows
the way the latches are mapped in the device.
Internal Device Configuration Latches
RXRATE[A..D]
Internal Latch[4]
[4]
SDASEL[2..1][A..D] Internal Latch
[1:0]
RXPLLPD[A..D]
RXBIST[A..D][1:0]
ROE2[A..D]
Internal Latch[4]
Internal Latch
Receive Clock Rate Select.
Signal Detect Amplitude Select.
Receive Channel Power Control.
[4]
Receive BIST Disabled.
[4]
Reclocker Differential Serial Output Driver 2 Enable.
[4]
Internal Latch
ROE1[A..D]
Internal Latch
Reclocker Differential Serial Output Driver 1 Enable.
GLEN[11..0]
Internal Latch[4]
Global Latch Enable.
FGLEN[2..0]
[4]
Internal Latch
Force Global Latch Enable.
Factory Test Modes
SCANEN2
LVTTL input,
internal pull down
Factory Test 2. The SCANEN2 input is for factory testing only. Leave this input
as a NO CONNECT, or GND only.
TMEN3
LVTTL input,
internal pull down
Factory Test 3. The TMEN3 input is for factory testing only. Leave this input as a
NO CONNECT, or GND only.
ROUTA1±
ROUTB1±
ROUTC1±
ROUTD1±
CML Differential
Output
Primary Differential Serial Data Output. The ROUTx1± PECL-compatible CML
outputs (+3.3V referenced) can drive terminated transmission lines or standard
fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.
ROUTA2±
ROUTB2±
ROUTC2±
ROUTD2±
CML Differential
Output
Secondary Differential Serial Data Output. The ROUTx2± PECL-compatible
CML outputs (+3.3V referenced) are capable of driving terminated transmission
lines or standard fiber-optic transmitter modules, and must be AC coupled for
PECL-compatible connections.
INA1±
INB1±
INC1±
IND1±
Differential Input
Primary Differential Serial Data Input. The INx1± input accepts the serial data
stream for deserialization. The INx1± serial stream passes to the receive CDR
circuit to extract the data content when INSELx = HIGH.
INA2±
INB2±
INC2±
IND2±
Differential Input
Secondary Differential Serial Data Input. The INx2± input accepts the serial
data stream for deserialization. The INx2± serial stream passes to the receiver
CDR circuit to extract the data content when INSELx = LOW.
TMS
LVTTL Input,
internal pull up
Test Mode Select. Controls access to the JTAG Test Modes. If TMS is HIGH for
>5 TCLK cycles, the JTAG test controller resets.
TCLK
LVTTL Input,
internal pull down
JTAG Test Clock.
Analog I/O
JTAG Interface
Note
4. See Device Configuration and Control Interface for detailed information on the internal latches.
Document #: 38-02102 Rev. *C
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Pin Definitions (continued)
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
Name
IO Characteristics
Signal Description
TDO
3-State LVTTL Output
Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not
selected.
TDI
LVTTL Input,
internal pull up
Test Data In. JTAG data input port.
TRST
LVTTL Input,
internal pull up
JTAG reset signal. When asserted (LOW), this input asynchronously resets the
JTAG test access port controller.
Power
VCC
+3.3V Power.
GND
Signal and Power Ground for all internal circuits.
CYV15G0404RB HOTLink II Operation
The CYV15G0404RB is a highly configurable, independent
clocking, quad-channel reclocking deserializer that supports
reliable transfer of large quantities of digital video data, using
high-speed serial links from multiple sources to multiple destinations. This device supports four 10-bit channels.
CYV15G0404RB Receive Data Path
Serial Line Receivers
Two differential Line Receivers, INx1± and INx2±, are
available on each channel to accept serial data streams. The
associated INSELx input selects the active Serial Line
Receiver on a channel. The Serial Line Receiver inputs are
differential, and can accommodate wire interconnect and
filtering losses or transmission line attenuation greater than
16 dB. For normal operation, these inputs must receive a
signal of at least VIDIFF > 100 mV, or 200 mV peak-to-peak
differential. Each Line Receiver can be DC or AC coupled to
+3.3V powered fiber-optic interface modules (any ECL/PECL
family, not limited to 100K PECL) or AC coupled to +5V
powered optical modules. The common mode tolerance of
these line receivers accommodates a wide range of signal
termination voltages. Each receiver provides internal DC
restoration, to the center of the receiver’s common mode
range, for AC coupled signals.
Signal Detect/Link Fault
Each selected Line Receiver (that is, that routed to the clock
and data recovery PLL) is simultaneously monitored for
• Analog amplitude above amplitude level selected by
SDASELx
• Transition density above the specified limit
• Range controls reporting the received data stream inside
normal frequency range (±1500 ppm[21])
• Receive channel enabled
• Reference clock present
• ULCx not asserted.
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFIx (Link Fault Indicator) output associated with each
receive channel, which changes synchronous to the receive
interface clock.
Analog Amplitude
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable to allow
operation with highly attenuated signals, or in high noise
environments. The SDASELx latch sets the analog amplitude
level detection via the device configuration interface. The
SDASELx latch sets the trip point for the detection of a valid
signal at one of three levels, as listed in Table 1. This control
input affects the analog monitors for all receive channels. The
Analog Signal Detect monitors are active for the Line Receiver,
as selected by the associated INSELx input.
Table 1. Analog Amplitude Detect Valid Signal Levels[5]
SDASEL Typical Signal with Peak Amplitudes Above
00
Analog Signal Detector is disabled
01
140 mV p-p differential
10
280 mV p-p differential
11
420 mV p-p differential
Transition Density
The Transition Detection logic checks for the absence of
transitions spanning greater than six transmission characters
(60 bits). If there are no transitions in the data received, the
Detection logic for that channel asserts LFIx.
Range Controls
The CDR circuit includes logic to monitor the frequency of the
PLL Voltage Controlled Oscillator (VCO) samples the
incoming data stream. This logic ensures that the VCO
Note
5. The peak amplitudes listed in this table are for typical waveforms that generally have 3–4 transitions for every ten bits. In a worst case environment the signals
may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase
the values in the table above by approximately 100 mV.
Document #: 38-02102 Rev. *C
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CYV15G0404RB
operates at, or near the rate of the incoming data stream for
two primary cases:
• When the incoming data stream resumes after a time in
which it was “missing.”
• When the incoming data stream is outside the acceptable
signaling rate range.
To perform this function, periodically compare the frequency of
the RXPLL VCO to the frequency of the TRGCLKx± input. If
the VCO is running at a frequency beyond ±1500 ppm[21] as
defined by the TRGCLKx± frequency, it is periodically forced
to the correct frequency (as defined by TRGCLKx±, SPDSELx,
and TRGRATEx) and then released in an attempt to lock to the
input data stream.
Calculate the sampling and relock period of the Range Control
as follows: RANGE_CONTROL_SAMPLING_PERIOD =
(RECOVERED BYTE CLOCK PERIOD) * (4096).
During the time that the Range Control forces the RXPLL VCO
to track TRGCLKx±, the LFIx output is asserted LOW. After a
valid serial data stream is applied, it may take up to one
RANGE CONTROL SAMPLING PERIOD before the PLL
locks to the input data stream, after which LFIx is HIGH.
Table 2 lists the operating serial signaling rate and allowable
range of TRGCLK± frequencies.
Table 2. Operating Speed Settings
SPDSELx
TRGRATEx
TRGCLKx±
Frequency
(MHz)
Signaling
Rate (Mbps)
LOW
1
Reserved
195–400
0
19.5–40
MID (Open)
1
20–40
0
40–80
HIGH
1
40–75
0
80–150
400–800
800–1500
Receive Channel Enabled
The CYV15G0404RB contains four receive channels that it
can independently enable and disable. Each channel are
enabled or disabled separately through the RXPLLPDx input
latch as controlled by the device configuration interface.
RXPLLPDx latch = 0 disables the associated PLL and analog
circuitry of the channel. Any disabled channel indicates a
constant link fault condition on the LFIx output. RXPLLPDx =
1 enables the associated PLL and receive channel to receive
a serial stream.
Note When a disabled receive channel is reenabled, the
status of the associated LFIx output and data on the parallel
outputs for the associated channel may be indeterminate for
up to 2 ms.
Clock/Data Recovery
A separate CDR block within each receive channel performs
the extraction of a bit rate clock and recovery of bits from each
received serial stream. An integrated PLL that tracks the
frequency of the transitions in the incoming bit stream and
aligns the phase of the internal bit rate clock to the transitions
Document #: 38-02102 Rev. *C
in the selected serial data stream performs the clock extraction
function.
Each CDR accepts a character-rate (bit-rate ÷ 10) or
half-character-rate (bit-rate ÷ 20) training clock from the
associated TRGCLKx± input. This TRGCLKx± input is used to
• Ensure that the VCO (within the CDR) is operating at the
correct frequency (rather than a harmonic of the bit rate)
• Reduce PLL acquisition time
• Limit unlocked frequency excursions of the CDR VCO when
there is no input data present at the selected Serial Line
Receiver.
Regardless of the type of signal present, the CDR attempts to
recover a data stream from it. If the signaling rate of the
recovered data stream is outside the limits set by the range
control monitors, the CDR tracks TRGCLKx± instead of the
data stream. Once the CDR output (RXCLK±) frequency
returns close to TRGCLKx± frequency, the CDR input
switches back to the input data stream. If no data is present at
the selected line receiver, this switching behavior may cause
brief RXCLK± frequency excursions from TRGCLKx±.
However, the LFIx output indicates the validity of the input data
stream. The frequency of TRGCLKx± must be within ±1500
ppm[21] of the frequency of the clock that drives the reference
clock input of the remote transmitter, to ensure a lock to the
incoming data stream. This large ppm tolerance allows the
CDR PLL to reliably receive a 1.485 or 1.485/1.001 Gbps
SMPTE HD-SDI data stream with a constant TRGCLK
frequency.
For systems using multiple or redundant connections, use the
LFIx output to select an alternate data stream. When the
device detects an LFIx indication, external logic toggles
selection of the associated INx1± and INx2± input through the
associated INSELx input. When a port switch takes place, the
receive PLL for that channel reacquires the new serial stream.
Reclocker
Each receive channel performs a reclocker function on the
incoming serial data. To do this, the Clock and Data Recovery
PLL first recovers the clock from the data. The recovered clock
retimes the data and then passes it to an output register. It also
passes the recovered character clock from the receive PLL to
the reclocker output PLL, which generates the bit clock that
clocks the retimed data into the output register. This data
stream is then transmitted through the differential serial
outputs.
Reclocker Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for 50Ω transmission lines. These drivers accept data from the
reclocker output register in the reclocker channel. These
drivers have signal swings equivalent to that of standard PECL
drivers, and can drive AC coupled optical modules or transmission lines.
Reclocker Output Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled using the configuration interface, it
internally powers down to reduce device power. If both
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CYV15G0404RB
reclocker serial drivers for a channel are in this disabled state,
the associated internal reclocker logic also powers down. The
deserialization logic and parallel outputs remain enabled. A
device reset (RESET sampled LOW) disables all output
drivers.
Note When the disabled reclocker function (that is, both
outputs disabled) is reenabled, the data on the reclocker serial
outputs may not meet all timing specifications for up to 250 µs.
Output Bus
Each receive channel presents a 10-bit data signal (and a
BIST status signal when RXBISTx[1:0] = 10).
Receive BIST Operation
Each receiver channel contains an internal pattern checker
that is used to validate both device and link operation. These
pattern checkers are enabled by the associated RXBISTx[1:0]
latch through the device configuration interface. When
enabled, a register in the associated receive channel becomes
a signature pattern generator and checker by logically
converting to a Linear Feedback Shift Register (LFSR). This
LFSR generates a 511-character sequence. This provides a
predictable, yet pseudorandom, sequence that can be
matched to an identical LFSR in the attached Transmitter(s).
When synchronized with the received data stream, the
associated Receiver checks each character from the deserializer with each character generated by the LFSR and
indicates compare errors and BIST status at the RXDx[1:0]
and BISTSTx bits of the Output Register.
The BIST status bus {BISTSTx, RXDx[0], RXDx[1]} indicates
010b or 100b for one character period per BIST loop to
indicate loop completion. Use this status to check test pattern
progress.
Table 5, “Receive BIST Status Bits,” on page 17 lists the
specific status reported by the BIST state machine. The
receive status outputs report these same codes.
If the number of invalid characters received exceeds the
number of valid characters by 16, the receive BIST state
machine aborts the compare operations and resets the LFSR
to look for the start of the BIST sequence again.
A device reset (RESET sampled LOW) presets the BIST
Enable Latches to disable BIST on all channels.
BIST Status State Machine
When a receive path is enabled to look for and compare the
received data stream with the BIST pattern, the {BISTSTx,
RXDx[0], RXDx[1]} bits identify the present state of the BIST
compare operation.
The BIST state machine has multiple states, as shown in
Figure 2, "Receive BIST State Machine," on page 18 and
Table 5, “Receive BIST Status Bits,” on page 17. When the
receive PLL detects an out-of-lock condition, it forces the BIST
state to the Start-of-BIST state, regardless of the present state
of the BIST state machine. If the number of detected errors
ever exceeds the number of valid matches by greater than 16,
the state machine is forced to the WAIT_FOR_BIST state,
where it monitors the receive path for the first character of the
next BIST sequence.
Document #: 38-02102 Rev. *C
Power Control
The CYV15G0404RB supports user control of the powered up
or down state of each transmit and receive channel. The
RXPLLPDx latch controls the receive channels through the
device configuration interface. RXPLLPDx = 0 disables the
associated PLL and analog circuitry of the channel. The OE1x
and the OE2x latches control the transmit channels via the
device configuration interface. The ROE1x and the ROE2x
latches control the reclocker function through the device
configuration interface. When the configuration interface
disables a driver, the driver internally powers down to reduce
device power. If both serial drivers for a channel are in this
disabled state, the associated internal logic for that channel
also powers down. The reclocker serial drivers being disabled
in turn disables the reclocker function, but the deserialization
logic and parallel outputs remain enabled.
Device Reset State
Assertion of RESET resets all state machines, counters, and
configuration latches in the device to a reset state.
Additionally, the JTAG controller must be reset for valid
operation (even if not performing JTAG testing). See “JTAG
Support” on page 17 for JTAG state machine initialization. See
Table 3, “Device Configuration and Control Latch Descriptions,” on page 14 for the initialize values of the configuration
latches.
Following a device reset, enable the receive channels used for
normal operation. Do this by sequencing the appropriate
values on the device configuration interface.[3]
Device Configuration and Control Interface
Configure the CYV15G0404RB through the configuration
interface. The configuration interface enables the device to be
configured globally or enables each channel to be configured
independently. Table 3, “Device Configuration and Control
Latch Descriptions,” on page 14 lists the configuration latches
within the device, including the initialization value of the
latches on the assertion of RESET. Table 4, “Device Control
Latch Configuration Table,” on page 16 shows how the latches
are mapped in the device. Each row in Table 4 maps to an 8-bit
latch bank. There are 16 such write only latch banks. When
WREN = 0, the logic value in the DATA[7:0] latches to the latch
bank specified by the values in ADDR[3:0]. The second
column of Table 4 specifies the channels associated with the
corresponding latch bank. For example, the first three latch
banks (0, 1, and 2) consist of configuration bits for channel A.
Latch banks 12, 13, and 14 consist of Global configuration bits,
and the last latch bank (15) is the Mask latch bank, which can
be configured to perform bit-by-bit configuration.
Global Enable Function
The global enable function, controlled by the GLENx bits, is a
feature that can reduce the number of write operations needed
to set up the latch banks. This function is beneficial in systems
that use a common configuration in multiple channels. The
GLENx bit is present in bit 0 of latch banks 0 through 11 only.
Its default value (1) enables the global update of the latch
bank's contents. Setting the GLENx bit to 0 disables this
functionality.
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CYV15G0404RB
Latch Banks 12, 13, and 14 load values in the related latch
banks in globally. A write operation to latch bank 12 performs
a global write to latch banks 0, 3, 6, and 9, depending on the
value of GLENx in these latch banks; latch bank 13 performs
a global write to latch banks 1, 4, 7, and 10; and latch bank 14
performs a global write to latch banks 2, 5, 8, and 11. The
GLENx bit cannot be modified by a global write operation.
Force Global Enable Function
FGLENx forces the global update of the target latch banks, but
does not change the contents of the GLENx bits. If FGLENx =
1 for the associated global channel, FGLENx forces the global
update of the target latch banks.
Mask Function
An additional latch bank (15) is a global mask vector that
controls the update of the configuration latch banks on a
bit-by-bit basis. A logic 1 in a bit location enables the update
of that same location of the target latch bank(s), whereas a
logic 0 disables it. The reset value of this latch bank is FFh,
thereby making its use optional by default. The mask latch
bank is not maskable. The bit 0 value of the mask latch bank
does not affect the FGLEN functionality.
Latch Types
latch banks. The S type contains those settings that normally
do not change for a given application, whereas the D type
controls the settings that might change during the application's
lifetime. The first and second rows of each channel (address
numbers 0, 1, 3, 4, 6, 7, 9, and 10) are the static control
latches. The third row of latches for each channel (address
numbers 2, 5, 8, and 11) are the dynamic control latches that
are associated with enabling dynamic functions within the
device.
Latch Bank 14 is also useful for those users that do not need
the latch based programmable feature of the device. This latch
bank is used in those applications that do not need to modify
the default value of the static latch banks, and that can afford
global (that is, not independent) control of the dynamic signals.
In this case, this feature becomes available when ADDR[3:0]
is unchanged with a value of “1110” and WREN is asserted.
The signals present in DATA[7:0] effectively become global
control pins, and for the latch banks 2, 5, 8, and 11.
Static Latch Values
There are some latches in the table that have a static value
(that is, 1, 0, or X). The latches that have a ‘1’ or ‘0’ must be
configured with their corresponding value each time that their
associated latch bank is configured. The latches that have an
‘X’ are don’t cares and can be configured with any value
There are two types of latch banks: static (S) and dynamic (D).
Each channel is configured by two static and one dynamic
Table 3. Device Configuration and Control Latch Descriptions
Name
Signal Description
RXRATEA
RXRATEB
RXRATEC
RXRATED
Receive Clock Rate Select. The initialization value of the RXRATEx latch = 1. RXRATEx selects the rate
of the RXCLKx± clock output.
When RXRATEx = 1, the RXCLKx± clock outputs are complementary clocks that follow the recovered
clock operating at half the character rate. Data for the associated receive channels must latch alternately
on the rising edge of RXCLKx+ and RXCLKx–.
When RXRATEx = 0, the RXCLKx± clock outputs are complementary clocks that follow the recovered
clock operating at the character rate. Data for the associated receive channels must latch on the rising
edge of RXCLKx+ or falling edge of RXCLKx–.
SDASEL1A[1:0]
SDASEL1B[1:0]
SDASEL1C[1:0]
SDASEL1D[1:0]
Primary Serial Data Input Signal Detector Amplitude Select. The initialization value of the
SDASEL1x[1:0] latch = 10. SDASEL1x[1:0] selects the trip point for the detection of a valid signal for the
INx1± Primary Differential Serial Data Inputs.
When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled.
When SDASEL1x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.
When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.
When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.
SDASEL2A[1:0]
SDASEL2B[1:0]
SDASEL2C[1:0]
SDASEL2D[1:0]
Secondary Serial Data Input Signal Detector Amplitude Select. The initialization value of the
SDASEL2x[1:0] latch = 10. SDASEL2x[1:0] selects the trip point for the detection of a valid signal for the
INx2± Secondary Differential Serial Data Inputs.
When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled
When SDASEL2x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.
When SDASEL2x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.
When SDASEL2x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.
TRGRATEA
TRGRATEB
TRGRATEC
TRGRATED
Training Clock Rate Select. The initialization value of the TRGRATEx latch = 0. TRGRATEx selects the
clock multiplier for the training clock input to the associated CDR PLL. When TRGRATEx = 0, the
associated TRGCLKx± input is not multiplied before it is passed to the CDR PLL. When TRGRATEx = 1,
the TRGCLKx± input is multiplied by 2 before it is passed to the CDR PLL. TRGRATEx = 1 and SPDSELx
= LOW is an invalid state and this combination is reserved.
Document #: 38-02102 Rev. *C
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CYV15G0404RB
Table 3. Device Configuration and Control Latch Descriptions (continued)
Name
Signal Description
RXPLLPDA
RXPLLPDB
RXPLLPDC
RXPLLPDD
Receive Channel Enable. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects whether
the associated receive channel is enabled or powered down. RXPLLPDx = 0 powers down the associated
receive PLL and analog circuitry. RXPLLPDx = 1 enables the associated receive PLL and analog circuitry.
RXBISTA[1:0]
RXBISTB[1:0]
RXBISTC[1:0]
RXBISTD[1:0]
Receive Bist Disable / SMPTE Receive Enable. The initialization value of the RXBISTx[1:0] latch = 11.
For SMPTE data reception, RXBISTx[1:0] should not remain in this initialization state (11). RXBISTx[1:0]
selects whether receive BIST is disabled or enabled and sets the associated channel for SMPTE data
reception. RXBISTx[1:0] = 01 disables the receiver BIST function and sets the associated channel to
receive SMPTE data. RXBISTx[1:0] = 10 enables the receive BIST function and sets the associated
channel to receive BIST data. RXBISTx[1:0] = 00 and RXBISTx[1:0] = 11 are invalid states.
ROE2A
ROE2B
ROE2C
ROE2D
Reclocker Secondary Differential Serial Data Output Driver Enable. The initialization value of the
ROE2x latch = 0. ROE2x selects whether the ROUT2± secondary differential output drivers are enabled
or disabled. ROE2x = 1 enables the associated serial data output driver, allowing data to be transmitted
from the transmit shifter. ROE2x = 0 disables the associated serial data output driver. When the configuration interface disables a driver, the driver internally powers down to reduce device power. If both serial
drivers for a channel are in this disabled state, the associated internal logic for that channel also powers
down. A device reset (RESET sampled LOW) disables all output drivers.
ROE1A
ROE1B
ROE1C
ROE1D
Reclocker Primary Differential Serial Data Output Driver Enable. The initialization value of the ROE1x
latch = 0. ROE1x selects whether the ROUT1± primary differential output drivers are enabled or disabled.
ROE1x = 1 enables the associated serial data output driver, allowing data to be transmitted from the
transmit shifter. ROE1x = 0 disables the associated serial data output driver. When the configuration
interface disables a driver, the driver internally powers down to reduce device power. If both serial drivers
for a channel are in this disabled state, the associated internal logic for that channel also powers down.
A device reset (RESET sampled LOW) disables all output drivers.
GLEN[11..0]
Global Enable. The initialization value of the GLENx latch = 1. The GLENx reconfigures several channels
simultaneously in applications where several channels may have the same configuration. When GLENx
= 1 for a given address, that address can participate in a global configuration. When GLENx = 0 for a
given address, that address cannot participate in a global configuration.
FGLEN[2..0]
Force Global Enable. The initialization value of the FGLENx latch is NA. The FGLENx latch forces a
GLobal ENable no matter what the setting is on the GLENx latch. If FGLENx = 1 for the associated Global
channel, FGLEN forces the global update of the target latch banks.
Device Configuration Strategy
Follow these steps to load the configuration latches on each
channel:
1. Pulse RESET Low after device power up. This operation
resets all four channels. Initialize the JTAG state machine
to its reset state, as detailed in “JTAG Support” on page 17.
2. Set the static latch banks for the target channel. You can
perform this step using a global operation, if the application
Document #: 38-02102 Rev. *C
permits it. [This is an optional step if the default settings
match the desired configuration.]
3. Set the dynamic bank of latches for the target channel.
Enable the Receive PLLs and set each channel for SMPTE
data reception (RXBISTx[1:0] = 01) or BIST data reception
(RXBISTx[1:0] = 10). You can perform this step using a
global operation, if the application permits it. [Required
step.]
Page 15 of 27
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CYV15G0404RB
Table 4. Device Control Latch Configuration Table
ADDR Channel Type
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Reset
Value
0
(0000b)
A
S
1
0
X
X
0
0
RXRATEA
GLEN0
10111111
1
(0001b)
A
S
SDASEL2A[1]
SDASEL2A[0]
SDASEL1A[1]
SDASEL1A[0]
X
X
TRGRATEA
GLEN1
10101101
2
(0010b)
A
D
RXBISTA[1]
RXPLLPDA
RXBISTA[0]
X
ROE2A
ROE1A
X
GLEN2
10110011
3
(0011b)
B
S
1
0
X
X
0
0
RXRATEB
GLEN3
10111111
4
(0100b)
B
S
SDASEL2B[1]
SDASEL2B[0]
SDASEL1B[1]
SDASEL1B[0]
X
X
TRGRATEB
GLEN4
10101101
5
(0101b)
B
D
RXBISTB[1]
RXPLLPDB
RXBISTB[0]
X
ROE2B
ROE1B
X
GLEN5
10110011
6
(0110b)
C
S
1
0
X
X
0
0
RXRATEC
GLEN6
10111111
7
(0111b)
C
S
SDASEL2C[1]
SDASEL2C[0]
SDASEL1C[1]
SDASEL1C[0]
X
X
TRGRATEC
GLEN7
10101101
8
(1000b)
C
D
RXBISTC[1]
RXPLLPDC
RXBISTC[0]
X
ROE2C
ROE1C
X
GLEN8
10110011
9
(1001b)
D
S
1
0
X
X
0
0
RXRATED
GLEN9
10111111
10
(1010b)
D
S
SDASEL2D[1]
SDASEL2D[0]
SDASEL1D[1]
SDASEL1D[0]
X
X
TRGRATED
GLEN10
10101101
11
(1011b)
D
D
RXBISTD[1]
RXPLLPDD
RXBISTD[0]
X
ROE2D
ROE1D
X
GLEN11
10110011
12
GLOBAL
(1100b)
S
1
0
X
X
0
0
RXRATEGL
FGLEN0
N/A
13
GLOBAL
(1101b)
S
X
X
TRGRATEGL
FGLEN1
N/A
14
GLOBAL
(1110b)
D
RXBISTGL[1]
RXPLLPDGL
RXBISTGL[0]
X
ROE2GL
ROE1GL
X
FGLEN2
N/A
15
(1111b)
D
D7
D6
D5
D4
D3
D2
D1
D0
11111111
MASK
SDASEL2GL[1] SDASEL2GL[0] SDASEL1GL[1] SDASEL1GL[0]
Document #: 38-02102 Rev. *C
Page 16 of 27
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CYV15G0404RB
JTAG Support
The CYV15G0404RB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan and bypass are supported. This
capability is present only on the LVTTL inputs and outputs and
the TRGCLKx± clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain.
To ensure valid device operation after power-up (including
non-JTAG operation), the JTAG state machine must also be
initialized to a reset state. This must be done in addition to the
device reset (using RESET). Initialize the JTAG state machine
using TRST (assert it LOW and deassert it or leave it
asserted), or by asserting TMS HIGH for at least 5 consecutive
TCLK cycles. This is necessary in order to ensure that the
JTAG controller does not enter any of the test modes after
device power-up. In this JTAG reset state, the rest of the
device will operate normally.
Note The order of device reset (using RESET) and JTAG
initialization does not matter.
3-Level Select Inputs
Each 3-Level select input reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11 respectively
JTAG ID
The JTAG device ID for the CYV15G0404RB is ‘0C811069’x.
Table 5. Receive BIST Status Bits
Description
{BISTSTx, RXDx[0],
RXDx[1]}
000, 001
010
Receive BIST Status
(Receive BIST = Enabled)
BIST Data Compare. Character compared correctly.
BIST Last Good. Last Character of BIST sequence detected and valid.
011
Reserved.
100
BIST Last Bad. Last Character of BIST sequence detected invalid.
101
BIST Start. Receive BIST is enabled on this channel, but character compares have not yet
commenced. This also indicates a PLL Out of Lock condition.
110
BIST Error. While comparing characters, a mismatch was found in one or more of the character bits.
111
BIST Wait. The receiver is comparing characters, but has not yet found the start of BIST character to
enable the LFSR.
Document #: 38-02102 Rev. *C
Page 17 of 27
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CYV15G0404RB
Figure 2. Receive BIST State Machine
Monitor Data
Received
Receive BIST
{BISTSTx, RXDx[0], Detected LOW
RXDx[1]} =
BIST_START (101)
RX PLL
Out of Lock
{BISTSTx, RXDx[0], RXDx[1]} =
BIST_WAIT (111)
Start of
BIST Detected
No
Yes, {BISTSTx, RXDx[0], RXDx[1]} =
BIST_DATA_COMPARE (000, 001)
Compare
Next Character
Mismatch
Yes
Match
Auto-Abort
Condition
{BISTSTx, RXDx[0], RXDx[1]} =
BIST_DATA_COMPARE (000, 001)
No
End-of-BIST
State
End-of-BIST
State
Yes, {BISTSTx, RXDx[0], RXDx[1]} =
BIST_LAST_BAD (100)
Yes, {BISTSTx, RXDx[0], RXDx[1]} =
BIST_LAST_GOOD (010)
No
No, {BISTSTx, RXDx[0], RXDx[1]} =
BIST_ERROR (110)
Document #: 38-02102 Rev. *C
Page 18 of 27
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CYV15G0404RB
Maximum Ratings
Static Discharge Voltage.......................................... > 2000 V
(MIL-STD-883, Method 3015)
Excedding maximum ratings may shorten the device life. User
guidelines are not tested
Latch Up Current .................................................... > 200 mA
Storage Temperature .................................. –65°C to +150°C
Power Up Requirements
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
The CYV15G0404RB requires one power supply. The voltage
on any input or I/O pin cannot exceed the power pin during
power up.
Supply Voltage to Ground Potential ............... –0.5V to +3.8V
DC Voltage Applied to LVTTL Outputs
in High-Z State .......................................–0.5V to VCC + 0.5V
Output Current into LVTTL Outputs (LOW)..................60 mA
Operating Range
Range
Ambient Temperature
VCC
Commercial
0°C to +70°C
+3.3V ±5%
DC Input Voltage....................................–0.5V to VCC + 0.5V
CYV15G0404RB DC Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
LVTTL-compatible Outputs
VOHT
Output HIGH Voltage
IOH = −4 mA, VCC = Min.
VOLT
Output LOW Voltage
IOL = 4 mA, VCC = Min.
0V[6],
IOST
Output Short Circuit Current
VOUT =
VCC = 3.3V
IOZL
High-Z Output Leakage Current
VOUT = 0V, VCC
2.4
V
0.4
V
–20
–100
mA
–20
20
µA
LVTTL-compatible Inputs
VIHT
Input HIGH Voltage
2.0
VCC + 0.3
V
VILT
Input LOW Voltage
–0.5
0.8
V
IIHT
Input HIGH Current
TRGCLKx Input, VIN = VCC
1.5
mA
Other Inputs, VIN = VCC
+40
µA
TRGCLKx Input, VIN = 0.0V
–1.5
mA
Other Inputs, VIN = 0.0V
–40
µA
Input LOW Current
IILT
IIHPDT
Input HIGH Current with Internal Pull Down VIN = VCC
+200
µA
IILPUT
Input LOW Current with Internal Pull Up
–200
µA
VCC
mV
VIN = 0.0V
LVDIFF Inputs: TRGCLKx±
VDIFF[7]
Input Differential Voltage
400
VIHHP
Highest Input HIGH Voltage
1.2
VCC
V
VILLP
Lowest Input LOW voltage
0.0
VCC/2
V
Common Mode Range
1.0
VCC – 1.2V
V
VCOMREF
[8]
3-Level Inputs
VIHH
Three-Level Input HIGH Voltage
Min. ≤ VCC ≤ Max.
0.87 * VCC
VCC
V
VIMM
Three-Level Input MID Voltage
Min. ≤ VCC ≤ Max.
0.47 * VCC
0.53 * VCC
V
VILL
Three-Level Input LOW Voltage
Min. ≤ VCC ≤ Max.
0.0
0.13 * VCC
V
IIHH
Input HIGH Current
VIN = VCC
200
µA
IIMM
Input MID current
VIN = VCC/2
IILL
Input LOW current
VIN = GND
–50
50
µA
–200
µA
Notes
6. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
7. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the
true (+) input is more positive than the complement (−) input. A logic-0 exists when the complement (−) input is more positive than true (+) input.
8. The common mode range defines the allowable range of TRGCLKx+ and TRGCLKx− when TRGCLKx+ = TRGCLKx−. This marks the zero-crossing between
the true and complement inputs as the signal switches between a logic-1 and a logic-0.
Document #: 38-02102 Rev. *C
Page 19 of 27
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CYV15G0404RB
CYV15G0404RB DC Electrical Characteristics (continued)
Parameter
Description
Test Conditions
Min
Max
Unit
Differential CML Serial Outputs: ROUTA1±, ROUTA2±, ROUTB1±, ROUTB2±, ROUTC1±, ROUTC2±, ROUTD1±, ROUTD2±
VOHC
VOLC
Output HIGH Voltage
(VCC Referenced)
100Ω differential load
VCC – 0.5
VCC – 0.2
V
150Ω differential load
VCC – 0.5
VCC – 0.2
V
Output LOW Voltage
(VCC Referenced)
100Ω differential load
VCC – 1.4
VCC – 0.7
V
150Ω differential load
VCC – 1.4
VCC – 0.7
V
Output Differential Voltage
|(OUT+) − (OUT−)|
VODIF
100Ω differential load
450
900
mV
150Ω differential load
560
1000
mV
1200
mV
VCC
V
Differential Serial Line Receiver Inputs: INA1±, INA2±, INB1±, INB2±, INC1±, INC2±, IND1±, IND2±
VDIFFs[7]
Input Differential Voltage |(IN+) − (IN−)|
VIHE
Highest Input HIGH Voltage
VILE
Lowest Input LOW Voltage
IIHE
Input HIGH Current
VIN = VIHE Max.
Input LOW Current
VIN = VILE Min.
–700
Common Mode input range
((VCC – 2.0V)+0.5)min,
(VCC – 0.5V) max.
+1.25
+3.1
Typ
Max
IILE
VICOM
[9]
100
VCC – 2.0
1350
Power Supply
ICC
[10,11]
Max Power Supply Current
ICC [10,11]
Typical Power Supply Current
V
TRGCLKx = Commercial
MAX
Industrial
910
TRGCLKx = Commercial
125 MHz
Industrial
900
µA
µA
V
1270
mA
1320
mA
1270
mA
1320
mA
AC Test Loads and Waveforms
3.3V
RL = 100Ω
R1
R1 = 590Ω
R2 = 435Ω
CL
CL ≤ 7 pF
(Includes fixture and
probe capacitance)
RL
(Includes fixture and
probe capacitance)
R2
(b) CML Output Test Load
[12]
[12]
(a) LVTTL Output Test Load
3.0V
Vth = 1.4V
GND
2.0V
2.0V
0.8V
0.8V
VIHE
VIHE
Vth = 1.4V
VILE
≤ 1 ns
≤ 1 ns
[13]
(c) LVTTL Input Test Waveform
80%
80%
20%
≤ 270 ps
20%
VILE
≤ 270 ps
(d) CML/LVPECL Input Test Waveform
Notes
9. The common mode range defines the allowable range of INPUT+ and INPUT− when INPUT+ = INPUT−. This marks the zero crossing between the true and
complement inputs as the signal switches between a logic-1 and a logic-0.
10. Maximum ICC is measured with VCC = MAX, TA = 25°C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and
outputs unloaded.
11. Typical ICC is measured under similar conditions except with VCC = 3.3V, TA = 25°C, with all channels enabled and one Serial Line Driver for each transmit
channel sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.
12. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
13. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.
Document #: 38-02102 Rev. *C
Page 20 of 27
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CYV15G0404RB
CYV15G0404RB AC Electrical Characteristics
Parameter
Description
Min
Max
Unit
CYV15G0404RB Receiver LVTTL Switching Characteristics Over the Operating Range
fRS
RXCLKx± Clock Output Frequency
9.75
150
MHz
tRXCLKP
RXCLKx± Period = 1/fRS
6.66
102.56
ns
tRXCLKD
RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate)
–1.0
+1.0
ns
tRXCLKR [14]
RXCLKx± Rise Time
0.3
1.2
ns
RXCLKx± Fall Time
0.3
1.2
ns
tRXCLKF
tRXDv–
[14]
[18]
tRXDv+[18]
5UI–2.0
[19]
ns
Status and Data Valid Time to RXCLKx± (RXRATEx = 1) (Half Rate)
5UI–1.3
[19]
ns
Status and Data Valid Time to RXCLKx± (RXRATEx = 0)
5UI–1.8[19]
ns
Status and Data Valid Time to RXCLKx± (RXRATEx = 1)
[19]
ns
Status and Data Valid Time to RXCLKx± (RXRATEx = 0) (Full Rate)
5UI–2.6
fROS
RECLKOx Clock Frequency
19.5
150
MHz
tRECLKO
RECLKOx Period = 1/fROS
6.66
51.28
ns
tRECLKOD
RECLKOx Duty Cycle centered at 60% HIGH time
–1.9
0
ns
CYV15G0404RB TRGCLKx Switching Characteristics Over the Operating Range
fTRG
TRGCLKx Clock Frequency
19.5
150
MHz
TRGCLK
TRGCLKx Period = 1/fREF
6.6
51.28
ns
tTRGH
TRGCLKx HIGH Time (TRGRATEx = 1)(Half Rate)
5.9
TRGCLKx HIGH Time (TRGRATEx = 0)(Full Rate)
TRGCLKx LOW Time (TRGRATEx = 0)(Full Rate)
tTRGD[20]
tTRGR
[14, 15, 16, 17]
tTRGF[14, 15, 16, 17]
tTRGRX[21]
ns
2.9
TRGCLKx LOW Time (TRGRATEx = 1)(Half Rate)
tTRGL
ns
[14]
5.9
2.9
TRGCLKx Duty Cycle
ns
[14]
ns
70
%
TRGCLKx Rise Time (20%–80%)
2
ns
TRGCLKx Fall Time (20%–80%)
2
ns
+0.15
%
TRGCLKx Frequency Referenced to Received Clock Frequency
30
–0.15
CYV15G0404RB Bus Configuration Write Timing Characteristics Over the Operating Range
tDATAH
Bus Configuration Data Hold
0
ns
tDATAS
Bus Configuration Data Setup
10
ns
tWRENP
Bus Configuration WREN Pulse Width
10
ns
CYV15G0404RB JTAG Test Clock Characteristics Over the Operating Range
fTCLK
JTAG Test Clock Frequency
tTCLK
JTAG Test Clock Period
20
50
MHz
ns
Notes
14. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
15. The ratio of rise time to falling time must not vary by greater than 2:1.
16. For a given operating frequency, neither rise nor fall specification can be greater than 20% of the clock cycle period or the data sheet maximum time.
17. All transmit AC timing parameters measured with 1ns typical rise time and fall time.
18. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
19. Receiver UI (Unit Interval) is calculated as 1/(fTRG * 20) (when TRGRATEx = 1) or 1/(fTRG * 10) (when TRGRATEx = 0). In an operating link this is equivalent to tB.
20. The duty cycle specification is a simultaneous condition with the tREFH and tREFL parameters. This means that at faster character rates the TRGCLKx± duty
cycle cannot be as large as 30%–70%.
21. TRGCLKx± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.
TRGCLKx± must be within ±1500 PPM (±0.15%) of the transmitter PLL reference (REFCLKx±) frequency. Although transmitting to a HOTLink II receiver channel
necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be
within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard.
Document #: 38-02102 Rev. *C
Page 21 of 27
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CYV15G0404RB
CYV15G0404RB AC Electrical Characteristics (continued)
Parameter
Description
Min
Max
Unit
CYV15G0404RB Device RESET Characteristics Over the Operating Range
tRST
Device RESET Pulse Width
30
ns
CYV15G0404RB Reclocker Serial Output Characteristics Over the Operating Range
Parameter
Description
Condition
tB
Bit Time
tRISE[14]
CML Output Rise Time 20−80% (CML Test Load)
tFALL
[14]
CML Output Fall Time 80−20% (CML Test Load)
Min.
Max.
Unit
5128
660
ps
SPDSELx = HIGH
50
270
ps
SPDSELx = MID
100
500
ps
SPDSELx =LOW
180
1000
ps
SPDSELx = HIGH
50
270
ps
SPDSELx = MID
100
500
ps
SPDSELx =LOW
180
1000
ps
PLL Characteristics
Parameter
Description
Condition
Min
Typ
Max
Unit
CYV15G0404RB Reclocker Output PLL Characteristics
tJRGENSD[14, 22]
Reclocker Jitter Generation - SD Data Rate
TRGCLKx = 27 MHz
133
ps
tJRGENHD[14, 22]
Reclocker Jitter Generation - HD Data Rate
TRGCLKx = 148.5 MHz
107
ps
CYV15G0404RB Receive PLL Characteristics Over the Operating Range
tRXLOCK
tRXUNLOCK
Receive PLL Lock to Input Data Stream (cold start)
376k
UI
Receive PLL Lock to Input Data Stream
376k
UI
46
UI
Receive PLL Unlock Rate
Capacitance[14]
Max
Unit
CINTTL
Parameter
TTL Input Capacitance
Description
TA = 25°C, f0 = 1 MHz, VCC = 3.3V
Test Conditions
7
pF
CINPECL
PECL input Capacitance
TA = 25°C, f0 = 1 MHz, VCC = 3.3V
4
pF
Note
22. Receiver input stream is BIST data from the transmit channel. This data is reclocked and output to a wide bandwidth digital sampling oscilloscope. The
measurement was recorded after 10,000 histogram hits, time referenced to REFCLKx± of the transmit channel.
Document #: 38-02102 Rev. *C
Page 22 of 27
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CYV15G0404RB
Switching Waveforms for the CYV15G0404RB HOTLink II Receiver
Receive Interface
Read Timing
tRXCLKP
RXRATEx = 0
RXCLKx+
RXCLKx–
tRXDV–
RXDx[9:0]
tRXDV+
Receive Interface
Read Timing
tRXCLKP
RXRATEx = 1
RXCLKx+
RXCLKx–
tRXDV–
RXDx[9:0]
tRXDV+
CYV15G0404RB HOTLink II Bus Configuration Switching Waveforms
Bus Configuration
Write Timing
ADDR[3:0]
DATA[7:0]
tWRENP
WREN
tDATAS
tDATAH
Document #: 38-02102 Rev. *C
Page 23 of 27
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CYV15G0404RB
Table 6. Package Coordinate Signal Allocation
Ball
ID
Signal Name
Signal Type
Ball
ID
Signal Name
Signal Type
Ball
ID
Signal Name
Signal Type
A01
INC1–
CML IN
C07
ULCC
LVTTL IN PU
F17
VCC
POWER
A02
ROUTC1–
CML OUT
C08
GND
GROUND
F18
RXDB[0]
LVTTL OUT
A03
INC2–
CML IN
C09
DATA[7]
LVTTL IN PU
F19
RECLKOB
LVTTL OUT
A04
ROUTC2–
CML OUT
C10
DATA[5]
LVTTL IN PU
F20
RXDB[1]
LVTTL OUT
A05
VCC
POWER
C11
DATA[3]
LVTTL IN PU
G01
GND
GROUND
A06
IND1–
CML IN
C12
DATA[1]
LVTTL IN PU
G02
WREN
LVTTL IN PU
A07
ROUTD1–
CML OUT
C13
GND
GROUND
G03
GND
GROUND
A08
GND
GROUND
C14
VCC
POWER
G04
GND
GROUND
A09
IND2–
CML IN
C15
SPDSELD
3-LEVEL SEL
G17
SPDSELB
3-LEVEL SEL
A10
ROUTD2–
CML OUT
C16
VCC
POWER
G18
NC
NO CONNECT
A11
INA1–
CML IN
C17
LDTDEN
LVTTL IN PU
G19
SPDSELA
3-LEVEL SEL
A12
ROUTA1–
CML OUT
C18
TRST
LVTTL IN PU
G20
RXDB[3]
LVTTL OUT
A13
GND
GROUND
C19
GND
GROUND
H01
GND
GROUND
A14
INA2–
CML IN
C20
TDO
LVTTL 3-S OUT
H02
GND
GROUND
A15
ROUTA2–
CML OUT
D01
TCLK
LVTTL IN PD
H03
GND
GROUND
A16
VCC
POWER
D02
RESET
LVTTL IN PU
H04
GND
GROUND
A17
INB1–
CML IN
D03
INSELD
LVTTL IN
H17
GND
GROUND
A18
ROUTB1–
CML OUT
D04
INSELA
LVTTL IN
H18
GND
GROUND
A19
INB2–
CML IN
D05
VCC
POWER
H19
GND
GROUND
A20
ROUTB2–
CML OUT
D06
ULCA
LVTTL IN PU
H20
GND
GROUND
B01
INC1+
CML IN
D07
SPDSELC
3-LEVEL SEL
J01
GND
GROUND
B02
ROUTC1+
CML OUT
D08
GND
GROUND
J02
GND
GROUND
B03
INC2+
CML IN
D09
DATA[6]
LVTTL IN PU
J03
GND
GROUND
B04
ROUTC2+
CML OUT
D10
DATA[4]
LVTTL IN PU
J04
GND
GROUND
B05
VCC
POWER
D11
DATA[2]
LVTTL IN PU
J17
BISTSTB
LVTTL OUT
B06
IND1+
CML IN
D12
DATA[0]
LVTTL IN PU
J18
RXDB[2]
LVTTL OUT
B07
ROUTD1+
CML OUT
D13
GND
GROUND
J19
RXDB[7]
LVTTL OUT
B08
GND
GROUND
D14
GND
GROUND
J20
RXDB[4]
LVTTL OUT
B09
IND2+
CML IN
D15
ULCB
LVTTL IN PU
K01
RXDC[4]
LVTTL OUT
B10
ROUTD2+
CML OUT
D16
VCC
POWER
K02
TRGCLKC–
PECL IN
B11
INA1+
CML IN
D17
NC
NO CONNECT
K03
GND
GROUND
B12
ROUTA1+
CML OUT
D18
VCC
POWER
K04
GND
GROUND
B13
GND
GROUND
D19
SCANEN2
LVTTL IN PD
K17
RXDB[5]
LVTTL OUT
B14
INA2+
CML IN
D20
TMEN3
LVTTL IN PD
K18
RXDB[6]
LVTTL OUT
B15
ROUTA2+
CML OUT
E01
VCC
POWER
K19
RXDB[9]
LVTTL OUT
B16
VCC
POWER
E02
VCC
POWER
K20
LFIB
LVTTL OUT
B17
INB1+
CML IN
E03
VCC
POWER
L01
RXDC[5]
LVTTL OUT
B18
ROUTB1+
CML OUT
E04
VCC
POWER
L02
TRGCLKC+
PECL IN
B19
INB2+
CML IN
E17
VCC
POWER
L03
LFIC
LVTTL OUT
Document #: 38-02102 Rev. *C
Page 24 of 27
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CYV15G0404RB
Table 6. Package Coordinate Signal Allocation (continued)
Ball
ID
Signal Name
Signal Type
Ball
ID
Signal Name
Signal Type
Ball
ID
Signal Name
Signal Type
B20
ROUTB2+
CML OUT
E18
VCC
POWER
L04
GND
GROUND
C01
TDI
LVTTL IN PU
E19
VCC
POWER
L17
RXDB[8]
LVTTL OUT
C02
TMS
LVTTL IN PU
E20
VCC
POWER
L18
RXCLKB+
LVTTL OUT
C03
INSELC
LVTTL IN
F01
RXDC[8]
LVTTL OUT
L19
RXCLKB–
LVTTL OUT
C04
INSELB
LVTTL IN
F02
RXDC[9]
LVTTL OUT
L20
GND
GROUND
C05
VCC
POWER
F03
VCC
POWER
M01
RXDC[6]
LVTTL OUT
C06
ULCD
LVTTL IN PU
F04
VCC
POWER
M02
RXDC[7]
LVTTL OUT
M03
VCC
POWER
U03
VCC
POWER
W03
LFID
LVTTL OUT
M04
REPDOC
LVTTL OUT
U04
VCC
POWER
W04
RXCLKD–
LVTTL OUT
M17
TRGCLKB+
PECL IN
U05
VCC
POWER
W05
VCC
POWER
M18
TRGCLKB–
PECL IN
U06
RXDD[4]
LVTTL OUT
W06
RXDD[6]
LVTTL OUT
M19
REPDOB
LVTTL OUT
U07
RXDD[3]
LVTTL OUT
W07
RXDD[0]
LVTTL OUT
M20
GND
GROUND
U08
GND
GROUND
W08
GND
GROUND
N01
GND
GROUND
U09
GND
GROUND
W09
ADDR [3]
LVTTL IN PU
N02
GND
GROUND
U10
ADDR [0]
LVTTL IN PU
W10
ADDR [1]
LVTTL IN PU
N03
GND
GROUND
U11
TRGCLKD–
PECL IN
W11
RXCLKA+
LVTTL OUT
N04
GND
GROUND
U12
GND
GROUND
W12
REPDOA
LVTTL OUT
N17
GND
GROUND
U13
GND
GROUND
W13
GND
GROUND
N18
GND
GROUND
U14
GND
GROUND
W14
GND
GROUND
N19
GND
GROUND
U15
VCC
POWER
W15
VCC
POWER
N20
GND
GROUND
U16
VCC
POWER
W16
VCC
POWER
P01
RXDC[3]
LVTTL OUT
U17
RXDA[4]
LVTTL OUT
W17
LFIA
LVTTL OUT
P02
RXDC[2]
LVTTL OUT
U18
VCC
POWER
W18
TRGCLKA+
PECL IN
P03
RXDC[1]
LVTTL OUT
U19
BISTSTA
LVTTL OUT
W19
RXDA[6]
LVTTL OUT
P04
RXDC[0]
LVTTL OUT
U20
RXDA[0]
LVTTL OUT
W20
RXDA[3]
LVTTL OUT
P17
GND
GROUND
V01
VCC
POWER
Y01
VCC
POWER
P18
GND
GROUND
V02
VCC
POWER
Y02
VCC
POWER
P19
GND
GROUND
V03
VCC
POWER
Y03
RXDD[9]
LVTTL OUT
P20
GND
GROUND
V04
RXDD[8]
LVTTL OUT
Y04
RXCLKD+
LVTTL OUT
R01
BISTSTC
LVTTL OUT
V05
VCC
POWER
Y05
VCC
POWER
R02
RECLKOC
LVTTL OUT
V06
RXDD[5]
LVTTL OUT
Y06
RXDD[7]
LVTTL OUT
R03
RXCLKC+
LVTTL OUT
V07
RXDD[1]
LVTTL OUT
Y07
RXDD[2]
LVTTL OUT
R04
RXCLKC–
LVTTL OUT
V08
GND
GROUND
Y08
GND
GROUND
R17
VCC
POWER
V09
BISTSTD
LVTTL OUT
Y09
RECLKOD
LVTTL OUT
R18
VCC
POWER
V10
ADDR [2]
LVTTL IN PU
Y10
NC
NO CONNECT
R19
VCC
POWER
V11
TRGCLKD+
PECL IN
Y11
GND
GROUND
R20
VCC
POWER
V12
RECLKOA
LVTTL OUT
Y12
RXCLKA–
LVTTL OUT
T01
VCC
POWER
V13
GND
GROUND
Y13
GND
GROUND
T02
VCC
POWER
V14
GND
GROUND
Y14
GND
GROUND
Document #: 38-02102 Rev. *C
Page 25 of 27
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CYV15G0404RB
Table 6. Package Coordinate Signal Allocation (continued)
Ball
ID
Signal Name
Signal Type
Ball
ID
Signal Name
Signal Type
Ball
ID
Signal Name
Signal Type
T03
VCC
POWER
V15
VCC
POWER
Y15
VCC
POWER
T04
VCC
POWER
V16
VCC
POWER
Y16
VCC
POWER
T17
VCC
POWER
V17
RXDA[9]
LVTTL OUT
Y17
REPDOD
LVTTL OUT
T18
VCC
POWER
V18
RXDA[5]
LVTTL OUT
Y18
TRGCLKA–
PECL IN
T19
VCC
POWER
V19
RXDA[2]
LVTTL OUT
Y19
RXDA[8]
LVTTL OUT
T20
VCC
POWER
V20
RXDA[1]
LVTTL OUT
Y20
RXDA[7]
LVTTL OUT
U01
VCC
POWER
W01
VCC
POWER
U02
VCC
POWER
W02
VCC
POWER
Ordering Information
Speed
Ordering Code
Package
Name
Operating
Range
Package Type
Standard
CYV15G0404RB-BGC
BL256
256-Ball Thermally Enhanced Ball Grid Array
Commercial
Standard
CYV15G0404RB-BGXC
BL256
Pb-Free 256-Ball Thermally Enhanced Ball Grid Array
Commercial
Package Diagram
Figure 3. 256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256
TOP VIEW
0.20(4X)
BOTTOM VIEW (BALL SIDE)
A
27.00±0.13
Ø0.15 M C
Ø0.30 M C
A1 CORNER I.D.
A
B
24.13
A1 CORNER I.D.
Ø0.75±0.15(256X)
14
15
12
13
10
11
8
9
6
7
4
5
27.00±0.13
R 2.5 Max (4X)
A
2
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
12.065
16
17
24.13
18
19
1.27
20
W
Y
0.50 MIN.
B
A
1.57±0.175
0.97 REF.
0.15
26°
TYP.
0.60±0.10
C
0.15
C
C
0.20 MIN
TOP OF MOLD COMPOUND
TO TOP OF BALLS
SEATING PLANE
SIDE VIEW
SECTION A-A
51-85123-*E
HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-02102 Rev. *C
Page 26 of 27
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CYV15G0404RB
Document History Page
Document Title: CYV15G0404RB Independent Clock Quad HOTLink II™ Deserializing Reclocker
Document Number: 38-02102
REV.
ECN NO.
ISSUE
DATE
ORIG. OF
CHANGE
**
246850
See ECN
FRE
New Data Sheet
*A
338721
See ECN
SUA
Added Pb-Free package option availability
*B
384307
See ECN
AGT
Revised setup and hold times (tRXDv–, tRXDv+)
*C
789283
See ECN
KKVTMP
Document #: 38-02102 Rev. *C
DESCRIPTION OF CHANGE
Clarification to the need and procedure to initialize the JTAG controller
(during test and non-test mode) to ensure valid device power-up. No
changes have been made to the device specifications or characterestics.
Page 27 of 27
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