深圳市美芯微电子有限公司 麦肯单片机授权一级代理商 MDT14F201 电话；０７５５－３６８５７６０９／２７９４５５５１／２９４９１８８２ 地址：深圳市宝安区宝源路名优产品采购中心Ｂ１区７２１室 1. General Description TMR0: 8-bit timer/counter This Flash ROM-Based 8-bit micro-controller uses a fully TMR1: 16-bit timer/counter static CMOS technology process to achieve higher speed TMR2: 8-bit timer and smaller size with the low power consumption and programming option: IRCInternal 16MHz RC oscillator high noise immunity. On chip memory includes 4K words of ROM, 256 bytes of EEPROM and 192 bytes of static RCLow cost RC oscillator RAM. LFXTLow frequency crystal oscillator XTALStandard crystal oscillator 2. Features The followings are some of the features on the hardware and software: Fully CMOS static design HFXTHigh frequency crystal oscillator On-chip RC oscillator based Watchdog Timer (WDT) 22/24/26/28 I/O pins with their own independent direction control 8-bit data bus On chip FLASH ROM size: 4.0 K words PINS I/O Internal RAM size: 192 bytes Internal EEPROM size: 256 bytes MDT14F201S11 28 24 37 single word instructions MDT14F201K11 28 24 14-bit instructions MDT14F201P11 32 28 8-level stacks MDT14F201LQ11 32 28 OSC AD CH IRC 16M 7 Operating voltage: 2.5 V ~ 5.5 V (PEDH Disable) 4.5 V ~ 5.5 V (PEDH Enable) Operating frequency: DC ~ 20 MHz The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the 5 types of oscillator can be selected by branch instruction Addressing modes include direct, indirect and relative addressing modes PINS I/O MDT14F201S12 28 22 MDT14F201K12 28 22 MDT14F201P12 32 26 MDT14F201LQ12 32 26 OSC AD CH HF, XT, RC, LF 5 3. Applications Power-on Reset Power edge-detector Reset Sleep Mode for power saving The application areas of this MDT14F201 range from Capture, Compare, PWM module appliance motor control and high speed auto-motive to 7 interrupt sources: low power remote transmitters/receivers, pointing -External INT pin devices, and telecommunications processors, such as -TMR0 timer, TMR1 timer, TMR2 timer Remote controller, small instruments, chargers, toy, -A/D conversion completion automobile and PC peripheral … etc. -Port B<7:4> interrupt on change -CCP1 A/D converter module: -5/7 analog inputs multiplexed into one A/D converter -8-bit resolution Preliminary http://www.mxmcu.com.cn P.1 2010/8 Ver. 0.3 MDT14F201 4. Pin Assignment PD2 PD3 /MCLR PA0/AIC0 PA1/AIC1 PA2/AIC2 PA3/AIC3/Vref PA4/T0CKI PA5/AIC4 VSS PA6/AIC5 PA7/AIC6 PC0/T1OSO/T1CKI PC1/T1OSI PC2/CCP PC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PD1 PD0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0/INT VDD VSS PC7 PC6 PC5 PC4 /MCLR PA0/AIC0 PA1/AIC1 PA2/AIC2 PA3/AIC3/Vref PA4/T0CKI PA5/AIC4 VSS PA6/AIC5 PA7/AIC6 PC0/T1OSO/T1CKI PC1/T1OSI PC2/CCP PC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0/INT VDD VSS PC7 PC6 PC5 PC4 MDT14F201K11 (SKINNY) MDT14F201S11 (SOP) PC7 PC6 PC5 PC4 PC3 PC2/CCP PC1/T1OSI PC0/T1OSO/T1CKI MDT14F201P11 (PDIP) 32 31 30 29 28 27 26 25 VSS VDD PB0/INT PB1 PB2 PB3 PB4 PB5 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 10 11 12 13 14 15 16 PB6 PB7 PD0 PD1 PD2 PD3 /MCLR PA0/AIC0 9 PA7/AIC6 PA6/AIC5 VSS PA5/AIC4 PA4/T0CKI PA3/AIC3/Vref PA2/AIC2 PA1/AIC1 MDT14F201LQ11 (LQFP) Preliminary http://www.mxmcu.com.cn P.2 2010/8 Ver. 0.3 MDT14F201 PD2 PD3 /MCLR PA0/AIC0 PA1/AIC1 PA2/AIC2 PA3/AIC3/Vref PA4/T0CKI PA5/AIC4 VSS OSC1 OSC2 PC0/T1OSO/T1CKI PC1/T1OSI PC2/CCP PC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PD1 PD0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0/INT VDD VSS PC7 PC6 PC5 PC4 /MCLR PA0/AIC0 PA1/AIC1 PA2/AIC2 PA3/AIC3/Vref PA4/T0CKI PA5/AIC4 VSS OSC1 OSC2 PC0/T1OSO/T1CKI PC1/T1OSI PC2/CCP PC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0/INT VDD VSS PC7 PC6 PC5 PC4 MDT14F201K12 (SKINNY) MDT14F201S12 (SOP) PC7 PC6 PC5 PC4 PC3 PC2/CCP PC1/T1OSI PC0/T1OSO/T1CKI MDT14F201P12 (PDIP) 32 31 30 29 28 27 26 25 VSS VDD PB0/INT PB1 PB2 PB3 PB4 PB5 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 10 11 12 13 14 15 16 PB6 PB7 PD0 PD1 PD2 PD3 /MCLR PA0/AIC0 9 OSC2 OSC1 VSS PA5/AIC4 PA4/T0CKI PA3/AIC3/Vref PA2/AIC2 PA1/AIC1 MDT14F201LQ12 (LQFP) Preliminary http://www.mxmcu.com.cn P.3 2010/8 Ver. 0.3 MDT14F201 5. Pin Function Description Pin Name I/O Function Description PA0~PA3, PA5 I/O Port A, TTL input level / Analog input channel PA4 I/O PA4, Schmitt Trigger input levels, Open drain output PB0~PB7 I/O Port B, TTL input level / PB0: External interrupt input PB4~PB7: Interrupt on pin change PC0~PC7 I/O Port C, Schmitt Trigger input levels PD0~3 I/O Port D, Schmitt Trigger input levels /MCLR I OSC1/CLKIN/PA6 I, I/O Master Clear, Schmitt Trigger input levels Oscillator Input / external clock input. PA6/ Analog input channel in IRC mode. OSC2/CLKOUT/PA7 O, I/O Oscillator Output / in RC mode, the CLKOUT pin has 1/4 frequency of CLKIN. PA7/ Analog input channel in IRC mode. VDD Power supply VSS Ground Preliminary http://www.mxmcu.com.cn P.4 2010/8 Ver. 0.3 MDT14F201 6. Memory Map (A) Register Map Address Description Address BANK0 Description BANK1 00 IAR 80 IAR 01 RTCC 81 TMR 02 PCL 82 PCL 03 STATUS 83 STATUS 04 MSR 84 MSR 05 Port A 85 CPIO A 06 Port B 86 CPIO B 07 Port C 87 CPIO C 08 Port D 88 CPIO D 09 TTLCTL0 89 TTLCTL1 0A PCHLAT 8A - 0B INTS 8B - 0C PIFB1 8C PIEB1 0D - 8D - 0E TMR1L 8E PSTA 0F TMR1H 8F PAPHR 10 T1STA 90 PBPHR 11 TMR2 91 - 12 T2STA 92 T2PER 13 DBCTL 93 - 94 - 14 15 CCP1L 95 PCPHR 16 CCP1H 96 PDPHR 17 CCP1CTL 97 - 18 - 98 - 19 - 99 - 1A - 9A EEDATA 1B - 9B EEADR 1C - 9C EECON1 1D - 9D EECON2 1E ADRES 9E ADRES 1F ADS0 9F ADS1 20~7F General purpose register A0~FF General purpose register Preliminary http://www.mxmcu.com.cn P.5 2010/8 Ver. 0.3 MDT14F201 (1) IAR (Indirect Address Register): R00 (2) RTCC (Real Time Counter/Counter Register): R01 (3) PC (Program Counter): R02, R0A Write PC --- from PCHLAT A11 Write PC --- from PCHLAT LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK A10~A8 A7~A0 Write PC --- from ALU LJUMP, LCALL --- from instruction word RTWI, RET, RTFI --- from STACK (4) STATUS (Status register): R03 Bit Symbol 0 C 1 HC 2 Z 3 /PF Power down bit 4 /TF WDT timer overflow bit 5 RBS0 Register Bank select bit Function Carry bit Half Carry bit Zero bit 0: 00h~7Fh (Bank0) 1: 80h~FFh (Bank1) 7~6 -- General purpose bit (5) MSR (Memory Bank Select Register): R04 Memory Bank Select Register: 0: 00h~7Fh (Bank0) 1: 80h~FFh (Bank1) b7 b6 b5 b4 b3 b2 b1 b0 Indirect Addressing Mode Preliminary P.6 http://www.mxmcu.com.cn 2010/8 Ver. 0.3 MDT14F201 (6) PORT A: R05 PA5~PA0, I/O Register (7) PORT B: R06 PB7~PB0, I/O Register (8) PORT C: R07 PC7~PC0, I/O Register (9) PORT D:R08 PD3~PD0, I/O Register (10) TTLCTL0: R09 Bit Symbol 0 PB1OUT PB1OUT in TTL MODE circuit 1 PC2OUT PC2OUT in TTL MODE circuit 2 EABS 3 LSOUTS 4 HSOUTS 7~5 Function EABS function enable Low side output active selection High side output active selection Low side Delay time set 000 : 0 clock 001 : 1 clock PRSCLL2~0 : 111 : 7 clocks (11) PCHLAT: R0A (12) INTS (Interrupt Status Register): R0B Bit Symbol Function 0 RBIF PORT B change interrupt flag, Set when PB <7:4> inputs change 1 INTF Set when INT interrupt occurs 2 TIF 3 RBIE Set when TMR0 overflows 0: Disable PB change interrupt 1: Enable PB change interrupt 4 INTS 0: Disable INT interrupt 1: Enable INT interrupt 5 TIS 0: Disable TMR0 interrupt 1: Enable TMR0 interrupt 6 PEIE 0: Disable all peripheral interrupt 1: Enable all peripheral interrupt 7 GIS 0: Disable global interrupt 1: Enable global interrupt Preliminary P.7 http://www.mxmcu.com.cn 2010/8 Ver. 0.3 http://www.mxmcu.com.cn MDT14F201 (13) PIFB1 (Peripheral Interrupt Flag Bit): R0C Bit Symbol 0 TMR1IF Function TMR1 interrupt flag 0: TMR1 did not overflow 1: TMR1 overflowed 1 TMR2IF TMR2 interrupt flag 0: No TMR2 to T2PER match occurred 1: TMR2 to T2PER match occurred 2 CCP1IF CCP1 interrupt flag 0: No TMR1 capture/compare occurred 1: A TMR1 capture/compare occurred 5~3 -- Unimplemented 6 ADIF A/D interrupt flag 0: A/D conversion is not complete 1: A/D conversion completed 7 -- Unimplemented (14) TMR1L: R0E The LSB of the 16-bit TMR1 (15) TMR1H: R0F The MSB of the 16-bit TMR1 Preliminary http://www.mxmcu.com.cn P.8 2010/8 Ver. 0.3 MDT14F201 (16) T1STA: R10 Bit Symbol 0 TMR1ON Function 0: Stop TMR1 1: Enable TMR1 1 TMR1CLK 0: Internal clock (Fosc/4) 1: External clock from pin PC0 2 /T1SYNC TMR1CLK = 1 0: Synchronize external clock 1: Do not synchronize external clock TMR1CLK = 0 This bit is ignored 3 T1OSCEN 0: TMR1 Oscillator is shut off 1: TMR1 Oscillator is enable 5~4 T1CKPS1 1 1 = 1:8 Prescale value ~ 1 0 = 1:4 Prescale value T1CKPS0 0 1 = 1:2 Prescale value 0 0 = 1:1 Prescale value 7~6 -- Unimplemented (17) TMR2: R11 TMR2 register (18) T2STA: R12 Bit Symbol 1~0 T2CKPS1 0 0 = Prescaler is 1 ~ 0 1 = Prescaler is 4 T2CKPS0 1 x = Prescaler is 16 TMR2ON 0: TMR2 is off 2 Function 1: TMR2 is on 7~3 -- Unimplemented Preliminary http://www.mxmcu.com.cn P.9 2010/8 Ver. 0.3 MDT14F201 (19) DBCTL: R13 PB0 input de-bounce control register Bit Symbol 0 DBEN Function 0: Disable PB0 input de-bounce 1: Enable PB0 input de-bounce 4~1 DEBNL3 ~ 7~5 Low pulse de-bounce control If Fosc=16MHz, DEBNL0 detect pulse 0000:0uS, 0001:1uS, 0010:2uS, ~ ,1111:15uS DEBNH2 How pulse de-bounce control ~ DEBNH0 If Fosc=16MHz, detect pulse 000:0uS, 001:1uS, 010:2uS, ~ ,111:7uS (20) CCP1L: R15 Capture/Compare/PWM LSB (21) CCP1H: R16 Capture/Compare/PWM MSB (22) CCP1CTL: R17 Bit Symbol 3~0 CCP1M3 Function 0 0 0 0: CCP1 off ~ 0 1 0 0: Capture1 mode, every falling edge CCP1M0 0 1 0 1: Capture1 mode, every rising edge 0 1 1 0: Capture1 mode, every 4th rising edge 0 1 1 1: Capture1 mode, every 16th rising edge 1 0 0 0: Compare1 mode, set output on match 1 0 0 1: Compare1 mode, clear output on match 1 0 1 0: Compare1 mode, generate software interrupt on match 1 0 1 1: Compare1 mode, trigger special event 1 1 x x: PWM1 mode 5~4 7~6 PWM1LSB These bits are the two LSBs of the PWM1 duty cycle -- Unimplemented Preliminary http://www.mxmcu.com.cn P.10 2010/8 Ver. 0.3 MDT14F201 (23) ADRES: R1E A/D result register (24) ADS0 ( A/D Status Register ): R1F Bit Symbol 0 ADRUN Function 0: A/D converter module is shut off and consumes no operating current 1: A/D converter module is operating 1 2 -- Unimplemented GO/DONEB 0: A/D conversion not in progress 1: A/D conversion in progress 5~3 CHS2~0 000: AIC0 001: AIC1 010: AIC2 011: AIC3 100: AIC4 101: AIC5 110: AIC6 7~6 ASCS1-0 00: fosc/2 01: fosc/8 10: fosc/32 (*Note1) 11: f RC (*Note2) *Note1: for HF or IRC *Note2: determined by OSC mode, HF: fosc/32, XT: fosc/8, RC: fosc/2, LF: fosc/2 (25) TMR (Time Mode Register): R81 Bit Symbol Function Prescaler Value 2~0 PS2~0 3 PSC 4 TCE 5 TCS 6 IES 7 PBPH RTCC rate 1:2 0 0 0 1:4 0 0 1 1:8 0 1 0 1 : 16 0 1 1 1 : 32 1 0 0 1 : 64 1 0 1 1 : 128 1 1 0 1 : 256 1 1 1 Prescaler assignment bit 0: RTCC 1: Watchdog Timer RTCC signal edge 0: Increment on low-to-high transition on RTCC pin 1: Increment on high-to-low transition on RTCC pin RTCC signal set 0: Internal instruction cycle clock 1: Transition on RTCC pin Interrupt edge select 0: Interrupt on falling edge on PB0 1: Interrupt on rising edge on PB0 PORTB7~0 pull-hi 0: PORTB7~0 pull-hi are enable 1: PORTB7~0 pull-hi are disable WDT rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 Preliminary http://www.mxmcu.com.cn P.11 2010/8 Ver. 0.3 MDT14F201 (26) CPIO A (Control Port I/O Mode Register): R85 “0”, I/O pin in output mode; “1”, I/O pin in input mode. (27) CPIO B (Control Port I/O Mode Register): R86 “0”, I/O pin in output mode; “1”, I/O pin in input mode. (28) CPIO C (Control Port I/O Mode Register): R87 “0”, I/O pin in output mode; “1”, I/O pin in input mode. (29) CPIO D (Control Port I/O Mode Register): R88 “0”, I/O pin in output mode; “1”, I/O pin in input mode. (30) TTLCTL1: R89 Bit Symbol 0 TTLMOD 1 OVLEN 3~2 7~4 Function 0: Disable TTL MODE 1: Enable TTL MODE Over load protect enable Clock input division PRDIV1~0 00=Fosc/2; 01=Fosc/4; 10=Fosc/8; 11=Fosc/16 Delay time set 0000 : 0 clock 0001 : 1 clock PRSCL3~0 0010 : 2 clocks : 1111 : 15 clocks Preliminary http://www.mxmcu.com.cn P.12 2010/8 Ver. 0.3 MDT14F201 (31) PIEB1: R8C Bit Symbol 0 TMR1IE Function TMR1 interrupt enable bit 0: Disable TMR1 interrupt 1: Enable TMR1 interrupt 1 TMR2IE TMR2 interrupt enable bit 0: Disable TMR2 interrupt 1: Enable TMR2 interrupt 2 CCP1IE CCP1 interrupt enable bit 0: Disable CCP1 interrupt 1: Enable CCP1 interrupt 5~3 -- 6 ADIE Unimplemented A/D interrupt enable bit 0: Disable A/D interrupt 1: Enable A/D interrupt 7 -- Unimplemented (32) PSTA: R8E Bit Symbol Function 0 PEDHB 0: Power-edge detector high level reset occurred 1: No Power-edge detector high level reset occurred 1 PORB 0: Power on Reset occurred 1: No Power on Reset occurred 7~2 -- Unimplemented (33) PAPHR: R8F PAPHR Bit 7 PHA7 Bit 6 PHA6 Bit 5 PHA5 Bit 4 - Bit 3 PHA3 Bit 2 PHA2 Bit 1 PHA1 Bit 0 PHA0 Bit 5 PHB5 Bit 4 PHB4 Bit 3 PHB3 Bit 2 PHB2 Bit 1 PHB1 Bit 0 PHB0 Port A Pull_hi Control Bits 0 = Pull_hi disable 1 = Pull_hi enable (34) PBPHR: R90 PBPHR Bit 7 PHB7 Bit 6 PHB6 Port B Pull_hi Control Bits 0 = Pull_hi disable 1 = Pull_hi enable (35) T2PER: R92 Timer2 period Preliminary http://www.mxmcu.com.cn P.13 2010/8 Ver. 0.3 MDT14F201 (36) PCPHR: R95 PCPHR Bit 7 PHC7 Bit 6 PHC6 Bit 5 PHC5 Bit 4 PHC4 Bit 3 PHC3 Bit 2 PHC2 Bit 1 PHC1 Bit 0 PHC0 Bit 5 - Bit 4 - Bit 3 PHD3 Bit 2 PHD2 Bit 1 PHD1 Bit 0 PHD0 Bit 4 EED4 Bit 3 EED3 Bit 2 EED2 Bit 1 EED1 Bit 0 EED0 Bit 4 EEAD4 Bit 3 EEAD3 Bit 2 EEAD2 Bit 1 EEAD1 Bit 0 EEAD0 Bit 4 - Bit 3 WRERR Bit 2 WREN Bit 1 WR Bit 0 RD Port C Pull_hi Control Bits 0 = Pull_hi disable 1 = Pull_hi enable (37) PDPHR: R96 PDPHR Bit 7 - Bit 6 - Port D Pull_hi Control Bits 0 = Pull_hi disable 1 = Pull_hi enable (38) EEDATA(EEPROM data register.):R9A EEDATA Bit 7 EED7 Bit 6 EED6 Bit 5 EED5 (39) EEADR (EEPROM address register):R9B. EEADR Bit 7 - Bit 6 EEAD6 Bit 5 EEAD5 (40) EECON (EEPROM control register 1):R9C. EECON1 Bit 7 - Bit 6 - Bit 5 - WRERR : EEPROM Write Error Flag Bit. 0 = The EEPROM write operation completed 1 = The EEPROM write operation is prematurely terminated (any MCLR reset or any WDT reset during normal operation) WREN : EEPROM Write Enable Bit. 0 = Inhibits write to the data EEPROM 1 = Allows write cycles WR : Write Control Bit. 0 = Write cycle to the data EEPROM is complete 1 = Initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only be set (not clear) in software.) RD : Read Control Bit. 0 = Does not initiate an EEPROM read. 1 = Initiates an EEPROM read (read takes once cycle. RD is cleared in hardware. The RD bit can only be set (not clear) in software.) (41) EECON2(EEPROM control register 2): R9D. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EECON2 Write only ; Read as “0” When write data to the EEPROM must write 55/H to EECCON2, and writ AA/H to EECCON2 then set WR bit; the EEPROM can write data inside for write each byte. Preliminary http://www.mxmcu.com.cn P.14 2010/8 Ver. 0.3 MDT14F201 Example : Data EEPROM Write BSR BCR BSR LDWI STWR LDWI STWR BSR STATUS, PAGE INTS, GIS EECON1, WREN 55H EECON2 0AAH EECON2 EECON1, WR ; Select bank1 ; Disable interrupt ; Enable write ; Write 55/H ; Write AA/H ; Begin write (42) ADS1 (A/D Status Register): R9F Bit 2~0 Symbol PAVM2~0 Function 0 0 0: PA0~3,PA5 = analog input, PA6~7 = analog input, VREF = VDD 0 0 1: PA0~2,PA5 = analog input, PA6~7 = analog input, VREF = PA3 0 1 0: PA0~3,PA5 = analog input, PA6~7 = digital input, VREF = VDD 0 1 1: PA0~2,PA5 = analog input, PA6~7 = digital input, VREF = PA3 1 0 0: PA0, 1, 3 = analog input, PA2, 5 = digital I/O, PA6~7 = digital input, VREF = VDD 1 0 1: PA0, 1 = analog input, PA2, 5 = digital I/O, PA6~7 = digital input, VREF = PA3 1 1 x PA0~3, 5 = digital I/O 7~3 -- Unimplemented Preliminary http://www.mxmcu.com.cn P.15 2010/8 Ver. 0.3 MDT14F201 Configurable options for FLASH ROM (Set by writer) Oscillator Type MDT14F201 P12/S12/K12/LQ12 RC Oscillator MDT14F201 P11/S11/K11/LQ11 IRC 16M Oscillator HFXT Oscillator XTAL Oscillator LFXT Oscillator Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time Power-edge Detect Power-edge Detect disable Low level around 1.8V Middle level around 2.1V High level around 3.8V Oscillator-start Timer control 0ms 75ms Security state Security Disable Security Enable (B) Program Memory Address 000-FFF Description Program memory 000 The starting address of power on, external reset or WDT time-out reset. 004 Interrupt vector Preliminary http://www.mxmcu.com.cn P.16 2010/8 Ver. 0.3 MDT14F201 7. Reset Condition for all Registers Register Address Power-On Reset, Power edge detector high level Reset /MCLR or WDT Reset Wake-up from SLEEP IAR 00h N/A N/A N/A RTCC 01h xxxx xxxx uuuu uuuu uuuu uuuu 0Ah,02h 0000 0000 0000 0000 0000 0000 PC+1 STATUS 03h 0001 1xxx 000# #uuu 000# #uuu MSR 04h xxxx xxxx uuuu uuuu uuuu uuuu PORT A 05h --xx xxxx --uu uuuu --uu uuuu PORT B 06h xxxx xxxx uuuu uuuu uuuu uuuu PORT C 07h xxxx xxxx uuuu uuuu uuuu uuuu PORT D 08h ---- xxxx ---- uuuu ---- uuuu TTLCTL0 09h 0000 0000 0000 0000 uuuu uuuu PCHLAT 0Ah ---0 0000 ---0 0000 ---u uuuu INTS 0Bh 0000 000x 0000 000u uuuu uuuu PIFB1 0Ch -0-- -000 -0-- -000 -u-- -uuu TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1STA 10h --00 0000 --uu uuuu --uu uuuu TMR2 11h 0000 0000 0000 0000 uuuu uuuu T2STA 12h ---- -000 ---- -uuu ---- -uuu DBCTL 13h 0000 0000 0000 0000 uuuu uuuu CCP1L 15h xxxx xxxx uuuu uuuu uuuu uuuu CCP1H 16h xxxx xxxx uuuu uuuu uuuu uuuu CCP1CTL 17h --00 0000 --00 0000 --uu uuuu ADRES 1Eh xxxx xxxx uuuu uuuu uuuu uuuu ADS0 1Fh 0000 00-0 0000 00-0 uuuu uu-u TMR 81h 1111 1111 1111 1111 uuuu uuuu CPIOA 85h --11 1111 --11 1111 --uu uuuu CPIOB 86h 1111 1111 1111 1111 uuuu uuuu CPIOC 87h 1111 1111 1111 1111 uuuu uuuu CPIOD 88h ---- 1111 ---- 1111 ---- uuuu PC Preliminary http://www.mxmcu.com.cn P.17 2010/8 Ver. 0.3 MDT14F201 Register Address Power-On Reset, Power range detector Reset /MCLR or WDT Reset Wake-up from SLEEP TTLCTL1 89h 0000 0000 0000 0000 uuuu uuuu PIEB1 8Ch -0-- -000 -0-- -000 -u-- -uuu PSTA 8Eh ---- --0u ---- --uu ---- --uu T2PER 92h 1111 1111 1111 1111 1111 1111 ADS1 9Fh ---- -000 ---- -000 ---- -uuu Note : uunchanged, xunknown, - unimplemented, read as “0” #value depends on the condition of the following table Condition Status: bit 4 Status: bit 3 PSTA: bit 1 PSTA: bit 0 /MCLR reset (not during SLEEP) u u u u /MCLR reset during SLEEP 1 0 u u WDT reset (not during SLEEP) 0 1 u u WDT reset during SLEEP 0 0 u u Power-on reset 1 1 0 x Power-edge high level reset 1 1 u 0 Note : uunchanged, xunknown, - unimplemented, read as “0” Preliminary http://www.mxmcu.com.cn P.18 2010/8 Ver. 0.3 MDT14F201 8. Instruction Set Mnemonic Operands Instruction Code Function Operating Status 010000 00000000 NOP No operation None 010000 00000001 CLRWT Clear Watchdog timer 0WT TF, PF 010000 00000010 SLEEP Sleep mode 0WT, stop OSC TF, PF 010000 00000011 TMODE Load W to TMODE register W TMODE None 010000 00000100 RET Return from subroutine StackPC None 010000 00000rrr CPIO Control I/O port register W CPIO 010001 1rrrrrrr STWR R Store W to register W R 011000 trrrrrrr LDR R, t Load register Rt Z 111010 iiiiiiii LDWI Load immediate to W i W None 010111 trrrrrrr SWAPR R, t Swap halves register [R(0~3) ↔R(4~7)] t None 011001 trrrrrrr INCR R, t Increment register R + 1t Z 011010 trrrrrrr INCRSZ R, t Increment register, skip if zero R + 1t None 011011 trrrrrrr ADDWR R, t Add W and register W + Rt C, HC, Z 011100 trrrrrrr SUBWR R, t Subtract W from register R W t or (R+/W+1t) C, HC, Z 011101 trrrrrrr DECR R, t Decrement register R 1t Z 011110 trrrrrrr DECRSZ R, t Decrement register, skip if zero R 1t None 010010 trrrrrrr ANDWR R, t AND W and register R W t Z 110100 iiiiiiii ANDWI AND W and immediate i W W Z 010011 trrrrrrr IORWR R, t Inclu. OR W and register R W t Z 110101 iiiiiiii IORWI Inclu. OR W and immediate i W W Z 010100 trrrrrrr XORWR R, t Exclu. OR W and register R W t Z 110110 iiiiiiii XORWI Exclu. OR W and immediate i W W Z 011111 trrrrrrr COMR R, t Complement register /Rt Z 010110 trrrrrrr RRR R, t Rotate right register R(n) R(n-1), CR(7), R(0)C C 010101 trrrrrrr RLR R, t Rotate left register R(n)r(n+1), CR(0), R(7)C C 010000 1xxxxxxx CLRW Clear working register 0W Z 010001 0rrrrrrr CLRR Clear register 0R Z 0000bb brrrrrrr BCR R, b Bit clear 0R(b) None 0010bb brrrrrrr BSR R, b Bit set 1R(b) None 0001bb brrrrrrr BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None R i i i i R R None None Preliminary http://www.mxmcu.com.cn P.19 2010/8 Ver. 0.3 MDT14F201 Mnemonic Operands Instruction Code Function Operating Status 100nnn nnnnnnnn LCALL n Long CALL subroutine nPC, PC+1Stack None 101nnn nnnnnnnn LJUMP n Long JUMP to address nPC None 110111 iiiiiiii ADDWI Add immediate to W W+iW 110001 iiiiiiii RTWI i Return, place immediate to W StackPC,iW 111000 iiiiiiii SUBWI i Subtract W from immediate i-W W 010000 00001001 RTFI Return from interrupt StackPC,1GIS Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : i Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ‘’ Exclusive ‘’ Logic AND ‘’ b t : : 0 1 R : C : HC : Z : / : x : i : n : C,HC,Z None C,HC,Z None Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don’t care Immediate data ( 8 bits ) Immediate address Preliminary http://www.mxmcu.com.cn P.20 2010/8 Ver. 0.3