CY5057 High-Frequency Flash Programmable PLL Die with Spread Spectrum Features Benefits ■ Flash programmable die for in-package programming of crystal oscillators ■ ■ High resolution phase-locked loop (PLL) with 10-bit multiplier and 7-bit divider Enables quick turnaround of custom oscillators and lowers inventory costs through stocking blank parts. In addition, the part may be Flash programmed up to 100 times. This reduces programming errors and provides an easy upgrade path for existing designs. ■ Flash programmable capacitor tuning array ■ ■ Simple 2-pin programming interface (excluding VDD and VSS pins) Enables synthesis of highly accurate and stable output clock frequencies with zero or low PPM. ■ ■ On-chip oscillator used with external 25.1 MHz fundamental tuned crystal Enables fine tuning of output clock frequency by adjusting the CLoad of the crystal. ■ Allows the device to go into standard 4 or 6-pin packages. ■ Flash programmable spread spectrum with spread percentages between +0.25% and +2.00% ■ Lowers cost of oscillator, because PLL may be programmed to a high frequency using a low frequency, low cost crystal. ■ Spread spectrum on/off function ■ Provides various spread percentage. ■ Operating frequency ❐ 5–170 MHz at 3.3V ± 10% ■ Provides the ability to enable or disable Spread Spectrum with an external pin. ■ Seven-bit linear post divider with divide options from divide-by-2 to divide-by-127 ■ Provides flexibility in output configurations and testing. ■ Programmable PD# or OE pin ■ Enables low operation or output enable function. ■ Provides flexibility for system applications through selectable instantaneous or synchronous change in outputs. ■ Suitable for most PC, consumer, and networking applications. ■ Has lower EMI than oscillators. ■ Easy to use software support for design entry. ■ Programmable asynchronous or synchronous OE and PD# modes ■ Low jitter output ❐ < 200 ps (pk-pk) at 3.3V ± 10% ■ Controlled rise and fall times and output slew rate ■ Software configuration support Die Pad Description Horizontal scribe 1 VDD SSON# 10 2 VDD OUT 9 3 XOUT Note Active die size: X = 75.0 mils / 1907 μm Y = 56.2 mils / 1428 μm Scribe: X (horizontal) = 2.8 mils / 71 μm Y (vertical) = 3.4 mils / 86.2 μm Bond pad opening: 85 μm x 85 μm Pad pitch: 125 μm x 125 μm (pad center to pad center) Wafer thickness: 11 mils TYPICAL NC 8 Y Vertical scribe 4 XIN VSS 7 5 PD#/OE VSS 6 X Cypress Semiconductor Corporation Document Number: 38-07363 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 10, 2008 [+] Feedback CY5057 Block Diagram XIN XOUT SSON# Crystal Osc with 8-bit Cap Array 7-bit ÷Q 10-bit ÷P 100- to 400-MHz PLL 7-bit Output Divider Block OUT Spread Spectrum PD#/OE Flash Configuration/ Spread Spectrum Storage Die Pad Summary Pad coordinates are referenced from the center of the die (X = 0, Y = 0) Table 1. Die Pad Summary Name Die Pad Description X Coordinate Y Coordinate –843.612 597.849, 427.266 VDD 1,2 Power supply. VSS 6,7 Ground. XIN 4 Crystal gate pin. –843.612 XOUT 3 Crystal drain pin. –843.612 236.565 PD#/OE 5 Flash programmable to function as power down or output enable in normal operating mode. Weak pull up is enabled by default. –843.612 –424.662 834.183 589.848 VPP –1.806 Super voltage when going into programming mode. SDA SSON# 883.743, 887.355 –563.304, –369.957 Data pin when going into and when in programming mode. 10 SCL Active low spread spectrum control. Asserting LOW turns the internal modulation waveform on. Strong pull down is enabled by default. Pull down is disabled in power down mode. Clock pin in programming mode. Must be double bonded to the OUT pad for pinouts not using the SSON# function. There is an internal pull down resistor on this pad. OUT 9 Clock output. There is an internal pull down resistor on this pad. Weak pull down is enabled by default. Default output is from the reference. 834.183 462.840 NC 8 No connect pin (do not connect this pad). 834.183 335.832 Document Number: 38-07363 Rev. *C Page 2 of 10 [+] Feedback CY5057 Functional Description CY5057 is a Flash programmable, high accuracy, PLL-based die designed for the crystal oscillator market. It also contains spread spectrum circuitry that is enabled or disabled with an external pin. The die is integrated with a low cost 25.1 MHz fundamental tuned crystal in a four or six pin through hole or surface mount package. The oscillator devices may be stocked as blank parts and custom frequencies programmed in-package at the last stage before shipping. This enables faster manufacturing of custom and standard crystal oscillators without the need for dedicated and expensive crystals. CY5057 contains an on-chip oscillator and unique oscillator tuning circuit for fine tuning the output frequency. The crystal Cload is selectively adjusted by programming a set of Flash memory bits. This feature is used to compensate for crystal variations or to obtain a more accurate synthesized frequency. CY5057 uses a simple two-pin programming interface excluding the VSS and VDD pins. Clock outputs are generated from 5 MHz to 170 MHz at 3.3V ± 10% operating voltage. You can reprogram the entire Flash configuration multiple times, to alter or reuse the programmed inventory. CY5057 PLL die is designed for very high resolution. It has a 10-bit feedback counter multiplier and a 7-bit reference counter divider. This enables the synthesis of highly accurate and stable output clock frequencies with zero or low PPM error. The output of the PLL or the oscillator is further modified by a 7-bit linear post divider with a total of 126 divider options (2 to 127). CY5057 also contains flexible power management controls. These parts include both power down mode (PD# = 0) and output enable mode (OE = 1). The power down and output enable modes have an additional setting to determine timing (asynchronous or synchronous) with respect to the output signal. Controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enables CY5057 to have low jitter and accurate outputs. This makes it suitable for most PC, networking, and consumer applications. Flash Configuration and Spread Spectrum Storage Block The following table summarizes the features configurable by the Flash memory bits. Refer to “CY5057 Programming Specification” for programming details. The specification can be obtained from your Cypress factory representative. Table 2. Flash Programmable Features Adjust Frequency Feedback counter value (P) Reference counter value (Q) Output divider selection Oscillator tuning (load capacitance values) Oscillator direct output Power management mode (OE or PD#) Power management timing (synchronous or asynchronous) Spread spectrum PLL Output Frequency CY5057 contains a high resolution PLL with a 10-bit multiplier and a 7-bit divider. The output frequency of the PLL is determined by the following formula: 2 • ( P BL + 4 ) + Po F PLL = ------------------------------------------------ • F REF (QL + 2) In this formula: ■ QL is the loaded or programmed reference counter value (Q counter) ■ PBL is the loaded or programmed feedback counter value (P counter) ■ Po is the P offset bit (is only 0 or 1) In spread spectrum mode, the time averaged P value is used to calculate the average frequency. CY5057 also has an additional spread spectrum feature that is disabled or enabled with an external pin. See Spread Spectrum on page 4 for details. Document Number: 38-07363 Rev. *C Page 3 of 10 [+] Feedback CY5057 Power Management Features edge at the output before power down or output enable signal initiated, thus preventing output glitches. In asynchronous or synchronous setting, the output is always enabled synchronously by waiting for the next falling edge of the output. CY5057 contains Flash programmable PD# (active LOW) and OE (active HIGH) functions. If power down mode is selected (PD# = 0), the oscillator and PLL are placed in a low supply current standby mode and the output is tri-stated and weakly pulled low. The oscillator and PLL circuits must relock when the part leaves power down mode. If output enable mode is selected (OE = 0), the output is tri-stated and weakly pulled low. In this mode the oscillator and PLL circuits continue to operate allowing a rapid return to normal operation when the output is enabled. Spread Spectrum CY5057 contains spread spectrum with Flash programmable spread percentage and modulation frequency. Center spread nonlinear “Hershey kiss” modulation is obtained. Spread percentage is programmed to values between +0.250% and +2.00%, in 0.25% intervals. Only one spread profile (for one specific percentage spread and for one output frequency) may be programmed into the device at a time. In addition, the PD# and OE modes may be programmed to occur synchronously or asynchronously with respect to the output signal. When the asynchronous setting is used, the power down or output disable occurs immediately (allowing for logic delays) irrespective of the position in the clock cycle. However, when the synchronous setting is used, the part waits for a falling CY5057 has a spread spectrum on and off function. The spread spectrum is enabled or disabled through an external pin. Timing this feature is explained in Switching Waveforms on page 7. Figure 1. Crystal Oscillator Tuning Circuit RF XIN XOUT CXOUT CXIN C7 C6 C5 C4 C3 C2 Table 3. Crystal Oscillator Tuning Cap Values Bit[1] C7 (MSB) 24.32 C6 12.16 C5 6.08 C4 3.04 C3 1.52 C2 0.76 C1 0.38 C0 (LSB) 0.19 C1 C0 C0 C1 C2 C3 C4 C5 C6 C7 Capacitance per Bit (pF) Note 1. CXIN, CXOUT, and parasitic capacitance due to fixture and package should be included when calculating the total capacitance. Document Number: 38-07363 Rev. *C Page 4 of 10 [+] Feedback CY5057 Inkless Die Pick Map (DPM) Format Absolute Maximum Ratings Cypress ships inkless wafers to customers with an accompanying die pick map, which is used to determine the good die for assembly and programming. Customers can also access individual DPM files at their convenience via ftp.cypress.com with a valid user account login and password. Contact your local Cypress Field Application Engineer (FAE) or sales representative for a customer FTP account. The DPM files are named using the fab lot number and wafer number scribed on the wafer. The DPM files are transferred to the customer’s FTP account when the factory ships out the wafers against their purchase order (PO). Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Supply voltage ................................................. –0.5 to +7.0V Input voltage .............................................–0.5V to VDD + 0.5 Storage temperature (non condensing) ...... –55°C to +125°C Junction temperature................................. –40°C to +125°C Data retention at Tj = 125°C..................................> 10 years Maximum non volatile programming cycles......................100 Static discharge voltage........................................... > 2000V (per MIL-STD-883, method 3015) Output (pad 9) sink or sources current ........20 mA maximum Operating Conditions Parameter Min Max Unit Supply voltage (3.3V) 3.0 3.6 V TAJ Operating temperature, junction –40 100 °C CLC Maximum capacitive load on the output (CMOS levels spec) VDD = 3.0V–3.6V, output frequency = 5–170 MHz XREF Reference frequency with spread spectrum disabled. Fundamental tuned crystals only Cin Input capacitance (except crystal pins) -- 7 pF CXIN Crystal input capacitance (all internal caps off) 10 14 pF VDD [2] Description CXout Crystal output capacitance (all internal caps off) T_PSRT Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) -- 15 pF 25.1 25.1 MHz 10 14 pF 0.005 500 ms Note 2. In Cypress standard TSSOP packages with external crystal. Document Number: 38-07363 Rev. *C Page 5 of 10 [+] Feedback CY5057 DC Electrical Characteristics Tj = –40 to 100°C Parameter VIL VIH VOL VOH IILPDOE IIHPDOE IILSR IIHSR IDD IOZ IPD RUP RDN Rf Description Input low voltage PD#/OE and SSON# pins Input high voltage PD#/OE and SSON# pins Output low voltage, OUT pin Output high voltage, CMOS levels Input low current, PD#/OE pin Input high current, PD#/OE pin Input low current, SSON# pin Input high current, SSON# pin Supply current Output leakage current, OUT pin Standby current Pull up resistor on PD#/OE pin Pull down resistor on SSON# and OUT pins Crystal feedback resistor Test Conditions CMOS levels, 30% of VDD VDD = 3.0V–3.6V Min -- CMOS levels, 70% of VDD VDD = 3.0V–3.6V 0.7* VDD VDD = 3.0V–3.6V, IOL = 8 mA VDD = 3.0V–3.6V, IOH = –8 mA Max 0.3* VDD Unit V V 0.4 V VDD – 0.4 -- V -- 10 μA -- 10 μA -- 10 μA VIN = VSS (Internal pull up = 3MΩ typical) VIN = VDD (Internal pull up = 100kΩ typical) VIN = VSS (Internal pull down = 100kΩ typical) VIN = VDD (Internal pull down = 100kΩ typical) No Load, VDD = 3.0V–3.6V, Fout = 170 MHz VDD = 3.0V–3.6V, output disabled with OE -- 50 μA --- 50 50 mA μA VDD = 3.0V–3.6V, device powered down with PD# VDD = 3.0 to 3.6V, measured at VIN =VSS VDD = 3.0V–3.6V, measured at VIN = 0.7VDD VDD = 3.0V–3.6V, measured at VIN = 0.5VDD -1 80 80 50 6 150 150 μA MΩ kΩ kΩ VDD = 3.0V–3.6V, measured at XIN = 0. 100 -- kΩ Min 5 --45 40 -- 30 -- Max 170 2.7 2.7 55 60 200 400 1% of 1/Fout 200 400 1% of 1/Fout 33 540 Unit MHz ns ns % % ps ps s ps ps s kHz μW -- –140 Ω AC Electrical Characteristics Tj = –40 to 100°C Parameter[2] Fout tr tf DC tJ1 tJ2 FMOD DL –R Description Output frequency OUT rise time OUT fall time OUT duty cycle Test Conditions VDD = 3.0 to 3.6V, CL = 15 pF VDD = 3.0V–3.6V, 20% to 80% VDD, CL = 15 pF VDD = 3.0V–3.6V, 80% to 20% VDD, CL = 15 pF Divider output, measured at VDD/2 Crystal direct output, measured at VDD/2 Peak to peak period jitter Fout >133 MHz, VDD/2, SS off 25 MHz < Fout< 133 MHz, VDD/2, SS off Fout< 25 MHz, VDD/2, SS off Cycle-to-cycle jitter Fout >133 MHz, VDD/2, SS on 25 MHz < Fout< 133 MHz, VDD/2, SS on Fout< 25 MHz, VDD/2, SS on Modulation frequency Crystal drive level Measured at 25.1 MHz, with crystal ESR = 20Ω, cap setting = hex16, DL = program code [1,0] Negative resistance Measured at 25.1 MHz, cap setting = hex FF Document Number: 38-07363 Rev. *C -- Page 6 of 10 [+] Feedback CY5057 Timing Parameters[2] Parameter Description Min Max Unit -- 600 μs -- 100 μs 250 -- μs 30 33.33 μs -- 1.5T + 350 ns TSTP,ASYNC Time from falling edge on PD# to stopped outputs, asynchronous mode -- 350 ns TPU,SYNC Time from rising edge on PD# to outputs at valid frequency, synchronous mode -- 3 ms TPU,ASYNC Time from rising edge on PD# to outputs at valid frequency, asynchronous mode -- 3 ms TPXZ,SYNC Time from falling edge on OE to high-impedance outputs, synchronous mode, T = 1/Fout -- 1.5T+350 ns TSSON1 Time from steady state spread to steady state non spread TSSON2 Time from steady state non-spread to steady state spread TSSON3 Minimum SSON# pulse width (positive or negative) TMOD Spread spectrum modulation period TSTP,SYNC Time from falling edge on PD# to stopped outputs, synchronous mode, T = 1/Fout TPXZ,ASYNC Time from falling edge on OE to high-impedance outputs, asynchronous mode -- 350 ns TPZX,SYNC -- 1.5T + 350 ns TPZX,ASYNC Time from rising edge on OE to running outputs, asynchronous mode -- 350 ns TLOCK -- 10 ms Time from rising edge on OE to running outputs, synchronous mode, T=1/Fout PLL lock time (from 0.9 VDD to valid output clock frequency) Switching Waveforms Figure 2. Duty Cycle Timing (dc) t1A t1B t 1A Duty = -------- × [ 100% ] t 1B OUTPUT Figure 3. Output Rise/Fall Time VDD OUTPUT 0V tr Document Number: 38-07363 Rev. *C tf Page 7 of 10 [+] Feedback CY5057 Figure 4. Power Down Timing (Synchronous and Asynchronous Modes) VIL High Impedance Weakly Pulled Low TSTP TPU High Impedance Weakly Pulled Low TSTP TPU Figure 5. Output Enable Timing (Synchronous and Asynchronous Modes) VIH VIL High Impedance Weakly Pulled Low TPXZ TPZX High Impedance Weakly Pulled Low TPXZ TPZX Figure 6. Power Up Timing .9 V D D T PSRT Pow er U p 0v C LK O U T Document Number: 38-07363 Rev. *C T LO C K V a lid C L K O U T Page 8 of 10 [+] Feedback CY5057 Figure 7. Spread Spectrum On and OFF Timing SSON# T SSON3 +100% Internal Modulation W aveform T SSON1 T SSON2 0% -100% Ordering Information Ordering Code Status Type Operating Range CY5057-11WAF Obsolete Inked Wafer (background to 11 mils) –40°C to 100°C CY5057-11WAF-IL Active Inkless Wafer (background to 11 mils) –40°C to 100°C Document Number: 38-07363 Rev. *C Page 9 of 10 [+] Feedback CY5057 Document History Page Document Title: CY5057 High-Frequency Flash Programmable PLL Die with Spread Spectrum Document Number: 38-07363 REV. ECN NO. Orig. of Change ** 112486 CKN New data sheet *A 121373 CKN Added scribe lines to die pad description Added wafer thickness to die pad description Added X and Y coordinates to die pad description Removed list of discrete frequencies and discrete spread percentages Removed references to discrete frequencies and profile tables Replaced with description of software for full programmability Operating frequency changed to 5 MHz–170 MHz Removed C0 and C1 from crystal oscillator tuning circuit; renumbered other capacitors Changed maximum junction temperature to 125°C Changed PDOE internal pull up value to 1–6 Mohm when VIN = VSS Changed IILPDOE to 10 μA Changed Rf spec to 100 kohm, at condition XIN = 0 Change DL spec to 540 μW, at condition cap setting = hex16, DL=10 Added power up timing diagram separate from power down timing diagram Removed die information table *B 127414 RGL Added –11 and other details to ordering Information Added tPU details to operating conditions Changed max TSSON1 value to 600 in timing parameters table Changed parameter TPU under timing parameters to TLOCK with the description “PLL lock time” Altered minimum and maximum values in power up timing figure *C 2143928 Description of Change FGA/PYRS Modified power down timing diagram Changed power up timing from min. of 50 μs to 5 μs Added output sink/source current specification in the absolute max ratings Change cap array from 10 to 8-bit Add MSB and LSB in the crystal oscillator tuning cap values table Fixed power up timing diagram Added -R cap setting value FF Added Inkless die information before Absolute Maximum Ratings Added new part number (CY5057-11WAF-IL) with note © Cypress Semiconductor Corporation, 2002-2008. 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Document Number: 38-07363 Rev. *C Revised March 10, 2008 Page 10 of 10 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback